Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AR-LV25UG256PC2/I1
Device GW5AR-25
Device Version A
Created Time Thu Oct 24 16:06:21 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C2/I1
Hold Delay Model Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed 12569
Numbers of Endpoints Analyzed 11844
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 mem_clk Base 1.875 533.333 0.000 0.938 memory_clk
2 rao_clk Base 50.000 20.000 0.000 25.000 tck_pad_i
3 clkin Base 20.000 50.000 0.000 10.000 clk
4 userclk Generated 7.500 133.333 0.000 3.750 memory_clk mem_clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 mem_clk 533.333(MHz) 2338.896(MHz) 1 TOP
2 rao_clk 20.000(MHz) 151.555(MHz) 6 TOP
3 clkin 50.000(MHz) 323.572(MHz) 2 TOP
4 userclk 133.333(MHz) 133.480(MHz) 3 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
mem_clk Setup 0.000 0
mem_clk Hold 0.000 0
rao_clk Setup 0.000 0
rao_clk Hold 0.000 0
clkin Setup 0.000 0
clkin Hold 0.000 0
userclk Setup 0.000 0
userclk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.008 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CEA userclk:[R] userclk:[R] 7.500 0.033 7.392
2 0.097 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CEA userclk:[R] userclk:[R] 7.500 0.025 7.311
3 0.133 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/D userclk:[R] userclk:[R] 7.500 -0.005 7.321
4 0.138 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CEA userclk:[R] userclk:[R] 7.500 0.018 7.277
5 0.158 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CEA userclk:[R] userclk:[R] 7.500 0.025 7.250
6 0.646 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_38_s0/D userclk:[R] userclk:[R] 7.500 -0.027 6.830
7 0.723 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/D userclk:[R] userclk:[R] 7.500 0.000 6.726
8 0.742 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_58_s0/D userclk:[R] userclk:[R] 7.500 -0.018 6.725
9 0.742 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_59_s0/D userclk:[R] userclk:[R] 7.500 -0.018 6.725
10 0.761 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CEA userclk:[R] userclk:[R] 7.500 0.025 6.647
11 0.789 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_39_s0/D userclk:[R] userclk:[R] 7.500 -0.023 6.683
12 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_24_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
13 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_25_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
14 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_50_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
15 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_51_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
16 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_56_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
17 0.894 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_57_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.571
18 0.917 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_16_s0/D userclk:[R] userclk:[R] 7.500 -0.030 6.563
19 0.917 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_17_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.548
20 0.917 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_61_s0/D userclk:[R] userclk:[R] 7.500 -0.030 6.563
21 0.928 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CEA userclk:[R] userclk:[R] 7.500 0.018 6.487
22 0.936 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_21_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.529
23 0.936 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_28_s0/D userclk:[R] userclk:[R] 7.500 -0.016 6.529
24 0.943 inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_63_s0/D userclk:[R] userclk:[R] 7.500 -0.023 6.529
25 0.947 inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CEA userclk:[R] userclk:[R] 7.500 0.033 6.453

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.155 inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0 userclk:[R] userclk:[R] 0.000 -0.002 0.239
2 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[5] userclk:[R] userclk:[R] 0.000 0.010 0.243
3 0.231 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[12] userclk:[R] userclk:[R] 0.000 0.013 0.255
4 0.235 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[3] userclk:[R] userclk:[R] 0.000 0.017 0.255
5 0.241 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/ADA[3] userclk:[R] userclk:[R] 0.000 0.021 0.257
6 0.242 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[7] userclk:[R] userclk:[R] 0.000 0.017 0.262
7 0.244 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/ADA[7] userclk:[R] userclk:[R] 0.000 0.021 0.260
8 0.256 inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_18_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D5 userclk:[R] userclk:[R] 0.000 -0.006 0.333
9 0.264 inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_17_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D6 userclk:[R] userclk:[R] 0.000 -0.002 0.348
10 0.264 inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_19_s0/Q inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D4 userclk:[R] userclk:[R] 0.000 -0.002 0.348
11 0.272 gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q gw_gao_inst_0/u_la0_top/rst_ao_s0/D userclk:[F] userclk:[F] 0.000 0.000 0.236
12 0.275 gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q gw_gao_inst_0/u_la0_top/address_counter_2_s0/D rao_clk:[R] rao_clk:[R] 0.000 0.000 0.300
13 0.275 inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/Q inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/D userclk:[R] userclk:[R] 0.000 0.000 0.300
14 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/Q inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/D userclk:[R] userclk:[R] 0.000 0.000 0.300
15 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/Q inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/D userclk:[R] userclk:[R] 0.000 0.000 0.300
16 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/Q inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/D userclk:[R] userclk:[R] 0.000 0.000 0.300
17 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
18 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/Q inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
19 0.275 u_test/addr_20_s0/Q u_test/addr_20_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
20 0.275 inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/Q inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
21 0.275 inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/Q inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
22 0.275 inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/Q inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/D userclk:[R] userclk:[R] 0.000 0.000 0.300
23 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/Q inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/D userclk:[R] userclk:[R] 0.000 0.000 0.300
24 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/Q inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/D userclk:[R] userclk:[R] 0.000 0.000 0.300
25 0.275 inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/Q inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/D userclk:[R] userclk:[R] 0.000 0.000 0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.973 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.028 2.471
2 0.973 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.028 2.471
3 1.236 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.010 2.226
4 1.236 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.010 2.226
5 1.236 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.010 2.226
6 1.261 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.002 2.209
7 1.261 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.002 2.209
8 1.261 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.002 2.209
9 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
10 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
11 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
12 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
13 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
14 1.277 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR userclk:[F] userclk:[R] 3.750 0.016 2.179
15 1.332 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR userclk:[F] userclk:[R] 3.750 -0.005 2.145
16 1.332 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR userclk:[F] userclk:[R] 3.750 -0.005 2.145
17 1.332 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR userclk:[F] userclk:[R] 3.750 -0.005 2.145
18 1.375 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR userclk:[F] userclk:[R] 3.750 0.011 2.085
19 1.375 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.011 2.085
20 1.375 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.011 2.085
21 1.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.026 1.931
22 1.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.026 1.931
23 1.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.026 1.931
24 1.515 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.026 1.931
25 1.526 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR userclk:[F] userclk:[R] 3.750 0.021 1.925

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.875 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLEAR clkin:[R] clkin:[R] 0.000 0.006 0.816
2 0.875 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.006 0.816
3 0.875 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.006 0.816
4 0.879 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR clkin:[R] clkin:[R] 0.000 0.010 0.816
5 0.879 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR clkin:[R] clkin:[R] 0.000 0.010 0.816
6 0.879 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR clkin:[R] clkin:[R] 0.000 -0.004 0.830
7 0.879 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_12_s1/CLEAR clkin:[R] clkin:[R] 0.000 0.010 0.816
8 0.879 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_15_s1/CLEAR clkin:[R] clkin:[R] 0.000 -0.004 0.830
9 0.882 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/PRESET clkin:[R] clkin:[R] 0.000 -0.023 0.852
10 0.882 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.023 0.852
11 0.882 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.018 0.847
12 0.883 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR clkin:[R] clkin:[R] 0.000 -0.000 0.830
13 0.883 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_8_s1/CLEAR clkin:[R] clkin:[R] 0.000 -0.000 0.830
14 0.883 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_9_s1/CLEAR clkin:[R] clkin:[R] 0.000 -0.000 0.830
15 0.883 u_reset_key/key_1_s0/Q inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_14_s1/CLEAR clkin:[R] clkin:[R] 0.000 -0.000 0.830
16 0.885 u_reset_key/key_1_s0/Q led_lch_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
17 0.885 u_reset_key/key_1_s0/Q led_cnt_1_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
18 0.885 u_reset_key/key_1_s0/Q led_cnt_3_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
19 0.885 u_reset_key/key_1_s0/Q led_cnt_6_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
20 0.885 u_reset_key/key_1_s0/Q led_cnt_13_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
21 0.885 u_reset_key/key_1_s0/Q led_cnt_14_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
22 0.885 u_reset_key/key_1_s0/Q led_cnt_15_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
23 0.885 u_reset_key/key_1_s0/Q led_cnt_16_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
24 0.885 u_reset_key/key_1_s0/Q led_cnt_18_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833
25 0.885 u_reset_key/key_1_s0/Q led_cnt_22_s0/CLEAR clkin:[R] clkin:[R] 0.000 -0.001 0.833

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.040 2.902 0.862 Low Pulse Width userclk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
2 2.040 2.902 0.862 Low Pulse Width userclk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
3 2.040 2.902 0.862 Low Pulse Width userclk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s
4 2.040 2.902 0.862 Low Pulse Width userclk gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
5 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
6 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s
7 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s
8 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
9 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s
10 2.040 2.902 0.862 Low Pulse Width userclk inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.008
Data Arrival Time 8.960
Data Required Time 8.969
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.960 2.351 tNET RR 1 BSRAM_R10[8] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.036 1.536 tNET RR 1 BSRAM_R10[8] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA
8.969 -0.067 tSu 1 BSRAM_R10[8] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s

Path Statistics:

Clock Skew -0.033
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 7.860%; route: 6.505, 88.001%; tC2Q: 0.306, 4.140%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.536, 100.000%

Path2

Path Summary:

Slack 0.097
Data Arrival Time 8.879
Data Required Time 8.976
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.879 2.270 tNET RR 1 BSRAM_R10[7] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.043 1.543 tNET RR 1 BSRAM_R10[7] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKA
8.976 -0.067 tSu 1 BSRAM_R10[7] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s

Path Statistics:

Clock Skew -0.025
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 7.947%; route: 6.424, 87.868%; tC2Q: 0.306, 4.185%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.543, 100.000%

Path3

Path Summary:

Slack 0.133
Data Arrival Time 8.890
Data Required Time 9.023
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.335 2.107 tNET RR 1 R21C58[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s1/I1
6.704 0.369 tINS RR 2 R21C58[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s1/F
6.708 0.004 tNET RR 1 R21C58[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s5/I0
7.129 0.421 tINS RR 3 R21C58[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s5/F
7.135 0.006 tNET RR 1 R21C58[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s3/I1
7.548 0.413 tINS RR 2 R21C58[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s3/F
7.828 0.280 tNET RR 2 R22C59[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n70_s0/I1
8.278 0.450 tINS RF 1 R22C59[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n70_s0/COUT
8.477 0.199 tNET FF 1 R22C59[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_rempty_val_s1/I2
8.890 0.413 tINS FR 1 R22C59[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_rempty_val_s1/F
8.890 0.000 tNET RR 1 R22C59[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.074 1.574 tNET RR 1 R22C59[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/CLK
9.023 -0.051 tSu 1 R22C59[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0

Path Statistics:

Clock Skew 0.005
Setup Relationship 7.500
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 2.278, 31.116%; route: 4.737, 64.704%; tC2Q: 0.306, 4.180%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.574, 100.000%

Path4

Path Summary:

Slack 0.138
Data Arrival Time 8.845
Data Required Time 8.984
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.845 2.236 tNET RR 1 BSRAM_R10[10] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.051 1.551 tNET RR 1 BSRAM_R10[10] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA
8.984 -0.067 tSu 1 BSRAM_R10[10] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 7.984%; route: 6.390, 87.811%; tC2Q: 0.306, 4.205%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path5

Path Summary:

Slack 0.158
Data Arrival Time 8.819
Data Required Time 8.976
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.819 2.209 tNET RR 1 BSRAM_R10[9] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.043 1.543 tNET RR 1 BSRAM_R10[9] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKA
8.976 -0.067 tSu 1 BSRAM_R10[9] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s

Path Statistics:

Clock Skew -0.025
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 8.014%; route: 6.363, 87.766%; tC2Q: 0.306, 4.221%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.543, 100.000%

Path6

Path Summary:

Slack 0.646
Data Arrival Time 8.367
Data Required Time 9.014
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_38_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.946 1.701 tNET FF 1 R5C48[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n114_s0/I0
8.367 0.421 tINS FR 1 R5C48[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n114_s0/F
8.367 0.000 tNET RR 1 R5C48[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_38_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.064 1.564 tNET RR 1 R5C48[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_38_s0/CLK
9.014 -0.051 tSu 1 R5C48[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_38_s0

Path Statistics:

Clock Skew 0.027
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 13.778%; route: 5.583, 81.742%; tC2Q: 0.306, 4.480%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.564, 100.000%

Path7

Path Summary:

Slack 0.723
Data Arrival Time 8.295
Data Required Time 9.018
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.335 2.107 tNET RR 1 R21C58[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s1/I1
6.704 0.369 tINS RR 2 R21C58[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s1/F
6.968 0.264 tNET RR 1 R21C59[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_3_s2/I0
7.337 0.369 tINS RR 3 R21C59[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_3_s2/F
7.343 0.006 tNET RR 1 R21C59[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s3/I3
7.756 0.413 tINS RR 1 R21C59[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s3/F
7.882 0.126 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s0/I2
8.295 0.413 tINS RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s0/F
8.295 0.000 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.069 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
9.018 -0.051 tSu 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 7.500
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 1.776, 26.405%; route: 4.644, 69.045%; tC2Q: 0.306, 4.550%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%

Path8

Path Summary:

Slack 0.742
Data Arrival Time 8.262
Data Required Time 9.004
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_58_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.841 1.596 tNET FF 1 R6C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n94_s0/I0
8.262 0.421 tINS FR 1 R6C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n94_s0/F
8.262 0.000 tNET RR 1 R6C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_58_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.055 1.555 tNET RR 1 R6C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_58_s0/CLK
9.004 -0.051 tSu 1 R6C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_58_s0

Path Statistics:

Clock Skew 0.018
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 13.993%; route: 5.478, 81.457%; tC2Q: 0.306, 4.550%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.555, 100.000%

Path9

Path Summary:

Slack 0.742
Data Arrival Time 8.262
Data Required Time 9.004
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_59_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.841 1.596 tNET FF 1 R6C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n93_s0/I0
8.262 0.421 tINS FR 1 R6C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n93_s0/F
8.262 0.000 tNET RR 1 R6C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_59_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.055 1.555 tNET RR 1 R6C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_59_s0/CLK
9.004 -0.051 tSu 1 R6C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_59_s0

Path Statistics:

Clock Skew 0.018
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 13.993%; route: 5.478, 81.457%; tC2Q: 0.306, 4.550%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.555, 100.000%

Path10

Path Summary:

Slack 0.761
Data Arrival Time 8.215
Data Required Time 8.976
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.215 1.606 tNET RR 1 BSRAM_R10[23] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.043 1.543 tNET RR 1 BSRAM_R10[23] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA
8.976 -0.067 tSu 1 BSRAM_R10[23] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Path Statistics:

Clock Skew -0.025
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 8.741%; route: 5.760, 86.656%; tC2Q: 0.306, 4.604%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.543, 100.000%

Path11

Path Summary:

Slack 0.789
Data Arrival Time 8.220
Data Required Time 9.010
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_39_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.799 1.554 tNET FF 1 R7C48[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n113_s0/I0
8.220 0.421 tINS FR 1 R7C48[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n113_s0/F
8.220 0.000 tNET RR 1 R7C48[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_39_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.061 1.560 tNET RR 1 R7C48[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_39_s0/CLK
9.010 -0.051 tSu 1 R7C48[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_39_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.081%; route: 5.436, 81.340%; tC2Q: 0.306, 4.579%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path12

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_24_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n128_s0/I0
8.108 0.421 tINS FR 1 R7C53[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n128_s0/F
8.108 0.000 tNET RR 1 R7C53[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_24_s0/CLK
9.002 -0.051 tSu 1 R7C53[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_24_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path13

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_25_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n127_s0/I0
8.108 0.421 tINS FR 1 R7C53[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n127_s0/F
8.108 0.000 tNET RR 1 R7C53[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_25_s0/CLK
9.002 -0.051 tSu 1 R7C53[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_25_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path14

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_50_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n102_s0/I0
8.108 0.421 tINS FR 1 R7C53[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n102_s0/F
8.108 0.000 tNET RR 1 R7C53[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_50_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_50_s0/CLK
9.002 -0.051 tSu 1 R7C53[1][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_50_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path15

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_51_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n101_s0/I0
8.108 0.421 tINS FR 1 R7C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n101_s0/F
8.108 0.000 tNET RR 1 R7C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_51_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_51_s0/CLK
9.002 -0.051 tSu 1 R7C53[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_51_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path16

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_56_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n96_s0/I0
8.108 0.421 tINS FR 1 R7C53[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n96_s0/F
8.108 0.000 tNET RR 1 R7C53[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_56_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_56_s0/CLK
9.002 -0.051 tSu 1 R7C53[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_56_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path17

Path Summary:

Slack 0.894
Data Arrival Time 8.108
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_57_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n95_s0/I0
8.108 0.421 tINS FR 1 R7C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n95_s0/F
8.108 0.000 tNET RR 1 R7C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_57_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_57_s0/CLK
9.002 -0.051 tSu 1 R7C53[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_57_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.321%; route: 5.324, 81.022%; tC2Q: 0.306, 4.657%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path18

Path Summary:

Slack 0.917
Data Arrival Time 8.100
Data Required Time 9.017
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_16_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C51[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n136_s0/I0
8.100 0.413 tINS FR 1 R7C51[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n136_s0/F
8.100 0.000 tNET RR 1 R7C51[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.068 1.568 tNET RR 1 R7C51[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_16_s0/CLK
9.017 -0.051 tSu 1 R7C51[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_16_s0

Path Statistics:

Clock Skew 0.030
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.933, 14.217%; route: 5.324, 81.121%; tC2Q: 0.306, 4.663%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%

Path19

Path Summary:

Slack 0.917
Data Arrival Time 8.085
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_17_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C53[3][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n135_s0/I0
8.085 0.398 tINS FR 1 R7C53[3][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n135_s0/F
8.085 0.000 tNET RR 1 R7C53[3][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C53[3][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_17_s0/CLK
9.002 -0.051 tSu 1 R7C53[3][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_17_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.918, 14.020%; route: 5.324, 81.307%; tC2Q: 0.306, 4.673%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path20

Path Summary:

Slack 0.917
Data Arrival Time 8.100
Data Required Time 9.017
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_61_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.687 1.442 tNET FF 1 R7C51[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n91_s0/I0
8.100 0.413 tINS FR 1 R7C51[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n91_s0/F
8.100 0.000 tNET RR 1 R7C51[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_61_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.068 1.568 tNET RR 1 R7C51[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_61_s0/CLK
9.017 -0.051 tSu 1 R7C51[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_61_s0

Path Statistics:

Clock Skew 0.030
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.933, 14.217%; route: 5.324, 81.121%; tC2Q: 0.306, 4.663%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.568, 100.000%

Path21

Path Summary:

Slack 0.928
Data Arrival Time 8.056
Data Required Time 8.984
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.056 1.446 tNET RR 1 BSRAM_R28[22] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.051 1.551 tNET RR 1 BSRAM_R28[22] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKA
8.984 -0.067 tSu 1 BSRAM_R28[22] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 8.956%; route: 5.600, 86.326%; tC2Q: 0.306, 4.717%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.551, 100.000%

Path22

Path Summary:

Slack 0.936
Data Arrival Time 8.066
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_21_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.645 1.400 tNET FF 1 R7C49[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n131_s0/I0
8.066 0.421 tINS FR 1 R7C49[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n131_s0/F
8.066 0.000 tNET RR 1 R7C49[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C49[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_21_s0/CLK
9.002 -0.051 tSu 1 R7C49[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_21_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.413%; route: 5.282, 80.900%; tC2Q: 0.306, 4.687%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path23

Path Summary:

Slack 0.936
Data Arrival Time 8.066
Data Required Time 9.002
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_28_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.645 1.400 tNET FF 1 R7C49[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n124_s0/I0
8.066 0.421 tINS FR 1 R7C49[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n124_s0/F
8.066 0.000 tNET RR 1 R7C49[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.053 1.553 tNET RR 1 R7C49[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_28_s0/CLK
9.002 -0.051 tSu 1 R7C49[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_28_s0

Path Statistics:

Clock Skew 0.016
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.413%; route: 5.282, 80.900%; tC2Q: 0.306, 4.687%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.553, 100.000%

Path24

Path Summary:

Slack 0.943
Data Arrival Time 8.066
Data Required Time 9.010
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_63_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.537 1.537 tNET RR 1 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/CLK
1.843 0.306 tC2Q RR 3 R11C34[3][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/data_lane_ca_flag_reg_hsleep_r_s0/Q
2.520 0.677 tNET RR 1 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/I2
2.852 0.332 tINS RR 86 R5C34[3][B] inst_apm64_top/u_apm64_top/u_apsram_ctrl/c_state_data_lane_5_s0/F
6.057 3.205 tNET RR 1 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/I1
6.245 0.188 tINS RF 96 R18C57[2][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/n89_s1/F
7.645 1.400 tNET FF 1 R7C50[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n89_s0/I0
8.066 0.421 tINS FR 1 R7C50[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/n89_s0/F
8.066 0.000 tNET RR 1 R7C50[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_63_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.061 1.560 tNET RR 1 R7C50[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_63_s0/CLK
9.010 -0.051 tSu 1 R7C50[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_d_63_s0

Path Statistics:

Clock Skew 0.023
Setup Relationship 7.500
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.537, 100.000%
Arrival Data Path Delay cell: 0.941, 14.413%; route: 5.282, 80.900%; tC2Q: 0.306, 4.687%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.560, 100.000%

Path25

Path Summary:

Slack 0.947
Data Arrival Time 8.021
Data Required Time 8.969
From inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.569 1.569 tNET RR 1 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
1.875 0.306 tC2Q RR 18 R21C60[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/Q
4.016 2.141 tNET RR 1 R33C31[3][A] u_test/wr_data_en_s/I0
4.227 0.212 tINS RR 4 R33C31[3][A] u_test/wr_data_en_s/F
6.240 2.013 tNET RR 1 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/I2
6.609 0.369 tINS RR 12 R21C58[2][A] inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s2/F
8.021 1.412 tNET RR 1 BSRAM_R10[20] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.036 1.536 tNET RR 1 BSRAM_R10[20] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA
8.969 -0.067 tSu 1 BSRAM_R10[20] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s

Path Statistics:

Clock Skew -0.033
Setup Relationship 7.500
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.569, 100.000%
Arrival Data Path Delay cell: 0.581, 9.004%; route: 5.566, 86.254%; tC2Q: 0.306, 4.742%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.536, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.155
Data Arrival Time 0.955
Data Required Time 0.799
From inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716 0.716 tNET RR 1 R2C61[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/CLK
0.860 0.144 tC2Q RR 2 R2C61[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/Q
0.955 0.095 tNET RR 1 IOT61[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.717 0.717 tNET RR 1 IOT61[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/PCLK
0.799 0.082 tHld 1 IOT61[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.717, 100.000%

Path2

Path Summary:

Slack 0.216
Data Arrival Time 0.953
Data Required Time 0.737
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.710 0.710 tNET RR 1 R26C35[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK
0.854 0.144 tC2Q RR 1 R26C35[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q
0.953 0.099 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.700 0.700 tNET RR 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
0.737 0.037 tHld 1 BSRAM_R28[10] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.710, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.700, 100.000%

Path3

Path Summary:

Slack 0.231
Data Arrival Time 0.964
Data Required Time 0.733
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.709 0.709 tNET RR 1 R24C41[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.853 0.144 tC2Q RR 22 R24C41[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
0.964 0.111 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.696 0.696 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA
0.733 0.037 tHld 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.013
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.709, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path4

Path Summary:

Slack 0.235
Data Arrival Time 0.968
Data Required Time 0.733
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.713 0.713 tNET RR 1 R24C42[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.857 0.144 tC2Q RR 25 R24C42[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
0.968 0.111 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.696 0.696 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA
0.733 0.037 tHld 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path5

Path Summary:

Slack 0.241
Data Arrival Time 0.970
Data Required Time 0.729
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.713 0.713 tNET RR 1 R24C42[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.857 0.144 tC2Q RR 25 R24C42[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
0.970 0.113 tNET RR 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/ADA[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.692 0.692 tNET RR 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA
0.729 0.037 tHld 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.113, 43.969%; tC2Q: 0.144, 56.031%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path6

Path Summary:

Slack 0.242
Data Arrival Time 0.975
Data Required Time 0.733
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.713 0.713 tNET RR 1 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.857 0.144 tC2Q RR 24 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
0.975 0.118 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.696 0.696 tNET RR 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA
0.733 0.037 tHld 1 BSRAM_R28[11] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Path Statistics:

Clock Skew -0.017
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.118, 45.038%; tC2Q: 0.144, 54.962%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.696, 100.000%

Path7

Path Summary:

Slack 0.244
Data Arrival Time 0.973
Data Required Time 0.729
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.713 0.713 tNET RR 1 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.857 0.144 tC2Q RR 24 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
0.973 0.116 tNET RR 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.692 0.692 tNET RR 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA
0.729 0.037 tHld 1 BSRAM_R28[12] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_9_s

Path Statistics:

Clock Skew -0.021
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.116, 44.615%; tC2Q: 0.144, 55.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.692, 100.000%

Path8

Path Summary:

Slack 0.256
Data Arrival Time 1.049
Data Required Time 0.793
From inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_18_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716 0.716 tNET RR 1 R2C65[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_18_s0/CLK
0.860 0.144 tC2Q RR 1 R2C65[0][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_18_s0/Q
1.049 0.189 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722 0.722 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/PCLK
0.793 0.072 tHld 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem

Path Statistics:

Clock Skew 0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.722, 100.000%

Path9

Path Summary:

Slack 0.264
Data Arrival Time 1.068
Data Required Time 0.803
From inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_17_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.720 0.720 tNET RR 1 R2C64[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_17_s0/CLK
0.864 0.144 tC2Q RR 1 R2C64[0][B] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_17_s0/Q
1.068 0.204 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722 0.722 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/PCLK
0.803 0.082 tHld 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.722, 100.000%

Path10

Path Summary:

Slack 0.264
Data Arrival Time 1.068
Data Required Time 0.803
From inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_19_s0
To inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.720 0.720 tNET RR 1 R2C64[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_19_s0/CLK
0.864 0.144 tC2Q RR 1 R2C64[1][A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/wr_dq_r_19_s0/Q
1.068 0.204 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722 0.722 tNET RR 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem/PCLK
0.803 0.082 tHld 1 IOT66[A] inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/oserdes_dq_gen[2].dq_oser8_mem

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.722, 100.000%

Path11

Path Summary:

Slack 0.272
Data Arrival Time 4.701
Data Required Time 4.429
From gw_gao_inst_0/u_la0_top/rst_ao_syn_s0
To gw_gao_inst_0/u_la0_top/rst_ao_s0
Launch Clk userclk:[F]
Latch Clk userclk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
4.465 0.715 tNET FF 1 R25C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK
4.623 0.158 tC2Q FR 1 R25C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q
4.701 0.078 tNET RR 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
4.465 0.715 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
4.429 -0.036 tHld 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.078, 33.051%; tC2Q: 0.158, 66.949%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.715, 100.000%

Path12

Path Summary:

Slack 0.275
Data Arrival Time 2.616
Data Required Time 2.341
From gw_gao_inst_0/u_la0_top/address_counter_2_s0
To gw_gao_inst_0/u_la0_top/address_counter_2_s0
Launch Clk rao_clk:[R]
Latch Clk rao_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rao_clk
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.581 0.581 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.581 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.162 0.581 tINS RR 537 - gw_gao_inst_0/u_gw_jtag/tck_o
2.316 1.154 tNET RR 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.457 0.141 tC2Q RF 22 R31C55[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/Q
2.463 0.006 tNET FF 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/I1
2.616 0.153 tINS FF 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/data_to_addr_counter_2_s0/F
2.616 0.000 tNET FF 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 rao_clk
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.581 0.581 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.581 0.000 tNET RR 1 - gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.162 0.581 tINS RR 537 - gw_gao_inst_0/u_gw_jtag/tck_o
2.316 1.154 tNET RR 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0/CLK
2.341 0.025 tHld 1 R31C55[1][A] gw_gao_inst_0/u_la0_top/address_counter_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.162, 50.170%; route: 1.154, 49.830%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 1.162, 50.170%; route: 1.154, 49.830%

Path13

Path Summary:

Slack 0.275
Data Arrival Time 1.011
Data Required Time 0.736
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1
To inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711 0.711 tNET RR 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/CLK
0.852 0.141 tC2Q RF 3 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/Q
0.858 0.006 tNET FF 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1175_s1/I2
1.011 0.153 tINS FF 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1175_s1/F
1.011 0.000 tNET FF 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711 0.711 tNET RR 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1/CLK
0.736 0.025 tHld 1 R7C34[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphw_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.711, 100.000%

Path14

Path Summary:

Slack 0.275
Data Arrival Time 1.014
Data Required Time 0.739
From inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4
To inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.714 0.714 tNET RR 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/CLK
0.855 0.141 tC2Q RF 2 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/Q
0.861 0.006 tNET FF 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1265_s6/I0
1.014 0.153 tINS FF 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1265_s6/F
1.014 0.000 tNET FF 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.714 0.714 tNET RR 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4/CLK
0.739 0.025 tHld 1 R21C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_cmd_cnt_4_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.714, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.714, 100.000%

Path15

Path Summary:

Slack 0.275
Data Arrival Time 1.001
Data Required Time 0.726
From inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1
To inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701 0.701 tNET RR 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/CLK
0.842 0.141 tC2Q RF 4 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/Q
0.848 0.006 tNET FF 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2812_s1/I2
1.001 0.153 tINS FF 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2812_s1/F
1.001 0.000 tNET FF 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701 0.701 tNET RR 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1/CLK
0.726 0.025 tHld 1 R9C36[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/rvalid_cnt_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.701, 100.000%

Path16

Path Summary:

Slack 0.275
Data Arrival Time 1.010
Data Required Time 0.735
From inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1
To inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711 0.711 tNET RR 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/CLK
0.852 0.141 tC2Q RF 4 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/Q
0.858 0.006 tNET FF 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1235_s2/I1
1.010 0.153 tINS FF 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1235_s2/F
1.010 0.000 tNET FF 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711 0.711 tNET RR 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1/CLK
0.735 0.025 tHld 1 R23C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.711, 100.000%

Path17

Path Summary:

Slack 0.275
Data Arrival Time 1.016
Data Required Time 0.741
From inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716 0.716 tNET RR 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/CLK
0.857 0.141 tC2Q RF 5 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/Q
0.863 0.006 tNET FF 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2404_s1/I2
1.016 0.153 tINS FF 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2404_s1/F
1.016 0.000 tNET FF 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716 0.716 tNET RR 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0/CLK
0.741 0.025 tHld 1 R20C37[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.716, 100.000%

Path18

Path Summary:

Slack 0.275
Data Arrival Time 1.014
Data Required Time 0.739
From inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0
To inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.714 0.714 tNET RR 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/CLK
0.855 0.141 tC2Q RF 7 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/Q
0.861 0.006 tNET FF 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n_state.WRITE_DATA_s20/I1
1.014 0.153 tINS FF 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n_state.WRITE_DATA_s20/F
1.014 0.000 tNET FF 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.714 0.714 tNET RR 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0/CLK
0.739 0.025 tHld 1 R21C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/c_state.WRITE_DATA_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.714, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.714, 100.000%

Path19

Path Summary:

Slack 0.275
Data Arrival Time 0.990
Data Required Time 0.715
From u_test/addr_20_s0
To u_test/addr_20_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R33C37[0][A] u_test/addr_20_s0/CLK
0.831 0.141 tC2Q RF 7 R33C37[0][A] u_test/addr_20_s0/Q
0.837 0.006 tNET FF 1 R33C37[0][A] u_test/n1399_s2/I3
0.990 0.153 tINS FF 1 R33C37[0][A] u_test/n1399_s2/F
0.990 0.000 tNET FF 1 R33C37[0][A] u_test/addr_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R33C37[0][A] u_test/addr_20_s0/CLK
0.715 0.025 tHld 1 R33C37[0][A] u_test/addr_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%

Path20

Path Summary:

Slack 0.275
Data Arrival Time 0.990
Data Required Time 0.715
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0
To inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/CLK
0.831 0.141 tC2Q RF 5 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/Q
0.837 0.006 tNET FF 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1062_s4/I2
0.990 0.153 tINS FF 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1062_s4/F
0.990 0.000 tNET FF 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0/CLK
0.715 0.025 tHld 1 R14C32[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%

Path21

Path Summary:

Slack 0.275
Data Arrival Time 0.990
Data Required Time 0.715
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0
To inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/CLK
0.831 0.141 tC2Q RF 2 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/Q
0.837 0.006 tNET FF 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1059_s1/I3
0.990 0.153 tINS FF 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1059_s1/F
0.990 0.000 tNET FF 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690 0.690 tNET RR 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0/CLK
0.715 0.025 tHld 1 R14C34[1][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/rw_burst_cnt_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.690, 100.000%

Path22

Path Summary:

Slack 0.275
Data Arrival Time 0.994
Data Required Time 0.719
From inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0
To inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.694 0.694 tNET RR 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/CLK
0.835 0.141 tC2Q RF 2 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/Q
0.841 0.006 tNET FF 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n218_s1/I2
0.994 0.153 tINS FF 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/n218_s1/F
0.994 0.000 tNET FF 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.694 0.694 tNET RR 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0/CLK
0.719 0.025 tHld 1 R14C31[0][A] inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.694, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.694, 100.000%

Path23

Path Summary:

Slack 0.275
Data Arrival Time 0.982
Data Required Time 0.707
From inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26
To inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682 0.682 tNET RR 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/CLK
0.823 0.141 tC2Q RF 2 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/Q
0.829 0.006 tNET FF 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2926_s4/I1
0.982 0.153 tINS FF 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2926_s4/F
0.982 0.000 tNET FF 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682 0.682 tNET RR 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26/CLK
0.707 0.025 tHld 1 R13C41[0][A] inst_apm64_top/u_apm64_top/u_apsram_init/readback_check_1_s26

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.682, 100.000%

Path24

Path Summary:

Slack 0.275
Data Arrival Time 0.997
Data Required Time 0.722
From inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3
To inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697 0.697 tNET RR 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/CLK
0.838 0.141 tC2Q RF 6 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/Q
0.844 0.006 tNET FF 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1046_s3/I2
0.997 0.153 tINS FF 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/n1046_s3/F
0.997 0.000 tNET FF 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.697 0.697 tNET RR 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3/CLK
0.722 0.025 tHld 1 R17C40[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.697, 100.000%

Path25

Path Summary:

Slack 0.275
Data Arrival Time 0.991
Data Required Time 0.716
From inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1
To inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1
Launch Clk userclk:[R]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691 0.691 tNET RR 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/CLK
0.832 0.141 tC2Q RF 7 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/Q
0.838 0.006 tNET FF 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2771_s3/I1
0.991 0.153 tINS FF 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/n2771_s3/F
0.991 0.000 tNET FF 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 userclk
0.000 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691 0.691 tNET RR 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1/CLK
0.716 0.025 tHld 1 R11C38[1][A] inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[1].read_i_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.691, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.973
Data Arrival Time 7.778
Data Required Time 8.751
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.778 2.117 tNET FF 1 R31C46[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.029 1.529 tNET RR 1 R31C46[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
8.751 -0.278 tSu 1 R31C46[0][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.117, 85.674%; tC2Q: 0.354, 14.326%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.529, 100.000%

Path2

Path Summary:

Slack 0.973
Data Arrival Time 7.778
Data Required Time 8.751
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.778 2.117 tNET FF 1 R31C46[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.029 1.529 tNET RR 1 R31C46[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
8.751 -0.278 tSu 1 R31C46[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.117, 85.674%; tC2Q: 0.354, 14.326%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.529, 100.000%

Path3

Path Summary:

Slack 1.236
Data Arrival Time 7.533
Data Required Time 8.769
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.533 1.872 tNET FF 1 R34C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.047 1.547 tNET RR 1 R34C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
8.769 -0.278 tSu 1 R34C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.872, 84.097%; tC2Q: 0.354, 15.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.547, 100.000%

Path4

Path Summary:

Slack 1.236
Data Arrival Time 7.533
Data Required Time 8.769
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.533 1.872 tNET FF 1 R34C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.047 1.547 tNET RR 1 R34C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
8.769 -0.278 tSu 1 R34C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.872, 84.097%; tC2Q: 0.354, 15.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.547, 100.000%

Path5

Path Summary:

Slack 1.236
Data Arrival Time 7.533
Data Required Time 8.769
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.533 1.872 tNET FF 1 R34C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.047 1.547 tNET RR 1 R34C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
8.769 -0.278 tSu 1 R34C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew -0.010
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.872, 84.097%; tC2Q: 0.354, 15.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.547, 100.000%

Path6

Path Summary:

Slack 1.261
Data Arrival Time 7.516
Data Required Time 8.777
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.516 1.855 tNET FF 1 R24C41[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.055 1.555 tNET RR 1 R24C41[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
8.777 -0.278 tSu 1 R24C41[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.855, 83.975%; tC2Q: 0.354, 16.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.555, 100.000%

Path7

Path Summary:

Slack 1.261
Data Arrival Time 7.516
Data Required Time 8.777
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.516 1.855 tNET FF 1 R24C41[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.055 1.555 tNET RR 1 R24C41[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
8.777 -0.278 tSu 1 R24C41[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.855, 83.975%; tC2Q: 0.354, 16.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.555, 100.000%

Path8

Path Summary:

Slack 1.261
Data Arrival Time 7.516
Data Required Time 8.777
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.516 1.855 tNET FF 1 R24C41[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.055 1.555 tNET RR 1 R24C41[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
8.777 -0.278 tSu 1 R24C41[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.002
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.855, 83.975%; tC2Q: 0.354, 16.025%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.555, 100.000%

Path9

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
8.763 -0.278 tSu 1 R32C47[2][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path10

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
8.763 -0.278 tSu 1 R32C47[1][A] gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path11

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
8.763 -0.278 tSu 1 R32C47[1][B] gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path12

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[0][A] gw_gao_inst_0/u_la0_top/triger_s0/CLK
8.763 -0.278 tSu 1 R32C47[0][A] gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path13

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
8.763 -0.278 tSu 1 R32C47[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path14

Path Summary:

Slack 1.277
Data Arrival Time 7.486
Data Required Time 8.763
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.486 1.825 tNET FF 1 R32C47[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.041 1.541 tNET RR 1 R32C47[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
8.763 -0.278 tSu 1 R32C47[3][A] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew -0.016
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.825, 83.754%; tC2Q: 0.354, 16.246%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.541, 100.000%

Path15

Path Summary:

Slack 1.332
Data Arrival Time 7.452
Data Required Time 8.785
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.452 1.791 tNET FF 1 R24C40[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.063 1.563 tNET RR 1 R24C40[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
8.785 -0.278 tSu 1 R24C40[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.791, 83.496%; tC2Q: 0.354, 16.503%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path16

Path Summary:

Slack 1.332
Data Arrival Time 7.452
Data Required Time 8.785
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.452 1.791 tNET FF 1 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.063 1.563 tNET RR 1 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
8.785 -0.278 tSu 1 R24C40[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.791, 83.496%; tC2Q: 0.354, 16.503%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path17

Path Summary:

Slack 1.332
Data Arrival Time 7.452
Data Required Time 8.785
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.452 1.791 tNET FF 1 R24C40[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.063 1.563 tNET RR 1 R24C40[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
8.785 -0.278 tSu 1 R24C40[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.005
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.791, 83.496%; tC2Q: 0.354, 16.503%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.563, 100.000%

Path18

Path Summary:

Slack 1.375
Data Arrival Time 7.392
Data Required Time 8.768
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.392 1.731 tNET FF 1 R33C47[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.046 1.546 tNET RR 1 R33C47[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
8.768 -0.278 tSu 1 R33C47[1][A] gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew -0.011
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.731, 83.022%; tC2Q: 0.354, 16.978%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.546, 100.000%

Path19

Path Summary:

Slack 1.375
Data Arrival Time 7.392
Data Required Time 8.768
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.392 1.731 tNET FF 1 R33C47[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.046 1.546 tNET RR 1 R33C47[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
8.768 -0.278 tSu 1 R33C47[2][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew -0.011
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.731, 83.022%; tC2Q: 0.354, 16.978%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.546, 100.000%

Path20

Path Summary:

Slack 1.375
Data Arrival Time 7.392
Data Required Time 8.768
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.392 1.731 tNET FF 1 R33C47[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.046 1.546 tNET RR 1 R33C47[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
8.768 -0.278 tSu 1 R33C47[0][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.011
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.731, 83.022%; tC2Q: 0.354, 16.978%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.546, 100.000%

Path21

Path Summary:

Slack 1.515
Data Arrival Time 7.239
Data Required Time 8.754
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.239 1.577 tNET FF 1 R30C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.032 1.532 tNET RR 1 R30C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
8.754 -0.278 tSu 1 R30C47[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.577, 81.668%; tC2Q: 0.354, 18.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.532, 100.000%

Path22

Path Summary:

Slack 1.515
Data Arrival Time 7.239
Data Required Time 8.754
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.239 1.577 tNET FF 1 R30C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.032 1.532 tNET RR 1 R30C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
8.754 -0.278 tSu 1 R30C47[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.577, 81.668%; tC2Q: 0.354, 18.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.532, 100.000%

Path23

Path Summary:

Slack 1.515
Data Arrival Time 7.239
Data Required Time 8.754
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.239 1.577 tNET FF 1 R30C47[3][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.032 1.532 tNET RR 1 R30C47[3][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
8.754 -0.278 tSu 1 R30C47[3][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.577, 81.668%; tC2Q: 0.354, 18.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.532, 100.000%

Path24

Path Summary:

Slack 1.515
Data Arrival Time 7.239
Data Required Time 8.754
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.239 1.577 tNET FF 1 R30C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.032 1.532 tNET RR 1 R30C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
8.754 -0.278 tSu 1 R30C47[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew -0.026
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.577, 81.668%; tC2Q: 0.354, 18.332%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.532, 100.000%

Path25

Path Summary:

Slack 1.526
Data Arrival Time 7.233
Data Required Time 8.759
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk userclk:[F]
Latch Clk userclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.750 3.750 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.307 1.557 tNET FF 1 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
5.661 0.354 tC2Q FF 60 R25C48[2][B] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.233 1.571 tNET FF 1 R31C47[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
7.500 7.500 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR 2749 TOPSIDE[0] inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.036 1.536 tNET RR 1 R31C47[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
8.759 -0.278 tSu 1 R31C47[0][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew -0.021
Setup Relationship 3.750
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.557, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.571, 81.610%; tC2Q: 0.354, 18.390%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.536, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.875
Data Arrival Time 2.096
Data Required Time 1.222
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.275 0.694 tNET RR 1 R11C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLK
1.222 -0.053 tHld 1 R11C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.566%; route: 0.694, 54.434%

Path2

Path Summary:

Slack 0.875
Data Arrival Time 2.096
Data Required Time 1.222
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C44[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.275 0.694 tNET RR 1 R11C44[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLK
1.222 -0.053 tHld 1 R11C44[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.566%; route: 0.694, 54.434%

Path3

Path Summary:

Slack 0.875
Data Arrival Time 2.096
Data Required Time 1.222
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C44[3][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.275 0.694 tNET RR 1 R11C44[3][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLK
1.222 -0.053 tHld 1 R11C44[3][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1

Path Statistics:

Clock Skew -0.006
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.566%; route: 0.694, 54.434%

Path4

Path Summary:

Slack 0.879
Data Arrival Time 2.096
Data Required Time 1.218
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.271 0.690 tNET RR 1 R11C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLK
1.218 -0.053 tHld 1 R11C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.709%; route: 0.690, 54.291%

Path5

Path Summary:

Slack 0.879
Data Arrival Time 2.096
Data Required Time 1.218
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C43[1][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.271 0.690 tNET RR 1 R11C43[1][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLK
1.218 -0.053 tHld 1 R11C43[1][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.709%; route: 0.690, 54.291%

Path6

Path Summary:

Slack 0.879
Data Arrival Time 2.110
Data Required Time 1.232
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.285 0.704 tNET RR 1 R9C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLK
1.232 -0.053 tHld 1 R9C44[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.211%; route: 0.704, 54.789%

Path7

Path Summary:

Slack 0.879
Data Arrival Time 2.096
Data Required Time 1.218
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_12_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.096 0.672 tNET RR 1 R11C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.271 0.690 tNET RR 1 R11C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_12_s1/CLK
1.218 -0.053 tHld 1 R11C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_12_s1

Path Statistics:

Clock Skew -0.010
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.672, 82.353%; tC2Q: 0.144, 17.647%
Required Clock Path Delay cell: 0.581, 45.709%; route: 0.690, 54.291%

Path8

Path Summary:

Slack 0.879
Data Arrival Time 2.110
Data Required Time 1.232
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_15_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C44[2][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.285 0.704 tNET RR 1 R9C44[2][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_15_s1/CLK
1.232 -0.053 tHld 1 R9C44[2][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_15_s1

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.211%; route: 0.704, 54.789%

Path9

Path Summary:

Slack 0.882
Data Arrival Time 2.132
Data Required Time 1.251
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.132 0.708 tNET RR 1 R2C4[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.304 0.723 tNET RR 1 R2C4[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
1.251 -0.053 tHld 1 R2C4[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0

Path Statistics:

Clock Skew 0.023
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.708, 83.099%; tC2Q: 0.144, 16.901%
Required Clock Path Delay cell: 0.581, 44.561%; route: 0.723, 55.439%

Path10

Path Summary:

Slack 0.882
Data Arrival Time 2.132
Data Required Time 1.251
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.132 0.708 tNET RR 1 R2C4[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.304 0.723 tNET RR 1 R2C4[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLK
1.251 -0.053 tHld 1 R2C4[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0

Path Statistics:

Clock Skew 0.023
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.708, 83.099%; tC2Q: 0.144, 16.901%
Required Clock Path Delay cell: 0.581, 44.561%; route: 0.723, 55.439%

Path11

Path Summary:

Slack 0.882
Data Arrival Time 2.127
Data Required Time 1.245
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.127 0.703 tNET RR 1 R5C38[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.298 0.718 tNET RR 1 R5C38[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLK
1.245 -0.053 tHld 1 R5C38[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0

Path Statistics:

Clock Skew 0.018
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.703, 82.994%; tC2Q: 0.144, 17.006%
Required Clock Path Delay cell: 0.581, 44.741%; route: 0.718, 55.259%

Path12

Path Summary:

Slack 0.883
Data Arrival Time 2.110
Data Required Time 1.228
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.281 0.700 tNET RR 1 R9C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLK
1.228 -0.053 tHld 1 R9C43[1][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.352%; route: 0.700, 54.648%

Path13

Path Summary:

Slack 0.883
Data Arrival Time 2.110
Data Required Time 1.228
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_8_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C43[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.281 0.700 tNET RR 1 R9C43[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_8_s1/CLK
1.228 -0.053 tHld 1 R9C43[0][B] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.352%; route: 0.700, 54.648%

Path14

Path Summary:

Slack 0.883
Data Arrival Time 2.110
Data Required Time 1.228
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_9_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C43[2][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.281 0.700 tNET RR 1 R9C43[2][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_9_s1/CLK
1.228 -0.053 tHld 1 R9C43[2][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.352%; route: 0.700, 54.648%

Path15

Path Summary:

Slack 0.883
Data Arrival Time 2.110
Data Required Time 1.228
From u_reset_key/key_1_s0
To inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_14_s1
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.110 0.686 tNET RR 1 R9C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.281 0.700 tNET RR 1 R9C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_14_s1/CLK
1.228 -0.053 tHld 1 R9C43[0][A] inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.686, 82.651%; tC2Q: 0.144, 17.349%
Required Clock Path Delay cell: 0.581, 45.352%; route: 0.700, 54.648%

Path16

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_lch_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C18[0][B] led_lch_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C18[0][B] led_lch_s0/CLK
1.229 -0.053 tHld 1 R18C18[0][B] led_lch_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path17

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_1_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[0][A] led_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[0][A] led_cnt_1_s0/CLK
1.229 -0.053 tHld 1 R18C34[0][A] led_cnt_1_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path18

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_3_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[3][A] led_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[3][A] led_cnt_3_s0/CLK
1.229 -0.053 tHld 1 R18C34[3][A] led_cnt_3_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path19

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_6_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[1][A] led_cnt_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[1][A] led_cnt_6_s0/CLK
1.229 -0.053 tHld 1 R18C34[1][A] led_cnt_6_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path20

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_13_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[1][B] led_cnt_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[1][B] led_cnt_13_s0/CLK
1.229 -0.053 tHld 1 R18C34[1][B] led_cnt_13_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path21

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_14_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C36[1][B] led_cnt_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C36[1][B] led_cnt_14_s0/CLK
1.229 -0.053 tHld 1 R18C36[1][B] led_cnt_14_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path22

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_15_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C36[1][A] led_cnt_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C36[1][A] led_cnt_15_s0/CLK
1.229 -0.053 tHld 1 R18C36[1][A] led_cnt_15_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path23

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_16_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C36[0][B] led_cnt_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C36[0][B] led_cnt_16_s0/CLK
1.229 -0.053 tHld 1 R18C36[0][B] led_cnt_16_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path24

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_18_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[2][A] led_cnt_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[2][A] led_cnt_18_s0/CLK
1.229 -0.053 tHld 1 R18C34[2][A] led_cnt_18_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Path25

Path Summary:

Slack 0.885
Data Arrival Time 2.113
Data Required Time 1.229
From u_reset_key/key_1_s0
To led_cnt_22_s0
Launch Clk clkin:[R]
Latch Clk clkin:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.280 0.700 tNET RR 1 R17C38[0][A] u_reset_key/key_1_s0/CLK
1.424 0.144 tC2Q RR 581 R17C38[0][A] u_reset_key/key_1_s0/Q
2.113 0.689 tNET RR 1 R18C34[2][B] led_cnt_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkin
0.000 0.000 tCL RR 1 IOB26[A] clk_ibuf/I
0.581 0.581 tINS RR 83 IOB26[A] clk_ibuf/O
1.282 0.701 tNET RR 1 R18C34[2][B] led_cnt_22_s0/CLK
1.229 -0.053 tHld 1 R18C34[2][B] led_cnt_22_s0

Path Statistics:

Clock Skew 0.001
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.581, 45.370%; route: 0.700, 54.630%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.689, 82.713%; tC2Q: 0.144, 17.287%
Required Clock Path Delay cell: 0.581, 45.326%; route: 0.701, 54.674%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW2

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

MPW3

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA

MPW4

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

MPW5

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKA

MPW6

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKA

MPW8

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

MPW9

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA

MPW10

MPW Summary:

Slack: 2.040
Actual Width: 2.902
Required Width: 0.862
Type: Low Pulse Width
Clock: userclk
Objects: inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
3.750 0.000 active clock edge time
3.750 0.000 userclk
3.750 0.000 tCL FF inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298 1.548 tNET FF inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
7.500 0.000 active clock edge time
7.500 0.000 userclk
7.500 0.000 tCL RR inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200 0.700 tNET RR inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
2749 clk_x1 0.008 1.580
537 control0[0] 43.402 2.395
341 init_calib_Z 1.200 2.800
189 n20_3 46.100 1.757
172 config_done_Z 3.014 2.677
169 data_out_shift_reg_166_7 44.259 2.453
167 n1370_5 45.174 1.783
167 n1370_10 45.226 1.909
129 rd_data_valid_init[0] 4.215 2.548
129 rd_data_valid_init[1] 4.470 2.445

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R25C41 55.56%
R26C48 52.78%
R27C49 52.78%
R30C49 52.78%
R28C47 52.78%
R12C43 51.39%
R10C45 50.00%
R29C55 50.00%
R28C51 50.00%
R10C44 50.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name mem_clk -period 1.875 -waveform {0 0.938} [get_nets {memory_clk}]
TC_CLOCK Actived create_clock -name rao_clk -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name userclk -source [get_nets {memory_clk}] -master_clock mem_clk -divide_by 4 -duty_cycle 50 [get_pins {inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {mem_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {rao_clk}] -group [get_clocks {clkin mem_clk userclk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {userclk}] -group [get_clocks {mem_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clkin}] -group [get_clocks {userclk}]