Power Messages

Report Title Power Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AR-LV25UG256PC2/I1
Device GW5AR-25
Device Version A
Created Time Thu Oct 24 16:06:21 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 370.804
Quiescent Power (mW) 52.269
Dynamic Power (mW) 318.535

Thermal Information:

Junction Temperature 35.160
Theta JA 27.400
Max Allowed Ambient Temperature 74.840

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 0.900 269.325 29.999 269.392
VCCX 3.300 3.674 3.000 22.024
VCCIO18 1.800 3.508 0.741 7.649
VCCIO33 3.300 0.170 0.254 1.399
VCC_LDO 3.300 17.316 4.000 70.342

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 2.230 NA 14.015
IO 29.696 6.942 76.942
BSRAM 192.172 NA NA
PLL 57.142 NA NA
DDRDLL 44.237 NA NA
DQS 111.024 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 406.805 406.805(406.793)
top/gw_gao_inst_0/ 76.611 76.611(76.611)
top/gw_gao_inst_0/u_icon_top/ 0.002 0.002(0.000)
top/gw_gao_inst_0/u_la0_top/ 76.609 76.609(76.530)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/ 0.004 0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/ 0.003 0.003(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ 76.523 76.523(0.000)
top/inst_apm64_top/ 272.624 272.624(272.624)
top/inst_apm64_top/u_apm64_top/ 272.624 272.624(228.056)
top/inst_apm64_top/u_apm64_top/u_apsram_ctrl/ 0.204 0.204(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_init/ 0.432 0.432(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_sync/ 0.015 0.015(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/ 227.328 227.328(227.325)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/ 113.628 113.628(57.888)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/ 28.685 28.685(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/ 29.203 29.203(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/ 113.611 113.611(57.888)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/ 28.685 28.685(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/ 29.203 29.203(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[0].u_fifo_ctrl/ 0.019 0.019(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/fifo_ctrl_in_gen[1].u_fifo_ctrl/ 0.019 0.019(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_apm64_cmd_lane/ 0.026 0.026(0.000)
top/inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/ 0.022 0.022(0.000)
top/inst_apm64_top/u_apm64_top/u_cmd_fifo/ 0.078 0.078(0.000)
top/u_Gowin_PLL/ 57.142 57.142(0.000)
top/u_reset_key/ 0.030 0.030(0.000)
top/u_test/ 0.386 0.386(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
clkin 50.000 57.197
rao_clk 20.000 9.969
userclk 133.333 184.278
mem_clk 533.333 155.361
NO CLOCK DOMAIN 0.000 0.000