Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\gowin_pll\gowin_pll.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\key_debounce.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\test_2k.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\top.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\uhs2_psram_memory_interface\uhs2_psram_memory_interface.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.10.03_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.10.03\Gowin_UHS2_PSRAM_Memory_Interface\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW5AR-LV25UG256PC2/I1
Device GW5AR-25
Device Version A
Created Time Thu Oct 24 16:06:04 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 265.492MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.241s, Peak memory usage = 265.492MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 265.492MB
    Optimizing Phase 2: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.242s, Peak memory usage = 265.492MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 265.492MB
    Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 265.492MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 265.492MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 265.492MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 265.492MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 265.492MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 265.492MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 280.969MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.191s, Peak memory usage = 280.969MB
Generate output files:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.31s, Peak memory usage = 282.293MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 282.293MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 8
Embedded Port 28
I/O Buf 32
    IBUF 5
    OBUF 5
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 2
    ELVDS_IOBUF 2
Register 3256
    DFFRE 285
    DFFPE 47
    DFFCE 2924
LUT 2617
    LUT2 646
    LUT3 839
    LUT4 1132
MUX 1
    MUX16 1
ALU 215
    ALU 215
INV 40
    INV 40
IOLOGIC 44
    IDES8_MEM 16
    OSER8 4
    OSER8_MEM 20
    IODELAY 4
BSRAM 27
    SDPB 4
    SDPX9B 23
CLOCK 6
    CLKDIV 1
    DQS 2
    DDRDLL 1
    DHCE 1
    PLLA 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2880(2665 LUT, 215 ALU) / 23040 13%
Register 3256 / 23640 14%
  --Register as Latch 0 / 23640 0%
  --Register as FF 3256 / 23640 14%
BSRAM 27 / 56 49%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Generated 1.875 533.3 0.000 0.938 clk_ibuf/I clk u_Gowin_PLL/PLLA_inst/CLKOUT0
3 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk Generated 7.500 133.3 0.000 3.750 u_Gowin_PLL/PLLA_inst/CLKOUT0 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 283.046(MHz) 5 TOP
2 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk 533.333(MHz) 1394.296(MHz) 1 TOP
3 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk 133.333(MHz) 1522.071(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.412
Data Arrival Time 8.416
Data Required Time 8.004
From inst_apm64_top/u_apm64_top/u_apm64_dll
To inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0
Launch Clk u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.625 0.000 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
5.869 0.244 tCL RR 1 u_Gowin_PLL/PLLA_inst/CLKOUT0
6.169 0.300 tNET RR 3 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
6.326 0.157 tINS RR 44 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
6.626 0.300 tNET RR 8 inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN
6.976 0.350 tINS RR 3 inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1]
7.276 0.300 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0
7.721 0.445 tINS RF 1 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT
7.721 0.000 tNET FF 2 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN
7.761 0.040 tINS FR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT
7.761 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN
7.801 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT
7.801 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN
7.841 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT
7.841 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN
7.881 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/COUT
7.881 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/CIN
7.921 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/COUT
7.921 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n8_s/CIN
8.116 0.195 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n8_s/SUM
8.416 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
7.790 0.290 tCL RR 2733 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.090 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0/CLK
8.055 -0.035 tUnc inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0
8.004 -0.051 tSu 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[1].RMOVE_PAR_7_s0
Path Statistics:
Clock Skew: -0.111
Setup Relationship: 1.875
Logic Level: 4
Arrival Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%
Arrival Data Path Delay: cell: 1.190, 56.937%; route: 0.600, 28.709%; tC2Q: 0.300, 14.354%
Required Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%

Path 2

Path Summary:
Slack -0.372
Data Arrival Time 8.376
Data Required Time 8.004
From inst_apm64_top/u_apm64_top/u_apm64_dll
To inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0
Launch Clk u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.625 0.000 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
5.869 0.244 tCL RR 1 u_Gowin_PLL/PLLA_inst/CLKOUT0
6.169 0.300 tNET RR 3 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
6.326 0.157 tINS RR 44 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
6.626 0.300 tNET RR 8 inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN
6.976 0.350 tINS RR 3 inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1]
7.276 0.300 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0
7.721 0.445 tINS RF 1 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT
7.721 0.000 tNET FF 2 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN
7.761 0.040 tINS FR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT
7.761 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN
7.801 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT
7.801 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN
7.841 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT
7.841 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN
7.881 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/COUT
7.881 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/CIN
8.076 0.195 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n9_s/SUM
8.376 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
7.790 0.290 tCL RR 2733 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.090 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0/CLK
8.055 -0.035 tUnc inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0
8.004 -0.051 tSu 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_6_s0
Path Statistics:
Clock Skew: -0.111
Setup Relationship: 1.875
Logic Level: 4
Arrival Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%
Arrival Data Path Delay: cell: 1.150, 56.097%; route: 0.600, 29.269%; tC2Q: 0.300, 14.634%
Required Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%

Path 3

Path Summary:
Slack -0.332
Data Arrival Time 8.336
Data Required Time 8.004
From inst_apm64_top/u_apm64_top/u_apm64_dll
To inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0
Launch Clk u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.625 0.000 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
5.869 0.244 tCL RR 1 u_Gowin_PLL/PLLA_inst/CLKOUT0
6.169 0.300 tNET RR 3 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
6.326 0.157 tINS RR 44 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
6.626 0.300 tNET RR 8 inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN
6.976 0.350 tINS RR 3 inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1]
7.276 0.300 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0
7.721 0.445 tINS RF 1 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT
7.721 0.000 tNET FF 2 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN
7.761 0.040 tINS FR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT
7.761 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN
7.801 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT
7.801 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN
7.841 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/COUT
7.841 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/CIN
8.036 0.195 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n10_s/SUM
8.336 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
7.790 0.290 tCL RR 2733 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.090 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0/CLK
8.055 -0.035 tUnc inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0
8.004 -0.051 tSu 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_5_s0
Path Statistics:
Clock Skew: -0.111
Setup Relationship: 1.875
Logic Level: 4
Arrival Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%
Arrival Data Path Delay: cell: 1.110, 55.223%; route: 0.600, 29.851%; tC2Q: 0.300, 14.926%
Required Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%

Path 4

Path Summary:
Slack -0.292
Data Arrival Time 8.296
Data Required Time 8.004
From inst_apm64_top/u_apm64_top/u_apm64_dll
To inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0
Launch Clk u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Latch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.625 0.000 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
5.869 0.244 tCL RR 1 u_Gowin_PLL/PLLA_inst/CLKOUT0
6.169 0.300 tNET RR 3 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
6.326 0.157 tINS RR 44 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
6.626 0.300 tNET RR 8 inst_apm64_top/u_apm64_top/u_apm64_dll/CLKIN
6.976 0.350 tINS RR 3 inst_apm64_top/u_apm64_top/u_apm64_dll/STEP[1]
7.276 0.300 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/I0
7.721 0.445 tINS RF 1 inst_apm64_top/u_apm64_top/u_apsram_init/n14_s/COUT
7.721 0.000 tNET FF 2 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/CIN
7.761 0.040 tINS FR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n13_s/COUT
7.761 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/CIN
7.801 0.040 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n12_s/COUT
7.801 0.000 tNET RR 2 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/CIN
7.996 0.195 tINS RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/n11_s/SUM
8.296 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.500 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
7.790 0.290 tCL RR 2733 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.090 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0/CLK
8.055 -0.035 tUnc inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0
8.004 -0.051 tSu 1 inst_apm64_top/u_apm64_top/u_apsram_init/rmove_gen[0].RMOVE_PAR_4_s0
Path Statistics:
Clock Skew: -0.111
Setup Relationship: 1.875
Logic Level: 4
Arrival Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%
Arrival Data Path Delay: cell: 1.070, 54.314%; route: 0.600, 30.457%; tC2Q: 0.300, 15.229%
Required Clock Path Delay: cell: 0.157, 34.338%; route: 0.300, 65.662%

Path 5

Path Summary:
Slack -0.261
Data Arrival Time 40.906
Data Required Time 40.645
From inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0
To inst_apm64_top/u_apm64_top/u_dqce_clk_x4
Launch Clk clk[F]
Latch Clk u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 clk
40.000 0.000 tCL RR 1 clk_ibuf/I
40.000 0.000 tINS RR 83 clk_ibuf/O
40.300 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLK
40.606 0.306 tC2Q RR 10 inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/Q
40.906 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CEN
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.313 0.000 u_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
40.556 0.244 tCL FF 1 u_Gowin_PLL/PLLA_inst/CLKOUT0
40.836 0.280 tNET FF 3 inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
40.801 -0.035 tUnc inst_apm64_top/u_apm64_top/u_dqce_clk_x4
40.645 -0.157 tSu 1 inst_apm64_top/u_apm64_top/u_dqce_clk_x4
Path Statistics:
Clock Skew: 0.224
Setup Relationship: 0.313
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.300, 49.505%; tC2Q: 0.306, 50.495%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%