#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020
#install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
#OS: Windows 8 6.2
#Hostname: JN-IP-SHANGYAN

# Mon Feb 22 14:30:22 2021

#Implementation: rev_1


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@N:CG1350 :  | Running Verilog Compiler in Multiple File Compilation Unit mode 

@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v" (library work)
@I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_local_define.v" (library work)
@I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_define.v" (library work)
@I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_param.v" (library work)
@I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_local_param.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_lane.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_syn_top.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_sync.v" (library work)
@N:CG346 : apsram_sync.v(159) | Read full_case directive.
@N:CG347 : apsram_sync.v(159) | Read a parallel_case directive.
@W:CG286 : apsram_sync.v(159) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_test.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_top_level0.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_top_level1.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_wd.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\fifo_sc.v" (library work)
@I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\gowin_rpll\gowin_rpll.v" (library work)
@N:CG1306 : gowin_rpll.v(25) | Loading library file E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\IDE\data\hardware_core\gw1n\prim_syn.v into library work
@I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\IDE\data\hardware_core\gw1n\prim_syn.v" (library work)
Verilog syntax check successful!
File D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_syn_top.v changed - recompiling
Selecting top level module psram_syn_top
@N:CG364 : gw1n.v(2181) | Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
@N:CG364 : gw1n.v(2299) | Synthesizing module DLL in library work.
Running optimization stage 1 on DLL .......
@N:CG364 : gw1n.v(2357) | Synthesizing module DHCEN in library work.
Running optimization stage 1 on DHCEN .......
@N:CG364 : gw1n.v(2288) | Synthesizing module CLKDIV in library work.
Running optimization stage 1 on CLKDIV .......
@N:CG364 : apsram_sync.v(4) | Synthesizing module \~apsram_sync.psram_memory_interface_top_2ch  in library work.
@N:CG179 : apsram_sync.v(121) | Removing redundant assignment.
@W:CG133 : apsram_sync.v(50) | Object lock_d1 is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~apsram_sync.psram_memory_interface_top_2ch  .......
@W:CL177 : apsram_sync.v(139) | Sharing sequential element ddr_rst_d1. Add a syn_preserve attribute to the element to prevent sharing.
@N:CG364 : apsram_wd.v(4) | Synthesizing module \~apsram_wd.psram_memory_interface_top_2ch  in library work.
@N:CG364 : gw1n.v(388) | Synthesizing module OSER4 in library work.
Running optimization stage 1 on OSER4 .......
@N:CG364 : apsram_lane.v(4) | Synthesizing module \~apsram_lane.psram_memory_interface_top_2ch  in library work.
@N:CG364 : gw1n.v(356) | Synthesizing module IDES4 in library work.
Running optimization stage 1 on IDES4 .......
@W:CG133 : apsram_lane.v(101) | Object cs_st_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_lane.v(102) | Object init_cs_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_lane.v(108) | Object dqstx0_dd is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_lane.v(118) | Object wr_en_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : apsram_lane.v(127) | Removing wire wr_data_d, as there is no assignment to it.
@W:CG360 : apsram_lane.v(128) | Removing wire data_mask_d, as there is no assignment to it.
@W:CG360 : apsram_lane.v(134) | Removing wire cs_d5, as there is no assignment to it.
@W:CG360 : apsram_lane.v(140) | Removing wire in_dqs, as there is no assignment to it.
Running optimization stage 1 on \~apsram_lane.psram_memory_interface_top_2ch  .......
@W:CL318 : apsram_lane.v(70) | *Output recalib has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : apsram_lane.v(87) | *Output test0 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL169 : apsram_lane.v(494) | Pruning unused register dqstx1_d. Make sure that there are no unused intermediate registers.
@W:CL169 : apsram_lane.v(485) | Pruning unused register genblk7.dqtx_dd0. Make sure that there are no unused intermediate registers.
@W:CL169 : apsram_lane.v(475) | Pruning unused register genblk7.dqtx_dd. Make sure that there are no unused intermediate registers.
@W:CL169 : apsram_lane.v(393) | Pruning unused register cs_dd. Make sure that there are no unused intermediate registers.
@W:CL113 : apsram_lane.v(682) | Feedback mux created for signal rd_data_valid_d1[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : apsram_lane.v(457) | Sharing sequential element dqtx0_d. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL250 : apsram_lane.v(682) | All reachable assignments to rd_data_valid_d1[2] assign 0, register removed by optimization
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : apsram_lane.v(170) | Pruning register bits 30 to 22 of CA_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CG781 : apsram_wd.v(127) | Input clk_x2p on instance u_psram_lane is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@N:CG364 : gw1n.v(318) | Synthesizing module IOBUF in library work.
Running optimization stage 1 on IOBUF .......
@N:CG364 : gw1n.v(433) | Synthesizing module IODELAY in library work.
Running optimization stage 1 on IODELAY .......
@N:CG179 : apsram_wd.v(250) | Removing redundant assignment.
@N:CG364 : gw1n.v(2247) | Synthesizing module ELVDS_OBUF in library work.
Running optimization stage 1 on ELVDS_OBUF .......
@N:CG364 : gw1n.v(314) | Synthesizing module TBUF in library work.
Running optimization stage 1 on TBUF .......
@N:CG364 : gw1n.v(310) | Synthesizing module OBUF in library work.
Running optimization stage 1 on OBUF .......
@W:CG360 : apsram_wd.v(85) | Removing wire dqs_ts, as there is no assignment to it.
@W:CG360 : apsram_wd.v(91) | Removing wire clkn_out_d, as there is no assignment to it.
@W:CG360 : apsram_wd.v(94) | Removing wire wr_en_delay, as there is no assignment to it.
@W:CG360 : apsram_wd.v(97) | Removing wire out_init, as there is no assignment to it.
@W:CG360 : apsram_wd.v(98) | Removing wire out_inits, as there is no assignment to it.
@W:CG360 : apsram_wd.v(99) | Removing wire out_ca, as there is no assignment to it.
@W:CG360 : apsram_wd.v(100) | Removing wire out_cats, as there is no assignment to it.
@W:CG360 : apsram_wd.v(101) | Removing wire out_data, as there is no assignment to it.
@W:CG360 : apsram_wd.v(102) | Removing wire out_datats, as there is no assignment to it.
Running optimization stage 1 on \~apsram_wd.psram_memory_interface_top_2ch  .......
@N:CG364 : apsram_init.v(4) | Synthesizing module \~apsram_init.psram_memory_interface_top_2ch  in library work.
@N:CG179 : apsram_init.v(270) | Removing redundant assignment.
@N:CG179 : apsram_init.v(286) | Removing redundant assignment.
@N:CG179 : apsram_init.v(296) | Removing redundant assignment.
@N:CG179 : apsram_init.v(304) | Removing redundant assignment.
@N:CG179 : apsram_init.v(314) | Removing redundant assignment.
@N:CG179 : apsram_init.v(431) | Removing redundant assignment.
@N:CG179 : apsram_init.v(587) | Removing redundant assignment.
@N:CG179 : apsram_init.v(619) | Removing redundant assignment.
@N:CG179 : apsram_init.v(629) | Removing redundant assignment.
@W:CG133 : apsram_init.v(69) | Object STEN is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_init.v(66) | Object cnt_clr is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on \~apsram_init.psram_memory_interface_top_2ch  .......
@W:CL207 : apsram_init.v(442) | All reachable assignments to addr[21:0] assign 0, register removed by optimization.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : apsram_init.v(442) | Pruning register bit 25 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : apsram_init.v(442) | Pruning register bit 16 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : apsram_init.v(442) | Pruning register bits 11 to 10 of wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : apsram_init.v(442) | Pruning register bit 5 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : apsram_init.v(442) | Pruning register bit 1 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : apsram_top_level0.v(4) | Synthesizing module \~apsram_top.psram_memory_interface_top_2ch  in library work.
@W:CG133 : apsram_top_level0.v(66) | Object calib_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_top_level0.v(67) | Object calib_div0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : apsram_top_level0.v(68) | Object calib_div1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : apsram_top_level0.v(85) | Removing wire wr_cs, as there is no assignment to it.
@W:CG360 : apsram_top_level0.v(99) | Removing wire dell_step, as there is no assignment to it.
@W:CG360 : apsram_top_level0.v(109) | Removing wire clk_x2p, as there is no assignment to it.
@W:CG360 : apsram_top_level0.v(110) | Removing wire clk_x1p, as there is no assignment to it.
@W:CG360 : apsram_top_level0.v(112) | Removing wire calib_div, as there is no assignment to it.
Running optimization stage 1 on \~apsram_top.psram_memory_interface_top_2ch  .......
@N:CG364 : apsram_top_level1.v(5) | Synthesizing module psram_memory_interface_top_2ch in library work.
@W:CG781 : apsram_top_level1.v(147) | Input pll_lock on instance u_psram_top0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : apsram_top_level1.v(175) | Input pll_lock on instance u_psram_top1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : apsram_top_level1.v(86) | Removing wire clk_x1p, as there is no assignment to it.
@W:CG360 : apsram_top_level1.v(87) | Removing wire clk_x2p, as there is no assignment to it.
Running optimization stage 1 on psram_memory_interface_top_2ch .......
@N:CG364 : apsram_test.v(2) | Synthesizing module apsram_test in library work.
@W:CS142 : apsram_test.v(9) | Range of port wr_data in port declaration and body are different.
@N:CG179 : apsram_test.v(186) | Removing redundant assignment.
@A:CG412 : apsram_test.v(276) | Treating === and !== as == and != -- possible simulation mismatch
Running optimization stage 1 on apsram_test .......
@W:CL207 : apsram_test.v(156) | All reachable assignments to data_mask[3:0] assign 0, register removed by optimization.
@W:CL190 : apsram_test.v(156) | Optimizing register bit addr_add_r[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : apsram_test.v(156) | Optimizing register bit addr_add_w[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr_add_r[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr_add_w[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : apsram_syn_top.v(2) | Synthesizing module psram_syn_top in library work.
@W:CS263 : apsram_syn_top.v(184) | Port-width mismatch for port wr_data. The port definition is 64 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W:CS263 : apsram_syn_top.v(202) | Port-width mismatch for port wr_data. The port definition is 64 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W:CG360 : apsram_syn_top.v(49) | Removing wire init_done0, as there is no assignment to it.
@W:CG360 : apsram_syn_top.v(58) | Removing wire init_done1, as there is no assignment to it.
Running optimization stage 1 on psram_syn_top .......
Running optimization stage 2 on psram_syn_top .......
@W:CL260 : apsram_syn_top.v(74) | Pruning register bit 1 of led[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Running optimization stage 2 on apsram_test .......
@W:CL190 : apsram_test.v(156) | Optimizing register bit addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL201 : apsram_test.v(84) | Trying to extract state machine for register curr_state.
Extracted state machine for register curr_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Running optimization stage 2 on psram_memory_interface_top_2ch .......
Running optimization stage 2 on \~apsram_top.psram_memory_interface_top_2ch  .......
@W:CL156 : apsram_top_level0.v(110) | *Input clk_x1p to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W:CL156 : apsram_top_level0.v(109) | *Input clk_x2p to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@N:CL159 : apsram_top_level0.v(37) | Input clk is unused.
@N:CL159 : apsram_top_level0.v(41) | Input pll_lock is unused.
Running optimization stage 2 on \~apsram_init.psram_memory_interface_top_2ch  .......
@W:CL260 : apsram_init.v(345) | Pruning register bit 31 of genblk1.init_dq[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : apsram_init.v(345) | Pruning register bits 29 to 3 of genblk1.init_dq[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL177 : apsram_init.v(363) | Sharing sequential element init_dqts. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : apsram_init.v(169) | Trying to extract state machine for register c_state.
Extracted state machine for register c_state
State machine has 19 reachable states with original encodings of:
   0000000000000000001
   0000000000000000010
   0000000000000000100
   0000000000000001000
   0000000000000010000
   0000000000000100000
   0000000000001000000
   0000000000010000000
   0000000000100000000
   0000000001000000000
   0000000010000000000
   0000000100000000000
   0000001000000000000
   0000010000000000000
   0000100000000000000
   0001000000000000000
   0010000000000000000
   0100000000000000000
   1000000000000000000
@W:CL279 : apsram_init.v(442) | Pruning register bits 2 to 1 of burst_num[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : apsram_init.v(442) | Pruning register bits 9 to 7 of wr_data[9:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : apsram_init.v(442) | Pruning register bit 15 of wr_data[15:12]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : apsram_init.v(442) | Pruning register bits 24 to 20 of wr_data[24:17]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : apsram_init.v(442) | Pruning register bits 31 to 29 of wr_data[31:26]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@A:CL153 : apsram_init.v(69) | *Unassigned bits of STEN[0] are referenced and tied to 0 -- simulation mismatch possible.
@N:CL159 : apsram_init.v(56) | Input DF is unused.
Running optimization stage 2 on OBUF .......
Running optimization stage 2 on TBUF .......
Running optimization stage 2 on ELVDS_OBUF .......
Running optimization stage 2 on IODELAY .......
Running optimization stage 2 on IOBUF .......
Running optimization stage 2 on IDES4 .......
Running optimization stage 2 on \~apsram_lane.psram_memory_interface_top_2ch  .......
@W:CL177 : apsram_lane.v(544) | Sharing sequential element genblk8.dqtx1. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : apsram_lane.v(184) | Trying to extract state machine for register c_state.
Extracted state machine for register c_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@N:CL159 : apsram_lane.v(51) | Input clk_x2p is unused.
@N:CL159 : apsram_lane.v(59) | Input wr_en is unused.
@N:CL159 : apsram_lane.v(68) | Input dqs is unused.
Running optimization stage 2 on OSER4 .......
Running optimization stage 2 on \~apsram_wd.psram_memory_interface_top_2ch  .......
@N:CL159 : apsram_wd.v(46) | Input clk_x1p is unused.
@N:CL159 : apsram_wd.v(48) | Input clk_x2p is unused.
@N:CL159 : apsram_wd.v(67) | Input STEN is unused.
Running optimization stage 2 on \~apsram_sync.psram_memory_interface_top_2ch  .......
@N:CL201 : apsram_sync.v(139) | Trying to extract state machine for register flag.
Extracted state machine for register flag
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Running optimization stage 2 on CLKDIV .......
Running optimization stage 2 on DHCEN .......
Running optimization stage 2 on DLL .......
Running optimization stage 2 on PLL .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 113MB peak: 119MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Feb 22 14:30:25 2021

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Feb 22 14:30:25 2021

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  fpga_project_1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 33MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Mon Feb 22 14:30:25 2021

###########################################################]


###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @

@N: :  | Running in 64-bit mode 
File D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\impl\synthesize\rev_1\synwork\fpga_project_1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Feb 22 14:30:26 2021

###########################################################]


# Mon Feb 22 14:30:27 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys Generic Technology Pre-mapping, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB)

@A:MF827 :  | No constraint file specified. 
Linked File:  fpga_project_1_scck.rpt
See clock summary report "D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\impl\synthesize\rev_1\fpga_project_1_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)

@N:MO111 : apsram_lane.v(87) | Tristate driver test0 (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog)) on net test0 (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog)) has its enable tied to GND.
@N:MO111 : apsram_lane.v(70) | Tristate driver recalib (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog)) on net recalib (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog)) has its enable tied to GND.
@W:BN132 : apsram_init.v(442) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[4:2] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[14:12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[28:26] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[19:17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN114 : apsram_wd.v(220) | Removing instance dqs_iodelay_gen\[0\]\.iodelay_dqs (in view: work.\\\~apsram_wd\.psram_memory_interface_top_2ch\ _0(verilog)) of black box view:GOWIN.IODELAY(PRIM) because it does not drive other instances.
@W:BN114 : apsram_wd.v(220) | Removing instance dqs_iodelay_gen\[0\]\.iodelay_dqs (in view: work.\\\~apsram_wd\.psram_memory_interface_top_2ch\ _1(verilog)) of black box view:GOWIN.IODELAY(PRIM) because it does not drive other instances.
@W:BN114 : apsram_lane.v(774) | Removing instance genclkpos\.u_ckn_gen (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _0(verilog)) of black box view:GOWIN.OSER4(PRIM) because it does not drive other instances.
@N:BN362 : apsram_init.v(496) | Removing sequential instance wr_en (in view: work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@W:BN114 : apsram_lane.v(774) | Removing instance genclkpos\.u_ckn_gen (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _1(verilog)) of black box view:GOWIN.OSER4(PRIM) because it does not drive other instances.
@N:BN362 : apsram_init.v(496) | Removing sequential instance wr_en (in view: work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : apsram_test.v(217) | Removing sequential instance wr_en (in view: work.apsram_test_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : apsram_test.v(217) | Removing sequential instance wr_en (in view: work.apsram_test_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine flag[2:0] (in view: work.\\\~apsram_sync\.psram_memory_interface_top_2ch\ (verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine c_state[7:0] (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _0(verilog))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine c_state[18:0] (in view: work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog))
original code -> new code
   0000000000000000001 -> 0000000000000000001
   0000000000000000010 -> 0000000000000000010
   0000000000000000100 -> 0000000000000000100
   0000000000000001000 -> 0000000000000001000
   0000000000000010000 -> 0000000000000010000
   0000000000000100000 -> 0000000000000100000
   0000000000001000000 -> 0000000000001000000
   0000000000010000000 -> 0000000000010000000
   0000000000100000000 -> 0000000000100000000
   0000000001000000000 -> 0000000001000000000
   0000000010000000000 -> 0000000010000000000
   0000000100000000000 -> 0000000100000000000
   0000001000000000000 -> 0000001000000000000
   0000010000000000000 -> 0000010000000000000
   0000100000000000000 -> 0000100000000000000
   0001000000000000000 -> 0001000000000000000
   0010000000000000000 -> 0010000000000000000
   0100000000000000000 -> 0100000000000000000
   1000000000000000000 -> 1000000000000000000
Encoding state machine c_state[7:0] (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _1(verilog))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine c_state[18:0] (in view: work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog))
original code -> new code
   0000000000000000001 -> 0000000000000000001
   0000000000000000010 -> 0000000000000000010
   0000000000000000100 -> 0000000000000000100
   0000000000000001000 -> 0000000000000001000
   0000000000000010000 -> 0000000000000010000
   0000000000000100000 -> 0000000000000100000
   0000000000001000000 -> 0000000000001000000
   0000000000010000000 -> 0000000000010000000
   0000000000100000000 -> 0000000000100000000
   0000000001000000000 -> 0000000001000000000
   0000000010000000000 -> 0000000010000000000
   0000000100000000000 -> 0000000100000000000
   0000001000000000000 -> 0000001000000000000
   0000010000000000000 -> 0000010000000000000
   0000100000000000000 -> 0000100000000000000
   0001000000000000000 -> 0001000000000000000
   0010000000000000000 -> 0010000000000000000
   0100000000000000000 -> 0100000000000000000
   1000000000000000000 -> 1000000000000000000
Encoding state machine curr_state[7:0] (in view: work.apsram_test_1(verilog))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine curr_state[7:0] (in view: work.apsram_test_0(verilog))
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 242MB peak: 242MB)

@N:MF578 :  | Incompatible asynchronous control logic preventing generated clock conversion. 

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB)



Clock Summary
******************

          Start                                                                                            Requested     Requested     Clock                                                                    Clock                     Clock
Level     Clock                                                                                            Frequency     Period        Type                                                                     Group                     Load 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       System                                                                                           100.0 MHz     10.000        system                                                                   system_clkgroup           0    
                                                                                                                                                                                                                                               
0 -       psram_memory_interface_top_2ch|clk_out_inferred_clock                                            150.2 MHz     6.660         inferred                                                                 Autoconstr_clkgroup_1     1578 
1 .         _~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0]     150.2 MHz     6.660         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1     8    
1 .         _~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0]     150.2 MHz     6.660         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1     8    
1 .         _~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0]                            150.2 MHz     6.660         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1     2    
1 .         _~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0]                            150.2 MHz     6.660         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1     2    
                                                                                                                                                                                                                                               
0 -       psram_memory_interface_top_2ch|clk_x2_inferred_clock                                             100.0 MHz     10.000        inferred                                                                 Autoconstr_clkgroup_2     40   
                                                                                                                                                                                                                                               
0 -       psram_syn_top|memory_clk_inferred_clock                                                          252.8 MHz     3.955         inferred                                                                 Autoconstr_clkgroup_0     33   
                                                                                                                                                                                                                                               
0 -       psram_syn_top|clk_d_inferred_clock                                                               206.8 MHz     4.836         inferred                                                                 Autoconstr_clkgroup_3     31   
===============================================================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                                               Clock     Source                                                                                Clock Pin                                                                                 Non-clock Pin                                                                                           Non-clock Pin
Clock                                                                                          Load      Pin                                                                                   Seq Example                                                                               Seq Example                                                                                             Comb Example 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                                         0         -                                                                                     -                                                                                         -                                                                                                       -            
                                                                                                                                                                                                                                                                                                                                                                                                              
psram_memory_interface_top_2ch|clk_out_inferred_clock                                          1578      u_PSRAM_TOP.clkdiv.CLKOUT(CLKDIV)                                                     u_test1.cyc_done_d.C                                                                      u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4.PCLK     -            
_~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0]     8         u_PSRAM_TOP.u_psram_top0.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0](dffre)     u_PSRAM_TOP.u_psram_top0.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[3\]\.iodelay.VALUE     -                                                                                                       -            
_~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0]     8         u_PSRAM_TOP.u_psram_top1.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0](dffre)     u_PSRAM_TOP.u_psram_top1.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[3\]\.iodelay.VALUE     -                                                                                                       -            
_~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0]                            2         u_PSRAM_TOP.u_psram_top0.u_psram_wd.step[8:0].Q[0](dffr)                              u_PSRAM_TOP.u_psram_top0.u_psram_wd.ck_delay\[0\]\.iodelay.VALUE                          -                                                                                                       -            
_~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0]                            2         u_PSRAM_TOP.u_psram_top1.u_psram_wd.step[8:0].Q[0](dffr)                              u_PSRAM_TOP.u_psram_top1.u_psram_wd.ck_delay\[0\]\.iodelay.VALUE                          -                                                                                                       -            
                                                                                                                                                                                                                                                                                                                                                                                                              
psram_memory_interface_top_2ch|clk_x2_inferred_clock                                           40        u_PSRAM_TOP.u_dhcen_clk_x2.CLKOUT(DHCEN)                                              u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.mask_oser4.FCLK      -                                                                                                       -            
                                                                                                                                                                                                                                                                                                                                                                                                              
psram_syn_top|memory_clk_inferred_clock                                                        33        u_PLL.CLKOUT(PLL)                                                                     led_1[0].C                                                                                -                                                                                                       -            
                                                                                                                                                                                                                                                                                                                                                                                                              
psram_syn_top|clk_d_inferred_clock                                                             31        u_PLL.CLKOUTD(PLL)                                                                    u_PSRAM_TOP.u_psram_sync.dll_rst.C                                                        -                                                                                                       -            
==============================================================================================================================================================================================================================================================================================================================================================================================================

@W:MT529 : apsram_syn_top.v(65) | Found inferred clock psram_syn_top|memory_clk_inferred_clock which controls 33 sequential elements including cnt[31:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : apsram_lane.v(184) | Found inferred clock psram_memory_interface_top_2ch|clk_out_inferred_clock which controls 1578 sequential elements including u_PSRAM_TOP.u_psram_top0.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.c_state[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : apsram_lane.v(756) | Found inferred clock psram_memory_interface_top_2ch|clk_x2_inferred_clock which controls 40 sequential elements including u_PSRAM_TOP.u_psram_top0.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.genclkpos\.u_ck_gen. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : apsram_sync.v(139) | Found inferred clock psram_syn_top|clk_d_inferred_clock which controls 31 sequential elements including u_PSRAM_TOP.u_psram_sync.flag[1]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

4 non-gated/non-generated clock tree(s) driving 1666 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 20 clock pin(s) of sequential element(s)
0 instances converted, 20 sequential instances remain driven by gated/generated clocks

========================================================================= Non-Gated/Non-Generated Clocks =========================================================================
Clock Tree ID     Driving Element                       Drive Element Type     Fanout     Sample Instance                                                                         
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_0       u_PSRAM_TOP.clkdiv.CLKOUT             CLKDIV                 1562       u_PSRAM_TOP.u_psram_top1.rdbk_data[31:0]                                                
ClockId_0_1       u_PSRAM_TOP.u_dhcen_clk_x2.CLKOUT     DHCEN                  40         u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.genclkpos\.u_ck_gen
ClockId_0_10      u_PLL.CLKOUTD                         PLL                    31         u_PSRAM_TOP.u_psram_sync.flag[1]                                                        
ClockId_0_11      u_PLL.CLKOUT                          PLL                    33         cnt[31:0]                                                                               
==================================================================================================================================================================================
========================================================================================================================== Gated/Generated Clocks ===========================================================================================================================
Clock Tree ID     Driving Element                                                                Drive Element Type     Unconverted Fanout     Sample Instance                                                                     Explanation                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId_0_2       u_PSRAM_TOP.u_psram_top1.u_psram_wd.step[8:0].Q[0]                             dffr                   2                      u_PSRAM_TOP.u_psram_top1.u_psram_wd.dqs_delay\[0\]\.iodelaydqs                      Derived clock on input (not legal for GCC)
ClockId_0_4       u_PSRAM_TOP.u_psram_top1.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0]     dffre                  8                      u_PSRAM_TOP.u_psram_top1.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[4\]\.iodelay     Derived clock on input (not legal for GCC)
ClockId_0_6       u_PSRAM_TOP.u_psram_top0.u_psram_wd.step[8:0].Q[0]                             dffr                   2                      u_PSRAM_TOP.u_psram_top0.u_psram_wd.dqs_delay\[0\]\.iodelaydqs                      Derived clock on input (not legal for GCC)
ClockId_0_8       u_PSRAM_TOP.u_psram_top0.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0]     dffre                  8                      u_PSRAM_TOP.u_psram_top0.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[4\]\.iodelay     Derived clock on input (not legal for GCC)
=============================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\impl\synthesize\rev_1\fpga_project_1.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 243MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 243MB peak: 244MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 245MB peak: 245MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 245MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Mon Feb 22 14:30:29 2021

###########################################################]


# Mon Feb 22 14:30:29 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03G-Beta1
Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro
OS: Windows 6.2

Hostname: JN-IP-SHANGYAN

Implementation : rev_1
Synopsys Generic Technology Mapper, Version mapgw2020q1p1, Build 004R, Built Jun 18 2020 10:25:53, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 137MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 229MB peak: 229MB)

@W:BN132 : apsram_top_level0.v(143) | Removing sequential instance u_PSRAM_TOP.u_psram_top0.rdbk_data[31:0] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.rd_data_d[31:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(540) | Removing sequential instance u_PSRAM_TOP.u_psram_top0.u_psram_init.timer_cnt1_clr because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_top_level0.v(143) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.rdbk_data[31:0] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.rd_data_d[31:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(540) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.timer_cnt1_clr because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 
@W:BN132 : apsram_init.v(532) | Removing sequential instance u_PSRAM_TOP.u_psram_top0.u_psram_init.read_over_rep because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.read_over. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(169) | Removing sequential instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state_rep_0[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state_rep[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(169) | Removing sequential instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state_rep[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(532) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.read_over_rep because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.read_over. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(169) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state_rep_0[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state_rep[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(169) | Removing sequential instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state_rep[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test0.curr_state_rep_2[7] because it is equivalent to instance u_test0.curr_state_rep_1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test0.curr_state_rep_1[7] because it is equivalent to instance u_test0.curr_state_rep_0[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test0.curr_state_rep_0[7] because it is equivalent to instance u_test0.curr_state_rep[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test0.curr_state_rep[7] because it is equivalent to instance u_test0.curr_state[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test1.curr_state_rep_2[7] because it is equivalent to instance u_test1.curr_state_rep_1[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test1.curr_state_rep_1[7] because it is equivalent to instance u_test1.curr_state_rep_0[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test1.curr_state_rep_0[7] because it is equivalent to instance u_test1.curr_state_rep[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(84) | Removing sequential instance u_test1.curr_state_rep[7] because it is equivalent to instance u_test1.curr_state[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(239) | Removing user instance u_test0.un1_burst_wnum[9:0] because it is equivalent to instance u_test0.un1_burst_rnum[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(225) | Removing sequential instance u_test0.burst_wnum[9:0] because it is equivalent to instance u_test0.burst_rnum[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(239) | Removing user instance u_test1.un1_burst_wnum[9:0] because it is equivalent to instance u_test1.un1_burst_rnum[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_test.v(225) | Removing sequential instance u_test1.burst_wnum[9:0] because it is equivalent to instance u_test1.burst_rnum[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 234MB peak: 234MB)

@N:MO231 : apsram_sync.v(113) | Found counter in view:work.\\\~apsram_sync\.psram_memory_interface_top_2ch\ (verilog) instance lock_cnt[15:0] 
@N:MO231 : apsram_wd.v(246) | Found counter in view:work.\\\~apsram_wd\.psram_memory_interface_top_2ch\ _0(verilog) instance step[8:0] 
@N:MO231 : apsram_lane.v(223) | Found counter in view:work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _0(verilog) instance burst_cnt[9:0] 
@N:MF179 :  | Found 10 by 10 bit equality operator ('==') genblk1\.un1_burst_cnt (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ _0(verilog)) 
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[19] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[18] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[13] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[17] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.wr_data_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : apsram_init.v(266) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance tvcs_cnt[15:0] 
@N:MO231 : apsram_init.v(639) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance read_calibration\[0\]\.check_cnt[5:0] 
@N:MO231 : apsram_init.v(652) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance read_calibration\[0\]\.times_reg[4:0] 
@N:MO231 : apsram_init.v(300) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance tRST_cnt[7:0] 
@N:MO231 : apsram_init.v(524) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance read_cnt[8:0] 
@N:MO231 : apsram_init.v(427) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance timer_cnt0[5:0] 
@N:MO231 : apsram_init.v(561) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance timer_cnt1[5:0] 
@N:MO231 : apsram_init.v(548) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _0(verilog) instance phase_cnt[4:0] 
@N:MO231 : apsram_wd.v(246) | Found counter in view:work.\\\~apsram_wd\.psram_memory_interface_top_2ch\ _1(verilog) instance step[8:0] 
@N:MO231 : apsram_lane.v(223) | Found counter in view:work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog) instance burst_cnt[9:0] 
@N:MF179 :  | Found 10 by 10 bit equality operator ('==') genblk1\.un1_burst_cnt (in view: work.\\\~apsram_lane\.psram_memory_interface_top_2ch\ (verilog)) 
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[19] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[14] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[18] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[13] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(442) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[17] because it is equivalent to instance u_PSRAM_TOP.u_psram_top1.u_psram_init.wr_data_1[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO231 : apsram_init.v(266) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance tvcs_cnt[15:0] 
@N:MO231 : apsram_init.v(639) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance read_calibration\[0\]\.check_cnt[5:0] 
@N:MO231 : apsram_init.v(652) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance read_calibration\[0\]\.times_reg[4:0] 
@N:MO231 : apsram_init.v(300) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance tRST_cnt[7:0] 
@N:MO231 : apsram_init.v(524) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance read_cnt[8:0] 
@N:MO231 : apsram_init.v(427) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance timer_cnt0[5:0] 
@N:MO231 : apsram_init.v(561) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance timer_cnt1[5:0] 
@N:MO231 : apsram_init.v(548) | Found counter in view:work.\\\~apsram_init\.psram_memory_interface_top_2ch\ _1(verilog) instance phase_cnt[4:0] 
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[32] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[33] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[34] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[35] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[36] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[37] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[38] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[39] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[40] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[41] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[42] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[43] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[44] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[45] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[46] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[47] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[48] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[49] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[50] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[51] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[52] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[53] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[54] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[55] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[56] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[57] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[58] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[59] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[60] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[61] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[62] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[63] (in view: work.apsram_test_1(verilog)) because it does not drive other instances.
@N:MO231 : apsram_test.v(265) | Found counter in view:work.apsram_test_1(verilog) instance check_data[63:0] 
@N:MO231 : apsram_test.v(156) | Found counter in view:work.apsram_test_1(verilog) instance wr_data_add[63:0] 
@N:MO231 : apsram_test.v(242) | Found counter in view:work.apsram_test_1(verilog) instance cyc_cnt[9:0] 
@N:MO231 : apsram_test.v(145) | Found counter in view:work.apsram_test_1(verilog) instance RD_CNT[9:0] 
@N:MO231 : apsram_test.v(132) | Found counter in view:work.apsram_test_1(verilog) instance WR_CNT[9:0] 
@N:MF179 : apsram_test.v(276) | Found 16 by 16 bit equality operator ('==') un1_check_data_0 (in view: work.apsram_test_1(verilog))
@N:MF179 : apsram_test.v(276) | Found 16 by 16 bit equality operator ('==') un1_check_data_2 (in view: work.apsram_test_1(verilog))
@N:MF179 : apsram_test.v(98) | Found 10 by 10 bit equality operator ('==') next_state9 (in view: work.apsram_test_1(verilog))
@N:MF179 : apsram_test.v(109) | Found 10 by 10 bit equality operator ('==') next_state19 (in view: work.apsram_test_1(verilog))
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[32] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[33] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[34] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[35] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[36] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[37] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[38] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[39] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[40] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[41] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[42] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[43] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[44] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[45] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[46] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[47] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[48] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[49] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[50] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[51] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[52] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[53] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[54] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[55] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[56] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[57] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[58] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[59] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[60] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[61] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[62] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance wr_data[63] (in view: work.apsram_test_0(verilog)) because it does not drive other instances.
@N:MO231 : apsram_test.v(265) | Found counter in view:work.apsram_test_0(verilog) instance check_data[63:0] 
@N:MO231 : apsram_test.v(156) | Found counter in view:work.apsram_test_0(verilog) instance wr_data_add[63:0] 
@N:MO231 : apsram_test.v(242) | Found counter in view:work.apsram_test_0(verilog) instance cyc_cnt[9:0] 
@N:MO231 : apsram_test.v(145) | Found counter in view:work.apsram_test_0(verilog) instance RD_CNT[9:0] 
@N:MO231 : apsram_test.v(132) | Found counter in view:work.apsram_test_0(verilog) instance WR_CNT[9:0] 
@N:MF179 : apsram_test.v(276) | Found 16 by 16 bit equality operator ('==') un1_check_data_0 (in view: work.apsram_test_0(verilog))
@N:MF179 : apsram_test.v(276) | Found 16 by 16 bit equality operator ('==') un1_check_data_2 (in view: work.apsram_test_0(verilog))
@N:MF179 : apsram_test.v(98) | Found 10 by 10 bit equality operator ('==') next_state9 (in view: work.apsram_test_0(verilog))
@N:MF179 : apsram_test.v(109) | Found 10 by 10 bit equality operator ('==') next_state19 (in view: work.apsram_test_0(verilog))

Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 241MB peak: 241MB)

@N:BN362 : apsram_lane.v(170) | Removing sequential instance u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.CA_reg[0] (in view: work.\\\~apsram_top\.psram_memory_interface_top_2ch\ _1(verilog)) because it does not drive other instances.
@N:BN362 : apsram_lane.v(170) | Removing sequential instance u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.CA_reg[0] (in view: work.\\\~apsram_top\.psram_memory_interface_top_2ch\ _0(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 249MB peak: 249MB)

@W:BN132 : apsram_wd.v(234) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_wd.dll_lock_d0 because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_wd.dll_lock_d0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(260) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.ready_d[0] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.ready_d[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(169) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.c_state[0] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.c_state[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_init.v(260) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_init.ready_d[1] because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_init.ready_d[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : apsram_wd.v(234) | Removing instance u_PSRAM_TOP.u_psram_top1.u_psram_wd.dll_lock_d because it is equivalent to instance u_PSRAM_TOP.u_psram_top0.u_psram_wd.dll_lock_d. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 254MB peak: 254MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 255MB peak: 255MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:05s; Memory used current: 255MB peak: 255MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:05s; Memory used current: 255MB peak: 255MB)

@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[63] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[62] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[61] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[60] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[59] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[58] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[57] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[56] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[55] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[54] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[53] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[52] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[51] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[50] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[49] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[48] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[47] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[46] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[45] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[44] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[43] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[42] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[41] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[40] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[39] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[38] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[37] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[36] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[35] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[34] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[33] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test1.wr_data_add[32] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test0.wr_data_add[63] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.
@N:BN362 : apsram_test.v(156) | Removing sequential instance u_test0.wr_data_add[62] (in view: work.psram_syn_top(verilog)) because it does not drive other instances.

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\impl\synthesize\rev_1\synlog\fpga_project_1_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.

Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 255MB peak: 255MB)


Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 263MB peak: 263MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:06s		    -2.70ns		1992 /      1371
   2		0h:00m:06s		    -2.70ns		1990 /      1371
   3		0h:00m:06s		    -2.70ns		1989 /      1371
   4		0h:00m:06s		    -2.70ns		1989 /      1371
   5		0h:00m:06s		    -2.70ns		1988 /      1371
   6		0h:00m:07s		    -2.70ns		1987 /      1371
@N:FX271 : apsram_init.v(581) | Replicating instance u_PSRAM_TOP.u_psram_top0.u_psram_init.read_calibration\[0\]\.wr_ptr[2] (in view: work.psram_syn_top(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : apsram_init.v(581) | Replicating instance u_PSRAM_TOP.u_psram_top1.u_psram_init.read_calibration\[0\]\.wr_ptr[0] (in view: work.psram_syn_top(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : apsram_init.v(581) | Replicating instance u_PSRAM_TOP.u_psram_top1.u_psram_init.read_calibration\[0\]\.wr_ptr[2] (in view: work.psram_syn_top(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : apsram_init.v(581) | Replicating instance u_PSRAM_TOP.u_psram_top0.u_psram_init.read_calibration\[0\]\.wr_ptr[0] (in view: work.psram_syn_top(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : apsram_init.v(688) | Replicating instance u_PSRAM_TOP.u_psram_top0.u_psram_init.init_calib (in view: work.psram_syn_top(verilog)) with 105 loads 3 times to improve timing.
@N:FX271 : apsram_init.v(688) | Replicating instance u_PSRAM_TOP.u_psram_top1.u_psram_init.init_calib (in view: work.psram_syn_top(verilog)) with 105 loads 3 times to improve timing.
@N:FX271 : apsram_test.v(84) | Replicating instance u_test1.curr_state[7] (in view: work.psram_syn_top(verilog)) with 30 loads 2 times to improve timing.
@N:FX271 : apsram_test.v(84) | Replicating instance u_test0.curr_state[7] (in view: work.psram_syn_top(verilog)) with 30 loads 2 times to improve timing.
Timing driven replication report
Added 14 Registers via timing driven replication
Added 8 LUTs via timing driven replication

   7		0h:00m:07s		    -2.43ns		2035 /      1385
   8		0h:00m:07s		    -2.88ns		2033 /      1385
   9		0h:00m:07s		    -2.63ns		2032 /      1385
  10		0h:00m:07s		    -2.67ns		2032 /      1385
  11		0h:00m:07s		    -2.41ns		2032 /      1385
  12		0h:00m:07s		    -3.20ns		2034 /      1385
  13		0h:00m:07s		    -3.20ns		2034 /      1385
  14		0h:00m:07s		    -2.67ns		2034 /      1385
  15		0h:00m:08s		    -2.67ns		2035 /      1385
@N:FX271 : apsram_syn_top.v(65) | Replicating instance cnt[13] (in view: work.psram_syn_top(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : apsram_syn_top.v(65) | Replicating instance cnt[16] (in view: work.psram_syn_top(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : apsram_init.v(688) | Replicating instance u_PSRAM_TOP.u_psram_top0.u_psram_init.init_calib_fast (in view: work.psram_syn_top(verilog)) with 17 loads 2 times to improve timing.
Timing driven replication report
Added 4 Registers via timing driven replication
Added 0 LUTs via timing driven replication


  16		0h:00m:08s		    -3.02ns		2029 /      1389
  17		0h:00m:08s		    -2.67ns		2029 /      1389
  18		0h:00m:08s		    -2.67ns		2029 /      1389
  19		0h:00m:08s		    -2.67ns		2031 /      1389
  20		0h:00m:08s		    -2.67ns		2031 /      1389
  21		0h:00m:08s		    -2.67ns		2031 /      1389

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 269MB peak: 269MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@W:MT453 :  | clock period is too long for clock psram_syn_top|clk_d_inferred_clock, changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  
@W:MT453 :  | clock period is too long for clock _~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0], changing period from 100000.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 50000.0 ns to 10000.0 ns.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 270MB peak: 270MB)


Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 190MB peak: 271MB)

Writing Analyst data base D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\impl\synthesize\rev_1\synwork\fpga_project_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:09s; Memory used current: 268MB peak: 271MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 269MB peak: 271MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 269MB peak: 271MB)


Start final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 265MB peak: 271MB)

@W:MT246 : apsram_syn_top.v(85) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : apsram_top_level1.v(120) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : apsram_top_level1.v(111) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : apsram_top_level1.v(101) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 :  | Found inferred clock psram_syn_top|memory_clk_inferred_clock with period 5.61ns. Please declare a user-defined clock on net memory_clk. 
@W:MT420 :  | Found inferred clock psram_memory_interface_top_2ch|clk_out_inferred_clock with period 8.62ns. Please declare a user-defined clock on net u_PSRAM_TOP.clk_x1. 
@W:MT420 :  | Found inferred clock psram_memory_interface_top_2ch|clk_x2_inferred_clock with period 10.00ns. Please declare a user-defined clock on net u_PSRAM_TOP.clk_x2. 
@W:MT420 :  | Found inferred clock psram_syn_top|clk_d_inferred_clock with period 5.93ns. Please declare a user-defined clock on net clk_d. 
@N:MT615 :  | Found clock _~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0] with period 20000.00ns  
@N:MT615 :  | Found clock _~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0] with period 20000.00ns  
@N:MT615 :  | Found clock _~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0] with period 20000.00ns  
@N:MT615 :  | Found clock _~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0] with period 20000.00ns  


##### START OF TIMING REPORT #####[
# Timing report written on Mon Feb 22 14:30:42 2021
#


Top view:               psram_syn_top
Requested Frequency:    0.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -1.522

                                                                                               Requested     Estimated     Requested     Estimated                Clock                                                                    Clock                
Starting Clock                                                                                 Frequency     Frequency     Period        Period        Slack      Type                                                                     Group                
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
_~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0]     0.1 MHz       NA            20000.000     NA            NA         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1
_~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0]     0.1 MHz       NA            20000.000     NA            NA         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1
_~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0]                            0.1 MHz       NA            20000.000     NA            NA         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1
_~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0]                            0.1 MHz       NA            20000.000     NA            NA         derived (from psram_memory_interface_top_2ch|clk_out_inferred_clock)     Autoconstr_clkgroup_1
psram_memory_interface_top_2ch|clk_out_inferred_clock                                          116.0 MHz     98.6 MHz      8.622         10.144        -1.522     inferred                                                                 Autoconstr_clkgroup_1
psram_memory_interface_top_2ch|clk_x2_inferred_clock                                           100.0 MHz     NA            10.000        NA            NA         inferred                                                                 Autoconstr_clkgroup_2
psram_syn_top|clk_d_inferred_clock                                                             168.5 MHz     143.2 MHz     5.934         6.981         -1.047     inferred                                                                 Autoconstr_clkgroup_3
psram_syn_top|memory_clk_inferred_clock                                                        178.1 MHz     151.4 MHz     5.614         6.605         -0.991     inferred                                                                 Autoconstr_clkgroup_0
System                                                                                         382.7 MHz     325.3 MHz     2.613         3.074         -0.461     system                                                                   system_clkgroup      
================================================================================================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





Clock Relationships
*******************

Clocks                                                                                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                               Ending                                                 |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                 System                                                 |  2.613       -0.461  |  No paths    -      |  No paths    -      |  No paths    -    
System                                                 psram_memory_interface_top_2ch|clk_out_inferred_clock  |  8.622       0.662   |  No paths    -      |  No paths    -      |  No paths    -    
System                                                 psram_syn_top|clk_d_inferred_clock                     |  5.934       3.681   |  No paths    -      |  No paths    -      |  No paths    -    
psram_syn_top|memory_clk_inferred_clock                psram_syn_top|memory_clk_inferred_clock                |  5.614       -0.991  |  No paths    -      |  No paths    -      |  No paths    -    
psram_memory_interface_top_2ch|clk_out_inferred_clock  psram_memory_interface_top_2ch|clk_out_inferred_clock  |  8.622       -1.522  |  No paths    -      |  No paths    -      |  No paths    -    
psram_memory_interface_top_2ch|clk_out_inferred_clock  psram_memory_interface_top_2ch|clk_x2_inferred_clock   |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
psram_syn_top|clk_d_inferred_clock                     System                                                 |  5.934       2.426   |  No paths    -      |  No paths    -      |  No paths    -    
psram_syn_top|clk_d_inferred_clock                     psram_memory_interface_top_2ch|clk_out_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
psram_syn_top|clk_d_inferred_clock                     psram_syn_top|clk_d_inferred_clock                     |  5.934       -1.047  |  No paths    -      |  No paths    -      |  No paths    -    
=====================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: psram_memory_interface_top_2ch|clk_out_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                          Starting                                                                                      Arrival           
Instance                  Reference                                                 Type      Pin     Net               Time        Slack 
                          Clock                                                                                                           
------------------------------------------------------------------------------------------------------------------------------------------
u_test1.curr_state[0]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFP      Q       curr_state[0]     0.367       -1.522
u_test0.curr_state[0]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFP      Q       curr_state[0]     0.367       -1.522
u_test1.cyc_done_d        psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFC      Q       cyc_done_d        0.367       -1.184
u_test0.cyc_done_d        psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFC      Q       cyc_done_d        0.367       -1.184
u_test0.check_data[0]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[0]     0.367       -1.028
u_test1.check_data[0]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[0]     0.367       -1.028
u_test1.check_data[1]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[1]     0.367       -0.971
u_test0.check_data[1]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[1]     0.367       -0.971
u_test1.check_data[2]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[2]     0.367       -0.913
u_test0.check_data[2]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     Q       check_data[2]     0.367       -0.913
==========================================================================================================================================


Ending Points with Worst Slack
******************************

                           Starting                                                                                         Required           
Instance                   Reference                                                 Type      Pin     Net                  Time         Slack 
                           Clock                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------
u_test0.check_data[63]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[63]     8.489        -1.522
u_test1.check_data[63]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[63]     8.489        -1.522
u_test0.check_data[62]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[62]     8.489        -1.465
u_test1.check_data[62]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[62]     8.489        -1.465
u_test0.check_data[61]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[61]     8.489        -1.408
u_test1.check_data[61]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[61]     8.489        -1.408
u_test1.check_data[60]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[60]     8.489        -1.351
u_test0.check_data[60]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[60]     8.489        -1.351
u_test1.check_data[59]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[59]     8.489        -1.294
u_test0.check_data[59]     psram_memory_interface_top_2ch|clk_out_inferred_clock     DFFCE     D       check_data_s[59]     8.489        -1.294
===============================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      10.011
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.522

    Number of logic level(s):                65
    Starting point:                          u_test1.curr_state[0] / Q
    Ending point:                            u_test1.check_data[63] / D
    The start point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                               Pin      Pin               Arrival      No. of    
Name                               Type      Name     Dir     Delay     Time         Fan Out(s)
-----------------------------------------------------------------------------------------------
u_test1.curr_state[0]              DFFP      Q        Out     0.367     0.367 r      -         
curr_state[0]                      Net       -        -       1.448     -            90        
u_test1.check_data_qxu_lofx[0]     LUT3      I1       In      -         1.815 r      -         
u_test1.check_data_qxu_lofx[0]     LUT3      F        Out     1.099     2.914 f      -         
check_data_qxu_lofx_0[0]           Net       -        -       1.021     -            1         
u_test1.check_data_cry_0[0]        ALU       I0       In      -         3.935 f      -         
u_test1.check_data_cry_0[0]        ALU       COUT     Out     0.958     4.893 f      -         
check_data_cry[0]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[1]        ALU       CIN      In      -         4.893 f      -         
u_test1.check_data_cry_0[1]        ALU       COUT     Out     0.057     4.950 f      -         
check_data_cry[1]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[2]        ALU       CIN      In      -         4.950 f      -         
u_test1.check_data_cry_0[2]        ALU       COUT     Out     0.057     5.007 f      -         
check_data_cry[2]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[3]        ALU       CIN      In      -         5.007 f      -         
u_test1.check_data_cry_0[3]        ALU       COUT     Out     0.057     5.064 f      -         
check_data_cry[3]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[4]        ALU       CIN      In      -         5.064 f      -         
u_test1.check_data_cry_0[4]        ALU       COUT     Out     0.057     5.121 f      -         
check_data_cry[4]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[5]        ALU       CIN      In      -         5.121 f      -         
u_test1.check_data_cry_0[5]        ALU       COUT     Out     0.057     5.178 f      -         
check_data_cry[5]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[6]        ALU       CIN      In      -         5.178 f      -         
u_test1.check_data_cry_0[6]        ALU       COUT     Out     0.057     5.235 f      -         
check_data_cry[6]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[7]        ALU       CIN      In      -         5.235 f      -         
u_test1.check_data_cry_0[7]        ALU       COUT     Out     0.057     5.292 f      -         
check_data_cry[7]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[8]        ALU       CIN      In      -         5.292 f      -         
u_test1.check_data_cry_0[8]        ALU       COUT     Out     0.057     5.349 f      -         
check_data_cry[8]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[9]        ALU       CIN      In      -         5.349 f      -         
u_test1.check_data_cry_0[9]        ALU       COUT     Out     0.057     5.406 f      -         
check_data_cry[9]                  Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[10]       ALU       CIN      In      -         5.406 f      -         
u_test1.check_data_cry_0[10]       ALU       COUT     Out     0.057     5.463 f      -         
check_data_cry[10]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[11]       ALU       CIN      In      -         5.463 f      -         
u_test1.check_data_cry_0[11]       ALU       COUT     Out     0.057     5.520 f      -         
check_data_cry[11]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[12]       ALU       CIN      In      -         5.520 f      -         
u_test1.check_data_cry_0[12]       ALU       COUT     Out     0.057     5.577 f      -         
check_data_cry[12]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[13]       ALU       CIN      In      -         5.577 f      -         
u_test1.check_data_cry_0[13]       ALU       COUT     Out     0.057     5.634 f      -         
check_data_cry[13]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[14]       ALU       CIN      In      -         5.634 f      -         
u_test1.check_data_cry_0[14]       ALU       COUT     Out     0.057     5.691 f      -         
check_data_cry[14]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[15]       ALU       CIN      In      -         5.691 f      -         
u_test1.check_data_cry_0[15]       ALU       COUT     Out     0.057     5.748 f      -         
check_data_cry[15]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[16]       ALU       CIN      In      -         5.748 f      -         
u_test1.check_data_cry_0[16]       ALU       COUT     Out     0.057     5.805 f      -         
check_data_cry[16]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[17]       ALU       CIN      In      -         5.805 f      -         
u_test1.check_data_cry_0[17]       ALU       COUT     Out     0.057     5.862 f      -         
check_data_cry[17]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[18]       ALU       CIN      In      -         5.862 f      -         
u_test1.check_data_cry_0[18]       ALU       COUT     Out     0.057     5.919 f      -         
check_data_cry[18]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[19]       ALU       CIN      In      -         5.919 f      -         
u_test1.check_data_cry_0[19]       ALU       COUT     Out     0.057     5.976 f      -         
check_data_cry[19]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[20]       ALU       CIN      In      -         5.976 f      -         
u_test1.check_data_cry_0[20]       ALU       COUT     Out     0.057     6.033 f      -         
check_data_cry[20]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[21]       ALU       CIN      In      -         6.033 f      -         
u_test1.check_data_cry_0[21]       ALU       COUT     Out     0.057     6.090 f      -         
check_data_cry[21]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[22]       ALU       CIN      In      -         6.090 f      -         
u_test1.check_data_cry_0[22]       ALU       COUT     Out     0.057     6.147 f      -         
check_data_cry[22]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[23]       ALU       CIN      In      -         6.147 f      -         
u_test1.check_data_cry_0[23]       ALU       COUT     Out     0.057     6.204 f      -         
check_data_cry[23]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[24]       ALU       CIN      In      -         6.204 f      -         
u_test1.check_data_cry_0[24]       ALU       COUT     Out     0.057     6.261 f      -         
check_data_cry[24]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[25]       ALU       CIN      In      -         6.261 f      -         
u_test1.check_data_cry_0[25]       ALU       COUT     Out     0.057     6.318 f      -         
check_data_cry[25]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[26]       ALU       CIN      In      -         6.318 f      -         
u_test1.check_data_cry_0[26]       ALU       COUT     Out     0.057     6.375 f      -         
check_data_cry[26]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[27]       ALU       CIN      In      -         6.375 f      -         
u_test1.check_data_cry_0[27]       ALU       COUT     Out     0.057     6.432 f      -         
check_data_cry[27]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[28]       ALU       CIN      In      -         6.432 f      -         
u_test1.check_data_cry_0[28]       ALU       COUT     Out     0.057     6.489 f      -         
check_data_cry[28]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[29]       ALU       CIN      In      -         6.489 f      -         
u_test1.check_data_cry_0[29]       ALU       COUT     Out     0.057     6.546 f      -         
check_data_cry[29]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[30]       ALU       CIN      In      -         6.546 f      -         
u_test1.check_data_cry_0[30]       ALU       COUT     Out     0.057     6.603 f      -         
check_data_cry[30]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[31]       ALU       CIN      In      -         6.603 f      -         
u_test1.check_data_cry_0[31]       ALU       COUT     Out     0.057     6.660 f      -         
check_data_cry[31]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[32]       ALU       CIN      In      -         6.660 f      -         
u_test1.check_data_cry_0[32]       ALU       COUT     Out     0.057     6.717 f      -         
check_data_cry[32]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[33]       ALU       CIN      In      -         6.717 f      -         
u_test1.check_data_cry_0[33]       ALU       COUT     Out     0.057     6.774 f      -         
check_data_cry[33]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[34]       ALU       CIN      In      -         6.774 f      -         
u_test1.check_data_cry_0[34]       ALU       COUT     Out     0.057     6.831 f      -         
check_data_cry[34]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[35]       ALU       CIN      In      -         6.831 f      -         
u_test1.check_data_cry_0[35]       ALU       COUT     Out     0.057     6.888 f      -         
check_data_cry[35]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[36]       ALU       CIN      In      -         6.888 f      -         
u_test1.check_data_cry_0[36]       ALU       COUT     Out     0.057     6.945 f      -         
check_data_cry[36]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[37]       ALU       CIN      In      -         6.945 f      -         
u_test1.check_data_cry_0[37]       ALU       COUT     Out     0.057     7.002 f      -         
check_data_cry[37]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[38]       ALU       CIN      In      -         7.002 f      -         
u_test1.check_data_cry_0[38]       ALU       COUT     Out     0.057     7.059 f      -         
check_data_cry[38]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[39]       ALU       CIN      In      -         7.059 f      -         
u_test1.check_data_cry_0[39]       ALU       COUT     Out     0.057     7.116 f      -         
check_data_cry[39]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[40]       ALU       CIN      In      -         7.116 f      -         
u_test1.check_data_cry_0[40]       ALU       COUT     Out     0.057     7.173 f      -         
check_data_cry[40]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[41]       ALU       CIN      In      -         7.173 f      -         
u_test1.check_data_cry_0[41]       ALU       COUT     Out     0.057     7.230 f      -         
check_data_cry[41]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[42]       ALU       CIN      In      -         7.230 f      -         
u_test1.check_data_cry_0[42]       ALU       COUT     Out     0.057     7.287 f      -         
check_data_cry[42]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[43]       ALU       CIN      In      -         7.287 f      -         
u_test1.check_data_cry_0[43]       ALU       COUT     Out     0.057     7.344 f      -         
check_data_cry[43]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[44]       ALU       CIN      In      -         7.344 f      -         
u_test1.check_data_cry_0[44]       ALU       COUT     Out     0.057     7.401 f      -         
check_data_cry[44]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[45]       ALU       CIN      In      -         7.401 f      -         
u_test1.check_data_cry_0[45]       ALU       COUT     Out     0.057     7.458 f      -         
check_data_cry[45]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[46]       ALU       CIN      In      -         7.458 f      -         
u_test1.check_data_cry_0[46]       ALU       COUT     Out     0.057     7.515 f      -         
check_data_cry[46]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[47]       ALU       CIN      In      -         7.515 f      -         
u_test1.check_data_cry_0[47]       ALU       COUT     Out     0.057     7.572 f      -         
check_data_cry[47]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[48]       ALU       CIN      In      -         7.572 f      -         
u_test1.check_data_cry_0[48]       ALU       COUT     Out     0.057     7.629 f      -         
check_data_cry[48]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[49]       ALU       CIN      In      -         7.629 f      -         
u_test1.check_data_cry_0[49]       ALU       COUT     Out     0.057     7.686 f      -         
check_data_cry[49]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[50]       ALU       CIN      In      -         7.686 f      -         
u_test1.check_data_cry_0[50]       ALU       COUT     Out     0.057     7.743 f      -         
check_data_cry[50]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[51]       ALU       CIN      In      -         7.743 f      -         
u_test1.check_data_cry_0[51]       ALU       COUT     Out     0.057     7.800 f      -         
check_data_cry[51]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[52]       ALU       CIN      In      -         7.800 f      -         
u_test1.check_data_cry_0[52]       ALU       COUT     Out     0.057     7.857 f      -         
check_data_cry[52]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[53]       ALU       CIN      In      -         7.857 f      -         
u_test1.check_data_cry_0[53]       ALU       COUT     Out     0.057     7.914 f      -         
check_data_cry[53]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[54]       ALU       CIN      In      -         7.914 f      -         
u_test1.check_data_cry_0[54]       ALU       COUT     Out     0.057     7.971 f      -         
check_data_cry[54]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[55]       ALU       CIN      In      -         7.971 f      -         
u_test1.check_data_cry_0[55]       ALU       COUT     Out     0.057     8.028 f      -         
check_data_cry[55]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[56]       ALU       CIN      In      -         8.028 f      -         
u_test1.check_data_cry_0[56]       ALU       COUT     Out     0.057     8.085 f      -         
check_data_cry[56]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[57]       ALU       CIN      In      -         8.085 f      -         
u_test1.check_data_cry_0[57]       ALU       COUT     Out     0.057     8.142 f      -         
check_data_cry[57]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[58]       ALU       CIN      In      -         8.142 f      -         
u_test1.check_data_cry_0[58]       ALU       COUT     Out     0.057     8.199 f      -         
check_data_cry[58]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[59]       ALU       CIN      In      -         8.199 f      -         
u_test1.check_data_cry_0[59]       ALU       COUT     Out     0.057     8.256 f      -         
check_data_cry[59]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[60]       ALU       CIN      In      -         8.256 f      -         
u_test1.check_data_cry_0[60]       ALU       COUT     Out     0.057     8.313 f      -         
check_data_cry[60]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[61]       ALU       CIN      In      -         8.313 f      -         
u_test1.check_data_cry_0[61]       ALU       COUT     Out     0.057     8.370 f      -         
check_data_cry[61]                 Net       -        -       0.000     -            1         
u_test1.check_data_cry_0[62]       ALU       CIN      In      -         8.370 f      -         
u_test1.check_data_cry_0[62]       ALU       COUT     Out     0.057     8.427 f      -         
check_data_cry[62]                 Net       -        -       0.000     -            1         
u_test1.check_data_s_0[63]         ALU       CIN      In      -         8.427 f      -         
u_test1.check_data_s_0[63]         ALU       SUM      Out     0.563     8.990 f      -         
check_data_s[63]                   Net       -        -       1.021     -            1         
u_test1.check_data[63]             DFFCE     D        In      -         10.011 f     -         
===============================================================================================
Total path delay (propagation time + setup) of 10.144 is 6.654(65.6%) logic and 3.490(34.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      10.011
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.522

    Number of logic level(s):                65
    Starting point:                          u_test0.curr_state[0] / Q
    Ending point:                            u_test0.check_data[63] / D
    The start point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                               Pin      Pin               Arrival      No. of    
Name                               Type      Name     Dir     Delay     Time         Fan Out(s)
-----------------------------------------------------------------------------------------------
u_test0.curr_state[0]              DFFP      Q        Out     0.367     0.367 r      -         
curr_state[0]                      Net       -        -       1.448     -            90        
u_test0.check_data_qxu_lofx[0]     LUT3      I1       In      -         1.815 r      -         
u_test0.check_data_qxu_lofx[0]     LUT3      F        Out     1.099     2.914 f      -         
check_data_qxu_lofx[0]             Net       -        -       1.021     -            1         
u_test0.check_data_cry_0[0]        ALU       I0       In      -         3.935 f      -         
u_test0.check_data_cry_0[0]        ALU       COUT     Out     0.958     4.893 f      -         
check_data_cry[0]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[1]        ALU       CIN      In      -         4.893 f      -         
u_test0.check_data_cry_0[1]        ALU       COUT     Out     0.057     4.950 f      -         
check_data_cry[1]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[2]        ALU       CIN      In      -         4.950 f      -         
u_test0.check_data_cry_0[2]        ALU       COUT     Out     0.057     5.007 f      -         
check_data_cry[2]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[3]        ALU       CIN      In      -         5.007 f      -         
u_test0.check_data_cry_0[3]        ALU       COUT     Out     0.057     5.064 f      -         
check_data_cry[3]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[4]        ALU       CIN      In      -         5.064 f      -         
u_test0.check_data_cry_0[4]        ALU       COUT     Out     0.057     5.121 f      -         
check_data_cry[4]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[5]        ALU       CIN      In      -         5.121 f      -         
u_test0.check_data_cry_0[5]        ALU       COUT     Out     0.057     5.178 f      -         
check_data_cry[5]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[6]        ALU       CIN      In      -         5.178 f      -         
u_test0.check_data_cry_0[6]        ALU       COUT     Out     0.057     5.235 f      -         
check_data_cry[6]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[7]        ALU       CIN      In      -         5.235 f      -         
u_test0.check_data_cry_0[7]        ALU       COUT     Out     0.057     5.292 f      -         
check_data_cry[7]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[8]        ALU       CIN      In      -         5.292 f      -         
u_test0.check_data_cry_0[8]        ALU       COUT     Out     0.057     5.349 f      -         
check_data_cry[8]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[9]        ALU       CIN      In      -         5.349 f      -         
u_test0.check_data_cry_0[9]        ALU       COUT     Out     0.057     5.406 f      -         
check_data_cry[9]                  Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[10]       ALU       CIN      In      -         5.406 f      -         
u_test0.check_data_cry_0[10]       ALU       COUT     Out     0.057     5.463 f      -         
check_data_cry[10]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[11]       ALU       CIN      In      -         5.463 f      -         
u_test0.check_data_cry_0[11]       ALU       COUT     Out     0.057     5.520 f      -         
check_data_cry[11]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[12]       ALU       CIN      In      -         5.520 f      -         
u_test0.check_data_cry_0[12]       ALU       COUT     Out     0.057     5.577 f      -         
check_data_cry[12]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[13]       ALU       CIN      In      -         5.577 f      -         
u_test0.check_data_cry_0[13]       ALU       COUT     Out     0.057     5.634 f      -         
check_data_cry[13]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[14]       ALU       CIN      In      -         5.634 f      -         
u_test0.check_data_cry_0[14]       ALU       COUT     Out     0.057     5.691 f      -         
check_data_cry[14]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[15]       ALU       CIN      In      -         5.691 f      -         
u_test0.check_data_cry_0[15]       ALU       COUT     Out     0.057     5.748 f      -         
check_data_cry[15]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[16]       ALU       CIN      In      -         5.748 f      -         
u_test0.check_data_cry_0[16]       ALU       COUT     Out     0.057     5.805 f      -         
check_data_cry[16]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[17]       ALU       CIN      In      -         5.805 f      -         
u_test0.check_data_cry_0[17]       ALU       COUT     Out     0.057     5.862 f      -         
check_data_cry[17]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[18]       ALU       CIN      In      -         5.862 f      -         
u_test0.check_data_cry_0[18]       ALU       COUT     Out     0.057     5.919 f      -         
check_data_cry[18]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[19]       ALU       CIN      In      -         5.919 f      -         
u_test0.check_data_cry_0[19]       ALU       COUT     Out     0.057     5.976 f      -         
check_data_cry[19]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[20]       ALU       CIN      In      -         5.976 f      -         
u_test0.check_data_cry_0[20]       ALU       COUT     Out     0.057     6.033 f      -         
check_data_cry[20]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[21]       ALU       CIN      In      -         6.033 f      -         
u_test0.check_data_cry_0[21]       ALU       COUT     Out     0.057     6.090 f      -         
check_data_cry[21]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[22]       ALU       CIN      In      -         6.090 f      -         
u_test0.check_data_cry_0[22]       ALU       COUT     Out     0.057     6.147 f      -         
check_data_cry[22]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[23]       ALU       CIN      In      -         6.147 f      -         
u_test0.check_data_cry_0[23]       ALU       COUT     Out     0.057     6.204 f      -         
check_data_cry[23]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[24]       ALU       CIN      In      -         6.204 f      -         
u_test0.check_data_cry_0[24]       ALU       COUT     Out     0.057     6.261 f      -         
check_data_cry[24]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[25]       ALU       CIN      In      -         6.261 f      -         
u_test0.check_data_cry_0[25]       ALU       COUT     Out     0.057     6.318 f      -         
check_data_cry[25]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[26]       ALU       CIN      In      -         6.318 f      -         
u_test0.check_data_cry_0[26]       ALU       COUT     Out     0.057     6.375 f      -         
check_data_cry[26]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[27]       ALU       CIN      In      -         6.375 f      -         
u_test0.check_data_cry_0[27]       ALU       COUT     Out     0.057     6.432 f      -         
check_data_cry[27]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[28]       ALU       CIN      In      -         6.432 f      -         
u_test0.check_data_cry_0[28]       ALU       COUT     Out     0.057     6.489 f      -         
check_data_cry[28]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[29]       ALU       CIN      In      -         6.489 f      -         
u_test0.check_data_cry_0[29]       ALU       COUT     Out     0.057     6.546 f      -         
check_data_cry[29]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[30]       ALU       CIN      In      -         6.546 f      -         
u_test0.check_data_cry_0[30]       ALU       COUT     Out     0.057     6.603 f      -         
check_data_cry[30]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[31]       ALU       CIN      In      -         6.603 f      -         
u_test0.check_data_cry_0[31]       ALU       COUT     Out     0.057     6.660 f      -         
check_data_cry[31]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[32]       ALU       CIN      In      -         6.660 f      -         
u_test0.check_data_cry_0[32]       ALU       COUT     Out     0.057     6.717 f      -         
check_data_cry[32]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[33]       ALU       CIN      In      -         6.717 f      -         
u_test0.check_data_cry_0[33]       ALU       COUT     Out     0.057     6.774 f      -         
check_data_cry[33]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[34]       ALU       CIN      In      -         6.774 f      -         
u_test0.check_data_cry_0[34]       ALU       COUT     Out     0.057     6.831 f      -         
check_data_cry[34]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[35]       ALU       CIN      In      -         6.831 f      -         
u_test0.check_data_cry_0[35]       ALU       COUT     Out     0.057     6.888 f      -         
check_data_cry[35]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[36]       ALU       CIN      In      -         6.888 f      -         
u_test0.check_data_cry_0[36]       ALU       COUT     Out     0.057     6.945 f      -         
check_data_cry[36]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[37]       ALU       CIN      In      -         6.945 f      -         
u_test0.check_data_cry_0[37]       ALU       COUT     Out     0.057     7.002 f      -         
check_data_cry[37]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[38]       ALU       CIN      In      -         7.002 f      -         
u_test0.check_data_cry_0[38]       ALU       COUT     Out     0.057     7.059 f      -         
check_data_cry[38]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[39]       ALU       CIN      In      -         7.059 f      -         
u_test0.check_data_cry_0[39]       ALU       COUT     Out     0.057     7.116 f      -         
check_data_cry[39]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[40]       ALU       CIN      In      -         7.116 f      -         
u_test0.check_data_cry_0[40]       ALU       COUT     Out     0.057     7.173 f      -         
check_data_cry[40]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[41]       ALU       CIN      In      -         7.173 f      -         
u_test0.check_data_cry_0[41]       ALU       COUT     Out     0.057     7.230 f      -         
check_data_cry[41]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[42]       ALU       CIN      In      -         7.230 f      -         
u_test0.check_data_cry_0[42]       ALU       COUT     Out     0.057     7.287 f      -         
check_data_cry[42]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[43]       ALU       CIN      In      -         7.287 f      -         
u_test0.check_data_cry_0[43]       ALU       COUT     Out     0.057     7.344 f      -         
check_data_cry[43]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[44]       ALU       CIN      In      -         7.344 f      -         
u_test0.check_data_cry_0[44]       ALU       COUT     Out     0.057     7.401 f      -         
check_data_cry[44]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[45]       ALU       CIN      In      -         7.401 f      -         
u_test0.check_data_cry_0[45]       ALU       COUT     Out     0.057     7.458 f      -         
check_data_cry[45]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[46]       ALU       CIN      In      -         7.458 f      -         
u_test0.check_data_cry_0[46]       ALU       COUT     Out     0.057     7.515 f      -         
check_data_cry[46]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[47]       ALU       CIN      In      -         7.515 f      -         
u_test0.check_data_cry_0[47]       ALU       COUT     Out     0.057     7.572 f      -         
check_data_cry[47]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[48]       ALU       CIN      In      -         7.572 f      -         
u_test0.check_data_cry_0[48]       ALU       COUT     Out     0.057     7.629 f      -         
check_data_cry[48]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[49]       ALU       CIN      In      -         7.629 f      -         
u_test0.check_data_cry_0[49]       ALU       COUT     Out     0.057     7.686 f      -         
check_data_cry[49]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[50]       ALU       CIN      In      -         7.686 f      -         
u_test0.check_data_cry_0[50]       ALU       COUT     Out     0.057     7.743 f      -         
check_data_cry[50]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[51]       ALU       CIN      In      -         7.743 f      -         
u_test0.check_data_cry_0[51]       ALU       COUT     Out     0.057     7.800 f      -         
check_data_cry[51]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[52]       ALU       CIN      In      -         7.800 f      -         
u_test0.check_data_cry_0[52]       ALU       COUT     Out     0.057     7.857 f      -         
check_data_cry[52]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[53]       ALU       CIN      In      -         7.857 f      -         
u_test0.check_data_cry_0[53]       ALU       COUT     Out     0.057     7.914 f      -         
check_data_cry[53]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[54]       ALU       CIN      In      -         7.914 f      -         
u_test0.check_data_cry_0[54]       ALU       COUT     Out     0.057     7.971 f      -         
check_data_cry[54]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[55]       ALU       CIN      In      -         7.971 f      -         
u_test0.check_data_cry_0[55]       ALU       COUT     Out     0.057     8.028 f      -         
check_data_cry[55]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[56]       ALU       CIN      In      -         8.028 f      -         
u_test0.check_data_cry_0[56]       ALU       COUT     Out     0.057     8.085 f      -         
check_data_cry[56]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[57]       ALU       CIN      In      -         8.085 f      -         
u_test0.check_data_cry_0[57]       ALU       COUT     Out     0.057     8.142 f      -         
check_data_cry[57]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[58]       ALU       CIN      In      -         8.142 f      -         
u_test0.check_data_cry_0[58]       ALU       COUT     Out     0.057     8.199 f      -         
check_data_cry[58]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[59]       ALU       CIN      In      -         8.199 f      -         
u_test0.check_data_cry_0[59]       ALU       COUT     Out     0.057     8.256 f      -         
check_data_cry[59]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[60]       ALU       CIN      In      -         8.256 f      -         
u_test0.check_data_cry_0[60]       ALU       COUT     Out     0.057     8.313 f      -         
check_data_cry[60]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[61]       ALU       CIN      In      -         8.313 f      -         
u_test0.check_data_cry_0[61]       ALU       COUT     Out     0.057     8.370 f      -         
check_data_cry[61]                 Net       -        -       0.000     -            1         
u_test0.check_data_cry_0[62]       ALU       CIN      In      -         8.370 f      -         
u_test0.check_data_cry_0[62]       ALU       COUT     Out     0.057     8.427 f      -         
check_data_cry[62]                 Net       -        -       0.000     -            1         
u_test0.check_data_s_0[63]         ALU       CIN      In      -         8.427 f      -         
u_test0.check_data_s_0[63]         ALU       SUM      Out     0.563     8.990 f      -         
check_data_s[63]                   Net       -        -       1.021     -            1         
u_test0.check_data[63]             DFFCE     D        In      -         10.011 f     -         
===============================================================================================
Total path delay (propagation time + setup) of 10.144 is 6.654(65.6%) logic and 3.490(34.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      9.954
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.465

    Number of logic level(s):                64
    Starting point:                          u_test1.curr_state[0] / Q
    Ending point:                            u_test1.check_data[63] / D
    The start point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_test1.curr_state[0]              DFFP      Q        Out     0.367     0.367 r     -         
curr_state[0]                      Net       -        -       1.448     -           90        
u_test1.check_data_qxu_lofx[1]     LUT3      I1       In      -         1.815 r     -         
u_test1.check_data_qxu_lofx[1]     LUT3      F        Out     1.099     2.914 f     -         
check_data_qxu_lofx_0[1]           Net       -        -       1.021     -           1         
u_test1.check_data_cry_0[1]        ALU       I0       In      -         3.935 f     -         
u_test1.check_data_cry_0[1]        ALU       COUT     Out     0.958     4.893 f     -         
check_data_cry[1]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[2]        ALU       CIN      In      -         4.893 f     -         
u_test1.check_data_cry_0[2]        ALU       COUT     Out     0.057     4.950 f     -         
check_data_cry[2]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[3]        ALU       CIN      In      -         4.950 f     -         
u_test1.check_data_cry_0[3]        ALU       COUT     Out     0.057     5.007 f     -         
check_data_cry[3]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[4]        ALU       CIN      In      -         5.007 f     -         
u_test1.check_data_cry_0[4]        ALU       COUT     Out     0.057     5.064 f     -         
check_data_cry[4]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[5]        ALU       CIN      In      -         5.064 f     -         
u_test1.check_data_cry_0[5]        ALU       COUT     Out     0.057     5.121 f     -         
check_data_cry[5]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[6]        ALU       CIN      In      -         5.121 f     -         
u_test1.check_data_cry_0[6]        ALU       COUT     Out     0.057     5.178 f     -         
check_data_cry[6]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[7]        ALU       CIN      In      -         5.178 f     -         
u_test1.check_data_cry_0[7]        ALU       COUT     Out     0.057     5.235 f     -         
check_data_cry[7]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[8]        ALU       CIN      In      -         5.235 f     -         
u_test1.check_data_cry_0[8]        ALU       COUT     Out     0.057     5.292 f     -         
check_data_cry[8]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[9]        ALU       CIN      In      -         5.292 f     -         
u_test1.check_data_cry_0[9]        ALU       COUT     Out     0.057     5.349 f     -         
check_data_cry[9]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[10]       ALU       CIN      In      -         5.349 f     -         
u_test1.check_data_cry_0[10]       ALU       COUT     Out     0.057     5.406 f     -         
check_data_cry[10]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[11]       ALU       CIN      In      -         5.406 f     -         
u_test1.check_data_cry_0[11]       ALU       COUT     Out     0.057     5.463 f     -         
check_data_cry[11]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[12]       ALU       CIN      In      -         5.463 f     -         
u_test1.check_data_cry_0[12]       ALU       COUT     Out     0.057     5.520 f     -         
check_data_cry[12]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[13]       ALU       CIN      In      -         5.520 f     -         
u_test1.check_data_cry_0[13]       ALU       COUT     Out     0.057     5.577 f     -         
check_data_cry[13]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[14]       ALU       CIN      In      -         5.577 f     -         
u_test1.check_data_cry_0[14]       ALU       COUT     Out     0.057     5.634 f     -         
check_data_cry[14]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[15]       ALU       CIN      In      -         5.634 f     -         
u_test1.check_data_cry_0[15]       ALU       COUT     Out     0.057     5.691 f     -         
check_data_cry[15]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[16]       ALU       CIN      In      -         5.691 f     -         
u_test1.check_data_cry_0[16]       ALU       COUT     Out     0.057     5.748 f     -         
check_data_cry[16]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[17]       ALU       CIN      In      -         5.748 f     -         
u_test1.check_data_cry_0[17]       ALU       COUT     Out     0.057     5.805 f     -         
check_data_cry[17]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[18]       ALU       CIN      In      -         5.805 f     -         
u_test1.check_data_cry_0[18]       ALU       COUT     Out     0.057     5.862 f     -         
check_data_cry[18]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[19]       ALU       CIN      In      -         5.862 f     -         
u_test1.check_data_cry_0[19]       ALU       COUT     Out     0.057     5.919 f     -         
check_data_cry[19]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[20]       ALU       CIN      In      -         5.919 f     -         
u_test1.check_data_cry_0[20]       ALU       COUT     Out     0.057     5.976 f     -         
check_data_cry[20]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[21]       ALU       CIN      In      -         5.976 f     -         
u_test1.check_data_cry_0[21]       ALU       COUT     Out     0.057     6.033 f     -         
check_data_cry[21]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[22]       ALU       CIN      In      -         6.033 f     -         
u_test1.check_data_cry_0[22]       ALU       COUT     Out     0.057     6.090 f     -         
check_data_cry[22]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[23]       ALU       CIN      In      -         6.090 f     -         
u_test1.check_data_cry_0[23]       ALU       COUT     Out     0.057     6.147 f     -         
check_data_cry[23]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[24]       ALU       CIN      In      -         6.147 f     -         
u_test1.check_data_cry_0[24]       ALU       COUT     Out     0.057     6.204 f     -         
check_data_cry[24]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[25]       ALU       CIN      In      -         6.204 f     -         
u_test1.check_data_cry_0[25]       ALU       COUT     Out     0.057     6.261 f     -         
check_data_cry[25]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[26]       ALU       CIN      In      -         6.261 f     -         
u_test1.check_data_cry_0[26]       ALU       COUT     Out     0.057     6.318 f     -         
check_data_cry[26]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[27]       ALU       CIN      In      -         6.318 f     -         
u_test1.check_data_cry_0[27]       ALU       COUT     Out     0.057     6.375 f     -         
check_data_cry[27]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[28]       ALU       CIN      In      -         6.375 f     -         
u_test1.check_data_cry_0[28]       ALU       COUT     Out     0.057     6.432 f     -         
check_data_cry[28]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[29]       ALU       CIN      In      -         6.432 f     -         
u_test1.check_data_cry_0[29]       ALU       COUT     Out     0.057     6.489 f     -         
check_data_cry[29]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[30]       ALU       CIN      In      -         6.489 f     -         
u_test1.check_data_cry_0[30]       ALU       COUT     Out     0.057     6.546 f     -         
check_data_cry[30]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[31]       ALU       CIN      In      -         6.546 f     -         
u_test1.check_data_cry_0[31]       ALU       COUT     Out     0.057     6.603 f     -         
check_data_cry[31]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[32]       ALU       CIN      In      -         6.603 f     -         
u_test1.check_data_cry_0[32]       ALU       COUT     Out     0.057     6.660 f     -         
check_data_cry[32]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[33]       ALU       CIN      In      -         6.660 f     -         
u_test1.check_data_cry_0[33]       ALU       COUT     Out     0.057     6.717 f     -         
check_data_cry[33]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[34]       ALU       CIN      In      -         6.717 f     -         
u_test1.check_data_cry_0[34]       ALU       COUT     Out     0.057     6.774 f     -         
check_data_cry[34]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[35]       ALU       CIN      In      -         6.774 f     -         
u_test1.check_data_cry_0[35]       ALU       COUT     Out     0.057     6.831 f     -         
check_data_cry[35]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[36]       ALU       CIN      In      -         6.831 f     -         
u_test1.check_data_cry_0[36]       ALU       COUT     Out     0.057     6.888 f     -         
check_data_cry[36]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[37]       ALU       CIN      In      -         6.888 f     -         
u_test1.check_data_cry_0[37]       ALU       COUT     Out     0.057     6.945 f     -         
check_data_cry[37]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[38]       ALU       CIN      In      -         6.945 f     -         
u_test1.check_data_cry_0[38]       ALU       COUT     Out     0.057     7.002 f     -         
check_data_cry[38]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[39]       ALU       CIN      In      -         7.002 f     -         
u_test1.check_data_cry_0[39]       ALU       COUT     Out     0.057     7.059 f     -         
check_data_cry[39]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[40]       ALU       CIN      In      -         7.059 f     -         
u_test1.check_data_cry_0[40]       ALU       COUT     Out     0.057     7.116 f     -         
check_data_cry[40]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[41]       ALU       CIN      In      -         7.116 f     -         
u_test1.check_data_cry_0[41]       ALU       COUT     Out     0.057     7.173 f     -         
check_data_cry[41]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[42]       ALU       CIN      In      -         7.173 f     -         
u_test1.check_data_cry_0[42]       ALU       COUT     Out     0.057     7.230 f     -         
check_data_cry[42]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[43]       ALU       CIN      In      -         7.230 f     -         
u_test1.check_data_cry_0[43]       ALU       COUT     Out     0.057     7.287 f     -         
check_data_cry[43]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[44]       ALU       CIN      In      -         7.287 f     -         
u_test1.check_data_cry_0[44]       ALU       COUT     Out     0.057     7.344 f     -         
check_data_cry[44]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[45]       ALU       CIN      In      -         7.344 f     -         
u_test1.check_data_cry_0[45]       ALU       COUT     Out     0.057     7.401 f     -         
check_data_cry[45]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[46]       ALU       CIN      In      -         7.401 f     -         
u_test1.check_data_cry_0[46]       ALU       COUT     Out     0.057     7.458 f     -         
check_data_cry[46]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[47]       ALU       CIN      In      -         7.458 f     -         
u_test1.check_data_cry_0[47]       ALU       COUT     Out     0.057     7.515 f     -         
check_data_cry[47]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[48]       ALU       CIN      In      -         7.515 f     -         
u_test1.check_data_cry_0[48]       ALU       COUT     Out     0.057     7.572 f     -         
check_data_cry[48]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[49]       ALU       CIN      In      -         7.572 f     -         
u_test1.check_data_cry_0[49]       ALU       COUT     Out     0.057     7.629 f     -         
check_data_cry[49]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[50]       ALU       CIN      In      -         7.629 f     -         
u_test1.check_data_cry_0[50]       ALU       COUT     Out     0.057     7.686 f     -         
check_data_cry[50]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[51]       ALU       CIN      In      -         7.686 f     -         
u_test1.check_data_cry_0[51]       ALU       COUT     Out     0.057     7.743 f     -         
check_data_cry[51]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[52]       ALU       CIN      In      -         7.743 f     -         
u_test1.check_data_cry_0[52]       ALU       COUT     Out     0.057     7.800 f     -         
check_data_cry[52]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[53]       ALU       CIN      In      -         7.800 f     -         
u_test1.check_data_cry_0[53]       ALU       COUT     Out     0.057     7.857 f     -         
check_data_cry[53]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[54]       ALU       CIN      In      -         7.857 f     -         
u_test1.check_data_cry_0[54]       ALU       COUT     Out     0.057     7.914 f     -         
check_data_cry[54]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[55]       ALU       CIN      In      -         7.914 f     -         
u_test1.check_data_cry_0[55]       ALU       COUT     Out     0.057     7.971 f     -         
check_data_cry[55]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[56]       ALU       CIN      In      -         7.971 f     -         
u_test1.check_data_cry_0[56]       ALU       COUT     Out     0.057     8.028 f     -         
check_data_cry[56]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[57]       ALU       CIN      In      -         8.028 f     -         
u_test1.check_data_cry_0[57]       ALU       COUT     Out     0.057     8.085 f     -         
check_data_cry[57]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[58]       ALU       CIN      In      -         8.085 f     -         
u_test1.check_data_cry_0[58]       ALU       COUT     Out     0.057     8.142 f     -         
check_data_cry[58]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[59]       ALU       CIN      In      -         8.142 f     -         
u_test1.check_data_cry_0[59]       ALU       COUT     Out     0.057     8.199 f     -         
check_data_cry[59]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[60]       ALU       CIN      In      -         8.199 f     -         
u_test1.check_data_cry_0[60]       ALU       COUT     Out     0.057     8.256 f     -         
check_data_cry[60]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[61]       ALU       CIN      In      -         8.256 f     -         
u_test1.check_data_cry_0[61]       ALU       COUT     Out     0.057     8.313 f     -         
check_data_cry[61]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[62]       ALU       CIN      In      -         8.313 f     -         
u_test1.check_data_cry_0[62]       ALU       COUT     Out     0.057     8.370 f     -         
check_data_cry[62]                 Net       -        -       0.000     -           1         
u_test1.check_data_s_0[63]         ALU       CIN      In      -         8.370 f     -         
u_test1.check_data_s_0[63]         ALU       SUM      Out     0.563     8.933 f     -         
check_data_s[63]                   Net       -        -       1.021     -           1         
u_test1.check_data[63]             DFFCE     D        In      -         9.954 f     -         
==============================================================================================
Total path delay (propagation time + setup) of 10.087 is 6.597(65.4%) logic and 3.490(34.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      9.954
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.465

    Number of logic level(s):                64
    Starting point:                          u_test1.curr_state[0] / Q
    Ending point:                            u_test1.check_data[62] / D
    The start point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_test1.curr_state[0]              DFFP      Q        Out     0.367     0.367 r     -         
curr_state[0]                      Net       -        -       1.448     -           90        
u_test1.check_data_qxu_lofx[0]     LUT3      I1       In      -         1.815 r     -         
u_test1.check_data_qxu_lofx[0]     LUT3      F        Out     1.099     2.914 f     -         
check_data_qxu_lofx_0[0]           Net       -        -       1.021     -           1         
u_test1.check_data_cry_0[0]        ALU       I0       In      -         3.935 f     -         
u_test1.check_data_cry_0[0]        ALU       COUT     Out     0.958     4.893 f     -         
check_data_cry[0]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[1]        ALU       CIN      In      -         4.893 f     -         
u_test1.check_data_cry_0[1]        ALU       COUT     Out     0.057     4.950 f     -         
check_data_cry[1]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[2]        ALU       CIN      In      -         4.950 f     -         
u_test1.check_data_cry_0[2]        ALU       COUT     Out     0.057     5.007 f     -         
check_data_cry[2]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[3]        ALU       CIN      In      -         5.007 f     -         
u_test1.check_data_cry_0[3]        ALU       COUT     Out     0.057     5.064 f     -         
check_data_cry[3]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[4]        ALU       CIN      In      -         5.064 f     -         
u_test1.check_data_cry_0[4]        ALU       COUT     Out     0.057     5.121 f     -         
check_data_cry[4]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[5]        ALU       CIN      In      -         5.121 f     -         
u_test1.check_data_cry_0[5]        ALU       COUT     Out     0.057     5.178 f     -         
check_data_cry[5]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[6]        ALU       CIN      In      -         5.178 f     -         
u_test1.check_data_cry_0[6]        ALU       COUT     Out     0.057     5.235 f     -         
check_data_cry[6]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[7]        ALU       CIN      In      -         5.235 f     -         
u_test1.check_data_cry_0[7]        ALU       COUT     Out     0.057     5.292 f     -         
check_data_cry[7]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[8]        ALU       CIN      In      -         5.292 f     -         
u_test1.check_data_cry_0[8]        ALU       COUT     Out     0.057     5.349 f     -         
check_data_cry[8]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[9]        ALU       CIN      In      -         5.349 f     -         
u_test1.check_data_cry_0[9]        ALU       COUT     Out     0.057     5.406 f     -         
check_data_cry[9]                  Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[10]       ALU       CIN      In      -         5.406 f     -         
u_test1.check_data_cry_0[10]       ALU       COUT     Out     0.057     5.463 f     -         
check_data_cry[10]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[11]       ALU       CIN      In      -         5.463 f     -         
u_test1.check_data_cry_0[11]       ALU       COUT     Out     0.057     5.520 f     -         
check_data_cry[11]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[12]       ALU       CIN      In      -         5.520 f     -         
u_test1.check_data_cry_0[12]       ALU       COUT     Out     0.057     5.577 f     -         
check_data_cry[12]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[13]       ALU       CIN      In      -         5.577 f     -         
u_test1.check_data_cry_0[13]       ALU       COUT     Out     0.057     5.634 f     -         
check_data_cry[13]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[14]       ALU       CIN      In      -         5.634 f     -         
u_test1.check_data_cry_0[14]       ALU       COUT     Out     0.057     5.691 f     -         
check_data_cry[14]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[15]       ALU       CIN      In      -         5.691 f     -         
u_test1.check_data_cry_0[15]       ALU       COUT     Out     0.057     5.748 f     -         
check_data_cry[15]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[16]       ALU       CIN      In      -         5.748 f     -         
u_test1.check_data_cry_0[16]       ALU       COUT     Out     0.057     5.805 f     -         
check_data_cry[16]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[17]       ALU       CIN      In      -         5.805 f     -         
u_test1.check_data_cry_0[17]       ALU       COUT     Out     0.057     5.862 f     -         
check_data_cry[17]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[18]       ALU       CIN      In      -         5.862 f     -         
u_test1.check_data_cry_0[18]       ALU       COUT     Out     0.057     5.919 f     -         
check_data_cry[18]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[19]       ALU       CIN      In      -         5.919 f     -         
u_test1.check_data_cry_0[19]       ALU       COUT     Out     0.057     5.976 f     -         
check_data_cry[19]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[20]       ALU       CIN      In      -         5.976 f     -         
u_test1.check_data_cry_0[20]       ALU       COUT     Out     0.057     6.033 f     -         
check_data_cry[20]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[21]       ALU       CIN      In      -         6.033 f     -         
u_test1.check_data_cry_0[21]       ALU       COUT     Out     0.057     6.090 f     -         
check_data_cry[21]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[22]       ALU       CIN      In      -         6.090 f     -         
u_test1.check_data_cry_0[22]       ALU       COUT     Out     0.057     6.147 f     -         
check_data_cry[22]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[23]       ALU       CIN      In      -         6.147 f     -         
u_test1.check_data_cry_0[23]       ALU       COUT     Out     0.057     6.204 f     -         
check_data_cry[23]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[24]       ALU       CIN      In      -         6.204 f     -         
u_test1.check_data_cry_0[24]       ALU       COUT     Out     0.057     6.261 f     -         
check_data_cry[24]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[25]       ALU       CIN      In      -         6.261 f     -         
u_test1.check_data_cry_0[25]       ALU       COUT     Out     0.057     6.318 f     -         
check_data_cry[25]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[26]       ALU       CIN      In      -         6.318 f     -         
u_test1.check_data_cry_0[26]       ALU       COUT     Out     0.057     6.375 f     -         
check_data_cry[26]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[27]       ALU       CIN      In      -         6.375 f     -         
u_test1.check_data_cry_0[27]       ALU       COUT     Out     0.057     6.432 f     -         
check_data_cry[27]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[28]       ALU       CIN      In      -         6.432 f     -         
u_test1.check_data_cry_0[28]       ALU       COUT     Out     0.057     6.489 f     -         
check_data_cry[28]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[29]       ALU       CIN      In      -         6.489 f     -         
u_test1.check_data_cry_0[29]       ALU       COUT     Out     0.057     6.546 f     -         
check_data_cry[29]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[30]       ALU       CIN      In      -         6.546 f     -         
u_test1.check_data_cry_0[30]       ALU       COUT     Out     0.057     6.603 f     -         
check_data_cry[30]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[31]       ALU       CIN      In      -         6.603 f     -         
u_test1.check_data_cry_0[31]       ALU       COUT     Out     0.057     6.660 f     -         
check_data_cry[31]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[32]       ALU       CIN      In      -         6.660 f     -         
u_test1.check_data_cry_0[32]       ALU       COUT     Out     0.057     6.717 f     -         
check_data_cry[32]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[33]       ALU       CIN      In      -         6.717 f     -         
u_test1.check_data_cry_0[33]       ALU       COUT     Out     0.057     6.774 f     -         
check_data_cry[33]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[34]       ALU       CIN      In      -         6.774 f     -         
u_test1.check_data_cry_0[34]       ALU       COUT     Out     0.057     6.831 f     -         
check_data_cry[34]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[35]       ALU       CIN      In      -         6.831 f     -         
u_test1.check_data_cry_0[35]       ALU       COUT     Out     0.057     6.888 f     -         
check_data_cry[35]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[36]       ALU       CIN      In      -         6.888 f     -         
u_test1.check_data_cry_0[36]       ALU       COUT     Out     0.057     6.945 f     -         
check_data_cry[36]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[37]       ALU       CIN      In      -         6.945 f     -         
u_test1.check_data_cry_0[37]       ALU       COUT     Out     0.057     7.002 f     -         
check_data_cry[37]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[38]       ALU       CIN      In      -         7.002 f     -         
u_test1.check_data_cry_0[38]       ALU       COUT     Out     0.057     7.059 f     -         
check_data_cry[38]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[39]       ALU       CIN      In      -         7.059 f     -         
u_test1.check_data_cry_0[39]       ALU       COUT     Out     0.057     7.116 f     -         
check_data_cry[39]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[40]       ALU       CIN      In      -         7.116 f     -         
u_test1.check_data_cry_0[40]       ALU       COUT     Out     0.057     7.173 f     -         
check_data_cry[40]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[41]       ALU       CIN      In      -         7.173 f     -         
u_test1.check_data_cry_0[41]       ALU       COUT     Out     0.057     7.230 f     -         
check_data_cry[41]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[42]       ALU       CIN      In      -         7.230 f     -         
u_test1.check_data_cry_0[42]       ALU       COUT     Out     0.057     7.287 f     -         
check_data_cry[42]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[43]       ALU       CIN      In      -         7.287 f     -         
u_test1.check_data_cry_0[43]       ALU       COUT     Out     0.057     7.344 f     -         
check_data_cry[43]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[44]       ALU       CIN      In      -         7.344 f     -         
u_test1.check_data_cry_0[44]       ALU       COUT     Out     0.057     7.401 f     -         
check_data_cry[44]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[45]       ALU       CIN      In      -         7.401 f     -         
u_test1.check_data_cry_0[45]       ALU       COUT     Out     0.057     7.458 f     -         
check_data_cry[45]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[46]       ALU       CIN      In      -         7.458 f     -         
u_test1.check_data_cry_0[46]       ALU       COUT     Out     0.057     7.515 f     -         
check_data_cry[46]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[47]       ALU       CIN      In      -         7.515 f     -         
u_test1.check_data_cry_0[47]       ALU       COUT     Out     0.057     7.572 f     -         
check_data_cry[47]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[48]       ALU       CIN      In      -         7.572 f     -         
u_test1.check_data_cry_0[48]       ALU       COUT     Out     0.057     7.629 f     -         
check_data_cry[48]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[49]       ALU       CIN      In      -         7.629 f     -         
u_test1.check_data_cry_0[49]       ALU       COUT     Out     0.057     7.686 f     -         
check_data_cry[49]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[50]       ALU       CIN      In      -         7.686 f     -         
u_test1.check_data_cry_0[50]       ALU       COUT     Out     0.057     7.743 f     -         
check_data_cry[50]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[51]       ALU       CIN      In      -         7.743 f     -         
u_test1.check_data_cry_0[51]       ALU       COUT     Out     0.057     7.800 f     -         
check_data_cry[51]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[52]       ALU       CIN      In      -         7.800 f     -         
u_test1.check_data_cry_0[52]       ALU       COUT     Out     0.057     7.857 f     -         
check_data_cry[52]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[53]       ALU       CIN      In      -         7.857 f     -         
u_test1.check_data_cry_0[53]       ALU       COUT     Out     0.057     7.914 f     -         
check_data_cry[53]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[54]       ALU       CIN      In      -         7.914 f     -         
u_test1.check_data_cry_0[54]       ALU       COUT     Out     0.057     7.971 f     -         
check_data_cry[54]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[55]       ALU       CIN      In      -         7.971 f     -         
u_test1.check_data_cry_0[55]       ALU       COUT     Out     0.057     8.028 f     -         
check_data_cry[55]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[56]       ALU       CIN      In      -         8.028 f     -         
u_test1.check_data_cry_0[56]       ALU       COUT     Out     0.057     8.085 f     -         
check_data_cry[56]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[57]       ALU       CIN      In      -         8.085 f     -         
u_test1.check_data_cry_0[57]       ALU       COUT     Out     0.057     8.142 f     -         
check_data_cry[57]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[58]       ALU       CIN      In      -         8.142 f     -         
u_test1.check_data_cry_0[58]       ALU       COUT     Out     0.057     8.199 f     -         
check_data_cry[58]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[59]       ALU       CIN      In      -         8.199 f     -         
u_test1.check_data_cry_0[59]       ALU       COUT     Out     0.057     8.256 f     -         
check_data_cry[59]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[60]       ALU       CIN      In      -         8.256 f     -         
u_test1.check_data_cry_0[60]       ALU       COUT     Out     0.057     8.313 f     -         
check_data_cry[60]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[61]       ALU       CIN      In      -         8.313 f     -         
u_test1.check_data_cry_0[61]       ALU       COUT     Out     0.057     8.370 f     -         
check_data_cry[61]                 Net       -        -       0.000     -           1         
u_test1.check_data_cry_0[62]       ALU       CIN      In      -         8.370 f     -         
u_test1.check_data_cry_0[62]       ALU       SUM      Out     0.563     8.933 f     -         
check_data_s[62]                   Net       -        -       1.021     -           1         
u_test1.check_data[62]             DFFCE     D        In      -         9.954 f     -         
==============================================================================================
Total path delay (propagation time + setup) of 10.087 is 6.597(65.4%) logic and 3.490(34.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      9.954
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.465

    Number of logic level(s):                64
    Starting point:                          u_test0.curr_state[0] / Q
    Ending point:                            u_test0.check_data[63] / D
    The start point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                               Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u_test0.curr_state[0]              DFFP      Q        Out     0.367     0.367 r     -         
curr_state[0]                      Net       -        -       1.448     -           90        
u_test0.check_data_qxu_lofx[1]     LUT3      I1       In      -         1.815 r     -         
u_test0.check_data_qxu_lofx[1]     LUT3      F        Out     1.099     2.914 f     -         
check_data_qxu_lofx[1]             Net       -        -       1.021     -           1         
u_test0.check_data_cry_0[1]        ALU       I0       In      -         3.935 f     -         
u_test0.check_data_cry_0[1]        ALU       COUT     Out     0.958     4.893 f     -         
check_data_cry[1]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[2]        ALU       CIN      In      -         4.893 f     -         
u_test0.check_data_cry_0[2]        ALU       COUT     Out     0.057     4.950 f     -         
check_data_cry[2]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[3]        ALU       CIN      In      -         4.950 f     -         
u_test0.check_data_cry_0[3]        ALU       COUT     Out     0.057     5.007 f     -         
check_data_cry[3]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[4]        ALU       CIN      In      -         5.007 f     -         
u_test0.check_data_cry_0[4]        ALU       COUT     Out     0.057     5.064 f     -         
check_data_cry[4]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[5]        ALU       CIN      In      -         5.064 f     -         
u_test0.check_data_cry_0[5]        ALU       COUT     Out     0.057     5.121 f     -         
check_data_cry[5]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[6]        ALU       CIN      In      -         5.121 f     -         
u_test0.check_data_cry_0[6]        ALU       COUT     Out     0.057     5.178 f     -         
check_data_cry[6]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[7]        ALU       CIN      In      -         5.178 f     -         
u_test0.check_data_cry_0[7]        ALU       COUT     Out     0.057     5.235 f     -         
check_data_cry[7]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[8]        ALU       CIN      In      -         5.235 f     -         
u_test0.check_data_cry_0[8]        ALU       COUT     Out     0.057     5.292 f     -         
check_data_cry[8]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[9]        ALU       CIN      In      -         5.292 f     -         
u_test0.check_data_cry_0[9]        ALU       COUT     Out     0.057     5.349 f     -         
check_data_cry[9]                  Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[10]       ALU       CIN      In      -         5.349 f     -         
u_test0.check_data_cry_0[10]       ALU       COUT     Out     0.057     5.406 f     -         
check_data_cry[10]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[11]       ALU       CIN      In      -         5.406 f     -         
u_test0.check_data_cry_0[11]       ALU       COUT     Out     0.057     5.463 f     -         
check_data_cry[11]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[12]       ALU       CIN      In      -         5.463 f     -         
u_test0.check_data_cry_0[12]       ALU       COUT     Out     0.057     5.520 f     -         
check_data_cry[12]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[13]       ALU       CIN      In      -         5.520 f     -         
u_test0.check_data_cry_0[13]       ALU       COUT     Out     0.057     5.577 f     -         
check_data_cry[13]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[14]       ALU       CIN      In      -         5.577 f     -         
u_test0.check_data_cry_0[14]       ALU       COUT     Out     0.057     5.634 f     -         
check_data_cry[14]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[15]       ALU       CIN      In      -         5.634 f     -         
u_test0.check_data_cry_0[15]       ALU       COUT     Out     0.057     5.691 f     -         
check_data_cry[15]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[16]       ALU       CIN      In      -         5.691 f     -         
u_test0.check_data_cry_0[16]       ALU       COUT     Out     0.057     5.748 f     -         
check_data_cry[16]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[17]       ALU       CIN      In      -         5.748 f     -         
u_test0.check_data_cry_0[17]       ALU       COUT     Out     0.057     5.805 f     -         
check_data_cry[17]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[18]       ALU       CIN      In      -         5.805 f     -         
u_test0.check_data_cry_0[18]       ALU       COUT     Out     0.057     5.862 f     -         
check_data_cry[18]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[19]       ALU       CIN      In      -         5.862 f     -         
u_test0.check_data_cry_0[19]       ALU       COUT     Out     0.057     5.919 f     -         
check_data_cry[19]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[20]       ALU       CIN      In      -         5.919 f     -         
u_test0.check_data_cry_0[20]       ALU       COUT     Out     0.057     5.976 f     -         
check_data_cry[20]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[21]       ALU       CIN      In      -         5.976 f     -         
u_test0.check_data_cry_0[21]       ALU       COUT     Out     0.057     6.033 f     -         
check_data_cry[21]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[22]       ALU       CIN      In      -         6.033 f     -         
u_test0.check_data_cry_0[22]       ALU       COUT     Out     0.057     6.090 f     -         
check_data_cry[22]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[23]       ALU       CIN      In      -         6.090 f     -         
u_test0.check_data_cry_0[23]       ALU       COUT     Out     0.057     6.147 f     -         
check_data_cry[23]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[24]       ALU       CIN      In      -         6.147 f     -         
u_test0.check_data_cry_0[24]       ALU       COUT     Out     0.057     6.204 f     -         
check_data_cry[24]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[25]       ALU       CIN      In      -         6.204 f     -         
u_test0.check_data_cry_0[25]       ALU       COUT     Out     0.057     6.261 f     -         
check_data_cry[25]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[26]       ALU       CIN      In      -         6.261 f     -         
u_test0.check_data_cry_0[26]       ALU       COUT     Out     0.057     6.318 f     -         
check_data_cry[26]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[27]       ALU       CIN      In      -         6.318 f     -         
u_test0.check_data_cry_0[27]       ALU       COUT     Out     0.057     6.375 f     -         
check_data_cry[27]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[28]       ALU       CIN      In      -         6.375 f     -         
u_test0.check_data_cry_0[28]       ALU       COUT     Out     0.057     6.432 f     -         
check_data_cry[28]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[29]       ALU       CIN      In      -         6.432 f     -         
u_test0.check_data_cry_0[29]       ALU       COUT     Out     0.057     6.489 f     -         
check_data_cry[29]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[30]       ALU       CIN      In      -         6.489 f     -         
u_test0.check_data_cry_0[30]       ALU       COUT     Out     0.057     6.546 f     -         
check_data_cry[30]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[31]       ALU       CIN      In      -         6.546 f     -         
u_test0.check_data_cry_0[31]       ALU       COUT     Out     0.057     6.603 f     -         
check_data_cry[31]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[32]       ALU       CIN      In      -         6.603 f     -         
u_test0.check_data_cry_0[32]       ALU       COUT     Out     0.057     6.660 f     -         
check_data_cry[32]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[33]       ALU       CIN      In      -         6.660 f     -         
u_test0.check_data_cry_0[33]       ALU       COUT     Out     0.057     6.717 f     -         
check_data_cry[33]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[34]       ALU       CIN      In      -         6.717 f     -         
u_test0.check_data_cry_0[34]       ALU       COUT     Out     0.057     6.774 f     -         
check_data_cry[34]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[35]       ALU       CIN      In      -         6.774 f     -         
u_test0.check_data_cry_0[35]       ALU       COUT     Out     0.057     6.831 f     -         
check_data_cry[35]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[36]       ALU       CIN      In      -         6.831 f     -         
u_test0.check_data_cry_0[36]       ALU       COUT     Out     0.057     6.888 f     -         
check_data_cry[36]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[37]       ALU       CIN      In      -         6.888 f     -         
u_test0.check_data_cry_0[37]       ALU       COUT     Out     0.057     6.945 f     -         
check_data_cry[37]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[38]       ALU       CIN      In      -         6.945 f     -         
u_test0.check_data_cry_0[38]       ALU       COUT     Out     0.057     7.002 f     -         
check_data_cry[38]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[39]       ALU       CIN      In      -         7.002 f     -         
u_test0.check_data_cry_0[39]       ALU       COUT     Out     0.057     7.059 f     -         
check_data_cry[39]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[40]       ALU       CIN      In      -         7.059 f     -         
u_test0.check_data_cry_0[40]       ALU       COUT     Out     0.057     7.116 f     -         
check_data_cry[40]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[41]       ALU       CIN      In      -         7.116 f     -         
u_test0.check_data_cry_0[41]       ALU       COUT     Out     0.057     7.173 f     -         
check_data_cry[41]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[42]       ALU       CIN      In      -         7.173 f     -         
u_test0.check_data_cry_0[42]       ALU       COUT     Out     0.057     7.230 f     -         
check_data_cry[42]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[43]       ALU       CIN      In      -         7.230 f     -         
u_test0.check_data_cry_0[43]       ALU       COUT     Out     0.057     7.287 f     -         
check_data_cry[43]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[44]       ALU       CIN      In      -         7.287 f     -         
u_test0.check_data_cry_0[44]       ALU       COUT     Out     0.057     7.344 f     -         
check_data_cry[44]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[45]       ALU       CIN      In      -         7.344 f     -         
u_test0.check_data_cry_0[45]       ALU       COUT     Out     0.057     7.401 f     -         
check_data_cry[45]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[46]       ALU       CIN      In      -         7.401 f     -         
u_test0.check_data_cry_0[46]       ALU       COUT     Out     0.057     7.458 f     -         
check_data_cry[46]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[47]       ALU       CIN      In      -         7.458 f     -         
u_test0.check_data_cry_0[47]       ALU       COUT     Out     0.057     7.515 f     -         
check_data_cry[47]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[48]       ALU       CIN      In      -         7.515 f     -         
u_test0.check_data_cry_0[48]       ALU       COUT     Out     0.057     7.572 f     -         
check_data_cry[48]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[49]       ALU       CIN      In      -         7.572 f     -         
u_test0.check_data_cry_0[49]       ALU       COUT     Out     0.057     7.629 f     -         
check_data_cry[49]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[50]       ALU       CIN      In      -         7.629 f     -         
u_test0.check_data_cry_0[50]       ALU       COUT     Out     0.057     7.686 f     -         
check_data_cry[50]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[51]       ALU       CIN      In      -         7.686 f     -         
u_test0.check_data_cry_0[51]       ALU       COUT     Out     0.057     7.743 f     -         
check_data_cry[51]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[52]       ALU       CIN      In      -         7.743 f     -         
u_test0.check_data_cry_0[52]       ALU       COUT     Out     0.057     7.800 f     -         
check_data_cry[52]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[53]       ALU       CIN      In      -         7.800 f     -         
u_test0.check_data_cry_0[53]       ALU       COUT     Out     0.057     7.857 f     -         
check_data_cry[53]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[54]       ALU       CIN      In      -         7.857 f     -         
u_test0.check_data_cry_0[54]       ALU       COUT     Out     0.057     7.914 f     -         
check_data_cry[54]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[55]       ALU       CIN      In      -         7.914 f     -         
u_test0.check_data_cry_0[55]       ALU       COUT     Out     0.057     7.971 f     -         
check_data_cry[55]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[56]       ALU       CIN      In      -         7.971 f     -         
u_test0.check_data_cry_0[56]       ALU       COUT     Out     0.057     8.028 f     -         
check_data_cry[56]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[57]       ALU       CIN      In      -         8.028 f     -         
u_test0.check_data_cry_0[57]       ALU       COUT     Out     0.057     8.085 f     -         
check_data_cry[57]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[58]       ALU       CIN      In      -         8.085 f     -         
u_test0.check_data_cry_0[58]       ALU       COUT     Out     0.057     8.142 f     -         
check_data_cry[58]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[59]       ALU       CIN      In      -         8.142 f     -         
u_test0.check_data_cry_0[59]       ALU       COUT     Out     0.057     8.199 f     -         
check_data_cry[59]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[60]       ALU       CIN      In      -         8.199 f     -         
u_test0.check_data_cry_0[60]       ALU       COUT     Out     0.057     8.256 f     -         
check_data_cry[60]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[61]       ALU       CIN      In      -         8.256 f     -         
u_test0.check_data_cry_0[61]       ALU       COUT     Out     0.057     8.313 f     -         
check_data_cry[61]                 Net       -        -       0.000     -           1         
u_test0.check_data_cry_0[62]       ALU       CIN      In      -         8.313 f     -         
u_test0.check_data_cry_0[62]       ALU       COUT     Out     0.057     8.370 f     -         
check_data_cry[62]                 Net       -        -       0.000     -           1         
u_test0.check_data_s_0[63]         ALU       CIN      In      -         8.370 f     -         
u_test0.check_data_s_0[63]         ALU       SUM      Out     0.563     8.933 f     -         
check_data_s[63]                   Net       -        -       1.021     -           1         
u_test0.check_data[63]             DFFCE     D        In      -         9.954 f     -         
==============================================================================================
Total path delay (propagation time + setup) of 10.087 is 6.597(65.4%) logic and 3.490(34.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: psram_syn_top|clk_d_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                           Starting                                                                   Arrival           
Instance                                   Reference                              Type      Pin     Net               Time        Slack 
                                           Clock                                                                                        
----------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_cnt[0]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[0]       0.367       -1.047
u_PSRAM_TOP.u_psram_sync.lock_syn[1]       psram_syn_top|clk_d_inferred_clock     DFFC      Q       lock_cnt          0.367       -1.041
u_PSRAM_TOP.u_psram_sync.lock_cnt[1]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[1]       0.367       -0.990
u_PSRAM_TOP.u_psram_sync.lock_cnt[2]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[2]       0.367       -0.933
u_PSRAM_TOP.u_psram_sync.lock_cnt[3]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[3]       0.367       -0.876
u_PSRAM_TOP.u_psram_sync.lock_cnt[4]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[4]       0.367       -0.819
u_PSRAM_TOP.u_psram_sync.lock_cnt[5]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[5]       0.367       -0.762
u_PSRAM_TOP.u_psram_sync.lock_cnt[6]       psram_syn_top|clk_d_inferred_clock     DFFCE     Q       lock_cnt[6]       0.367       -0.705
u_PSRAM_TOP.u_psram_sync.cs_memsync[3]     psram_syn_top|clk_d_inferred_clock     DFFCE     Q       cs_memsync[3]     0.367       -0.671
u_PSRAM_TOP.u_psram_sync.flag[1]           psram_syn_top|clk_d_inferred_clock     DFFC      Q       flag[1]           0.367       -0.671
========================================================================================================================================


Ending Points with Worst Slack
******************************

                                           Starting                                                                    Required           
Instance                                   Reference                              Type      Pin     Net                Time         Slack 
                                           Clock                                                                                          
------------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_cnt[15]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[15]     5.801        -1.047
u_PSRAM_TOP.u_psram_sync.lock_cnt[14]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[14]     5.801        -0.990
u_PSRAM_TOP.u_psram_sync.lock_cnt[13]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[13]     5.801        -0.933
u_PSRAM_TOP.u_psram_sync.lock_cnt[12]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[12]     5.801        -0.876
u_PSRAM_TOP.u_psram_sync.lock_cnt[11]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[11]     5.801        -0.819
u_PSRAM_TOP.u_psram_sync.lock_cnt[10]      psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[10]     5.801        -0.762
u_PSRAM_TOP.u_psram_sync.lock_cnt[9]       psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[9]      5.801        -0.705
u_PSRAM_TOP.u_psram_sync.cs_memsync[5]     psram_syn_top|clk_d_inferred_clock     DFFCE     D       ns_memsync[5]      5.801        -0.671
u_PSRAM_TOP.u_psram_sync.flag[1]           psram_syn_top|clk_d_inferred_clock     DFFC      D       flag_ns[1]         5.801        -0.671
u_PSRAM_TOP.u_psram_sync.lock_cnt[8]       psram_syn_top|clk_d_inferred_clock     DFFCE     D       lock_cnt_s[8]      5.801        -0.648
==========================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.934
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.801

    - Propagation time:                      6.848
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.047

    Number of logic level(s):                17
    Starting point:                          u_PSRAM_TOP.u_psram_sync.lock_cnt[0] / Q
    Ending point:                            u_PSRAM_TOP.u_psram_sync.lock_cnt[15] / D
    The start point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK
    The end   point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_cnt[0]              DFFCE     Q        Out     0.367     0.367 r     -         
lock_cnt[0]                                       Net       -        -       1.021     -           2         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      I1       In      -         1.388 r     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      F        Out     1.099     2.487 f     -         
lock_cnt_qxu_lofx[0]                              Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       I0       In      -         3.508 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       COUT     Out     0.958     4.466 f     -         
lock_cnt_cry[0]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       CIN      In      -         4.466 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.057     4.523 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.523 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.580 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.580 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.637 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.637 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.694 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.694 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.751 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.751 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.808 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.808 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.865 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.865 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.922 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.922 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.979 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.979 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     5.036 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         5.036 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.093 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.093 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.150 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.150 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.207 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.207 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.264 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.264 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.827 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt[15]             DFFCE     D        In      -         6.848 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.981 is 3.918(56.1%) logic and 3.063(43.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.934
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.801

    - Propagation time:                      6.842
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.041

    Number of logic level(s):                17
    Starting point:                          u_PSRAM_TOP.u_psram_sync.lock_syn[1] / Q
    Ending point:                            u_PSRAM_TOP.u_psram_sync.lock_cnt[15] / D
    The start point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK
    The end   point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_syn[1]              DFFC      Q        Out     0.367     0.367 r     -         
lock_cnt                                          Net       -        -       1.082     -           18        
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      I0       In      -         1.449 r     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      F        Out     1.032     2.481 f     -         
lock_cnt_qxu_lofx[0]                              Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       I0       In      -         3.502 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       COUT     Out     0.958     4.460 f     -         
lock_cnt_cry[0]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       CIN      In      -         4.460 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.057     4.517 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.517 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.574 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.574 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.631 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.631 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.688 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.688 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.745 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.745 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.802 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.802 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.859 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.859 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.916 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.916 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.973 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.973 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     5.030 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         5.030 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.087 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.087 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.144 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.144 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.201 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.201 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.258 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.258 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.821 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt[15]             DFFCE     D        In      -         6.842 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.975 is 3.851(55.2%) logic and 3.124(44.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.934
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.801

    - Propagation time:                      6.791
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.990

    Number of logic level(s):                16
    Starting point:                          u_PSRAM_TOP.u_psram_sync.lock_cnt[1] / Q
    Ending point:                            u_PSRAM_TOP.u_psram_sync.lock_cnt[15] / D
    The start point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK
    The end   point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_cnt[1]              DFFCE     Q        Out     0.367     0.367 r     -         
lock_cnt[1]                                       Net       -        -       1.021     -           2         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[1]     LUT2      I1       In      -         1.388 r     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[1]     LUT2      F        Out     1.099     2.487 f     -         
lock_cnt_qxu_lofx[1]                              Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       I0       In      -         3.508 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.958     4.466 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.466 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.523 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.523 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.580 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.580 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.637 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.637 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.694 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.694 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.751 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.751 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.808 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.808 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.865 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.865 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.922 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.922 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     4.979 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         4.979 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.036 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.036 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.093 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.093 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.150 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.150 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.207 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.207 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.770 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt[15]             DFFCE     D        In      -         6.791 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.924 is 3.861(55.8%) logic and 3.063(44.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.934
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.801

    - Propagation time:                      6.791
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.990

    Number of logic level(s):                16
    Starting point:                          u_PSRAM_TOP.u_psram_sync.lock_cnt[0] / Q
    Ending point:                            u_PSRAM_TOP.u_psram_sync.lock_cnt[14] / D
    The start point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK
    The end   point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_cnt[0]              DFFCE     Q        Out     0.367     0.367 r     -         
lock_cnt[0]                                       Net       -        -       1.021     -           2         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      I1       In      -         1.388 r     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[0]     LUT2      F        Out     1.099     2.487 f     -         
lock_cnt_qxu_lofx[0]                              Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       I0       In      -         3.508 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[0]        ALU       COUT     Out     0.958     4.466 f     -         
lock_cnt_cry[0]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       CIN      In      -         4.466 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.057     4.523 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.523 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.580 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.580 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.637 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.637 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.694 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.694 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.751 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.751 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.808 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.808 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.865 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.865 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.922 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.922 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.979 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.979 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     5.036 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         5.036 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.093 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.093 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.150 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.150 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.207 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.207 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       SUM      Out     0.563     5.770 f     -         
lock_cnt_s[14]                                    Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt[14]             DFFCE     D        In      -         6.791 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.924 is 3.861(55.8%) logic and 3.063(44.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.934
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.801

    - Propagation time:                      6.785
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.984

    Number of logic level(s):                16
    Starting point:                          u_PSRAM_TOP.u_psram_sync.lock_syn[1] / Q
    Ending point:                            u_PSRAM_TOP.u_psram_sync.lock_cnt[15] / D
    The start point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK
    The end   point is clocked by            psram_syn_top|clk_d_inferred_clock [rising] (rise=0.000 fall=2.967 period=5.934) on pin CLK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                              Type      Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_psram_sync.lock_syn[1]              DFFC      Q        Out     0.367     0.367 r     -         
lock_cnt                                          Net       -        -       1.082     -           18        
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[1]     LUT2      I0       In      -         1.449 r     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_qxu_lofx[1]     LUT2      F        Out     1.032     2.481 f     -         
lock_cnt_qxu_lofx[1]                              Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       I0       In      -         3.502 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[1]        ALU       COUT     Out     0.958     4.460 f     -         
lock_cnt_cry[1]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       CIN      In      -         4.460 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[2]        ALU       COUT     Out     0.057     4.517 f     -         
lock_cnt_cry[2]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       CIN      In      -         4.517 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[3]        ALU       COUT     Out     0.057     4.574 f     -         
lock_cnt_cry[3]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       CIN      In      -         4.574 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[4]        ALU       COUT     Out     0.057     4.631 f     -         
lock_cnt_cry[4]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       CIN      In      -         4.631 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[5]        ALU       COUT     Out     0.057     4.688 f     -         
lock_cnt_cry[5]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       CIN      In      -         4.688 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[6]        ALU       COUT     Out     0.057     4.745 f     -         
lock_cnt_cry[6]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       CIN      In      -         4.745 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[7]        ALU       COUT     Out     0.057     4.802 f     -         
lock_cnt_cry[7]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       CIN      In      -         4.802 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[8]        ALU       COUT     Out     0.057     4.859 f     -         
lock_cnt_cry[8]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       CIN      In      -         4.859 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[9]        ALU       COUT     Out     0.057     4.916 f     -         
lock_cnt_cry[9]                                   Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       CIN      In      -         4.916 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[10]       ALU       COUT     Out     0.057     4.973 f     -         
lock_cnt_cry[10]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       CIN      In      -         4.973 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[11]       ALU       COUT     Out     0.057     5.030 f     -         
lock_cnt_cry[11]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       CIN      In      -         5.030 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[12]       ALU       COUT     Out     0.057     5.087 f     -         
lock_cnt_cry[12]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       CIN      In      -         5.087 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[13]       ALU       COUT     Out     0.057     5.144 f     -         
lock_cnt_cry[13]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       CIN      In      -         5.144 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_cry_0[14]       ALU       COUT     Out     0.057     5.201 f     -         
lock_cnt_cry[14]                                  Net       -        -       0.000     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       CIN      In      -         5.201 f     -         
u_PSRAM_TOP.u_psram_sync.lock_cnt_s_0[15]         ALU       SUM      Out     0.563     5.764 f     -         
lock_cnt_s[15]                                    Net       -        -       1.021     -           1         
u_PSRAM_TOP.u_psram_sync.lock_cnt[15]             DFFCE     D        In      -         6.785 f     -         
=============================================================================================================
Total path delay (propagation time + setup) of 6.918 is 3.794(54.8%) logic and 3.124(45.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: psram_syn_top|memory_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

             Starting                                                                 Arrival           
Instance     Reference                                   Type     Pin     Net         Time        Slack 
             Clock                                                                                      
--------------------------------------------------------------------------------------------------------
cnt[11]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[11]     0.367       -0.991
cnt[2]       psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[2]      0.367       -0.924
cnt[9]       psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[9]      0.367       -0.924
cnt[21]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[21]     0.367       -0.924
cnt[1]       psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[1]      0.367       -0.857
cnt[17]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[17]     0.367       -0.857
cnt[0]       psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[0]      0.367       -0.849
cnt[18]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[18]     0.367       -0.735
cnt[12]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[12]     0.367       -0.714
cnt[20]      psram_syn_top|memory_clk_inferred_clock     DFFC     Q       cnt[20]     0.367       -0.714
========================================================================================================


Ending Points with Worst Slack
******************************

             Starting                                                                     Required           
Instance     Reference                                   Type     Pin     Net             Time         Slack 
             Clock                                                                                           
-------------------------------------------------------------------------------------------------------------
cnt[0]       psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[0]        5.481        -0.991
cnt[9]       psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[9]        5.481        -0.924
cnt[11]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[11]       5.481        -0.924
cnt[12]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[12]       5.481        -0.924
cnt[14]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[14]       5.481        -0.924
cnt[17]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[17]       5.481        -0.924
cnt[21]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[21]       5.481        -0.924
cnt[22]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[22]       5.481        -0.924
cnt[25]      psram_syn_top|memory_clk_inferred_clock     DFFC     D       cnt_3[25]       5.481        -0.924
led_1[0]     psram_syn_top|memory_clk_inferred_clock     DFFC     D       un1_cnt_1_i     5.481        -0.735
=============================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.614
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.481

    - Propagation time:                      6.472
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.991

    Number of logic level(s):                3
    Starting point:                          cnt[11] / Q
    Ending point:                            cnt[0] / D
    The start point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK
    The end   point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[11]            DFFC     Q        Out     0.367     0.367 r     -         
cnt[11]            Net      -        -       1.021     -           3         
cnt10_16           LUT4     I1       In      -         1.388 r     -         
cnt10_16           LUT4     F        Out     1.099     2.487 f     -         
cnt10_16           Net      -        -       0.766     -           1         
cnt10_22           LUT4     I1       In      -         3.253 f     -         
cnt10_22           LUT4     F        Out     1.099     4.352 f     -         
cnt10_22           Net      -        -       1.021     -           9         
cnt_3[0]           LUT4     I1       In      -         5.373 f     -         
cnt_3[0]           LUT4     F        Out     1.099     6.472 f     -         
cnt_3[0]           Net      -        -       0.000     -           1         
cnt[0]             DFFC     D        In      -         6.472 f     -         
=============================================================================
Total path delay (propagation time + setup) of 6.605 is 3.797(57.5%) logic and 2.808(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      5.614
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.481

    - Propagation time:                      6.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.924

    Number of logic level(s):                3
    Starting point:                          cnt[2] / Q
    Ending point:                            cnt[9] / D
    The start point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK
    The end   point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[2]             DFFC     Q        Out     0.367     0.367 r     -         
cnt[2]             Net      -        -       1.021     -           2         
cnt10_14           LUT4     I1       In      -         1.388 r     -         
cnt10_14           LUT4     F        Out     1.099     2.487 f     -         
cnt10_14           Net      -        -       0.766     -           1         
cnt10_21           LUT4     I0       In      -         3.253 f     -         
cnt10_21           LUT4     F        Out     1.032     4.285 f     -         
cnt10_21           Net      -        -       1.021     -           9         
cnt_3[9]           LUT4     I1       In      -         5.306 f     -         
cnt_3[9]           LUT4     F        Out     1.099     6.405 f     -         
cnt_3[9]           Net      -        -       0.000     -           1         
cnt[9]             DFFC     D        In      -         6.405 f     -         
=============================================================================
Total path delay (propagation time + setup) of 6.538 is 3.730(57.1%) logic and 2.808(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      5.614
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.481

    - Propagation time:                      6.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.924

    Number of logic level(s):                3
    Starting point:                          cnt[9] / Q
    Ending point:                            cnt[0] / D
    The start point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK
    The end   point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[9]             DFFC     Q        Out     0.367     0.367 r     -         
cnt[9]             Net      -        -       1.021     -           3         
cnt10_16           LUT4     I0       In      -         1.388 r     -         
cnt10_16           LUT4     F        Out     1.032     2.420 f     -         
cnt10_16           Net      -        -       0.766     -           1         
cnt10_22           LUT4     I1       In      -         3.186 f     -         
cnt10_22           LUT4     F        Out     1.099     4.285 f     -         
cnt10_22           Net      -        -       1.021     -           9         
cnt_3[0]           LUT4     I1       In      -         5.306 f     -         
cnt_3[0]           LUT4     F        Out     1.099     6.405 f     -         
cnt_3[0]           Net      -        -       0.000     -           1         
cnt[0]             DFFC     D        In      -         6.405 f     -         
=============================================================================
Total path delay (propagation time + setup) of 6.538 is 3.730(57.1%) logic and 2.808(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      5.614
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.481

    - Propagation time:                      6.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.924

    Number of logic level(s):                3
    Starting point:                          cnt[21] / Q
    Ending point:                            cnt[0] / D
    The start point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK
    The end   point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[21]            DFFC     Q        Out     0.367     0.367 r     -         
cnt[21]            Net      -        -       1.021     -           4         
cnt10_4            LUT2     I1       In      -         1.388 r     -         
cnt10_4            LUT2     F        Out     1.099     2.487 f     -         
cnt10_4            Net      -        -       0.766     -           1         
cnt10_22           LUT4     I0       In      -         3.253 f     -         
cnt10_22           LUT4     F        Out     1.032     4.285 f     -         
cnt10_22           Net      -        -       1.021     -           9         
cnt_3[0]           LUT4     I1       In      -         5.306 f     -         
cnt_3[0]           LUT4     F        Out     1.099     6.405 f     -         
cnt_3[0]           Net      -        -       0.000     -           1         
cnt[0]             DFFC     D        In      -         6.405 f     -         
=============================================================================
Total path delay (propagation time + setup) of 6.538 is 3.730(57.1%) logic and 2.808(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      5.614
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.481

    - Propagation time:                      6.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.924

    Number of logic level(s):                3
    Starting point:                          cnt[2] / Q
    Ending point:                            cnt[12] / D
    The start point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK
    The end   point is clocked by            psram_syn_top|memory_clk_inferred_clock [rising] (rise=0.000 fall=2.807 period=5.614) on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[2]             DFFC     Q        Out     0.367     0.367 r     -         
cnt[2]             Net      -        -       1.021     -           2         
cnt10_14           LUT4     I1       In      -         1.388 r     -         
cnt10_14           LUT4     F        Out     1.099     2.487 f     -         
cnt10_14           Net      -        -       0.766     -           1         
cnt10_21           LUT4     I0       In      -         3.253 f     -         
cnt10_21           LUT4     F        Out     1.032     4.285 f     -         
cnt10_21           Net      -        -       1.021     -           9         
cnt_3[12]          LUT4     I1       In      -         5.306 f     -         
cnt_3[12]          LUT4     F        Out     1.099     6.405 f     -         
cnt_3[12]          Net      -        -       0.000     -           1         
cnt[12]            DFFC     D        In      -         6.405 f     -         
=============================================================================
Total path delay (propagation time + setup) of 6.538 is 3.730(57.1%) logic and 2.808(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                               Starting                                              Arrival           
Instance                       Reference     Type       Pin         Net              Time        Slack 
                               Clock                                                                   
-------------------------------------------------------------------------------------------------------
u_PLL                          System        PLL        LOCK        pll_lock         0.000       -0.461
u_PSRAM_TOP.clkdiv             System        CLKDIV     CLKOUT      clk_out_i        0.000       0.662 
u_PSRAM_TOP.u_dhcen_clk_x2     System        DHCEN      CLKOUT      clk_x2_i         0.000       1.348 
u_PLL                          System        PLL        CLKOUT      memory_clk_i     0.000       1.409 
u_PSRAM_TOP.u_dll              System        DLL        LOCK        dll_lock         0.000       3.681 
u_PSRAM_TOP.u_dll              System        DLL        STEP[0]     dll_step[0]      0.000       4.071 
u_PSRAM_TOP.u_dll              System        DLL        STEP[1]     dll_step[1]      0.000       4.128 
u_PSRAM_TOP.u_dll              System        DLL        STEP[2]     dll_step[2]      0.000       4.185 
u_PSRAM_TOP.u_dll              System        DLL        STEP[3]     dll_step[3]      0.000       4.242 
u_PSRAM_TOP.u_dll              System        DLL        STEP[4]     dll_step[4]      0.000       4.299 
=======================================================================================================


Ending Points with Worst Slack
******************************

                                          Starting                                           Required           
Instance                                  Reference     Type     Pin      Net                Time         Slack 
                                          Clock                                                                 
----------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.u_dll                         System        DLL      STOP     pll_lock_i         2.613        -0.461
u_PSRAM_TOP.u_psram_top0.rd_data_d[0]     System        DFFC     D        rd_data_d_3[0]     8.489        0.662 
u_PSRAM_TOP.u_psram_top1.rd_data_d[0]     System        DFFC     D        rd_data_d_3[0]     8.489        0.662 
u_PSRAM_TOP.u_psram_top0.rd_data_d[1]     System        DFFC     D        rd_data_d_3[1]     8.489        0.662 
u_PSRAM_TOP.u_psram_top1.rd_data_d[1]     System        DFFC     D        rd_data_d_3[1]     8.489        0.662 
u_PSRAM_TOP.u_psram_top0.rd_data_d[2]     System        DFFC     D        rd_data_d_3[2]     8.489        0.662 
u_PSRAM_TOP.u_psram_top1.rd_data_d[2]     System        DFFC     D        rd_data_d_3[2]     8.489        0.662 
u_PSRAM_TOP.u_psram_top0.rd_data_d[3]     System        DFFC     D        rd_data_d_3[3]     8.489        0.662 
u_PSRAM_TOP.u_psram_top1.rd_data_d[3]     System        DFFC     D        rd_data_d_3[3]     8.489        0.662 
u_PSRAM_TOP.u_psram_top1.rd_data_d[4]     System        DFFC     D        rd_data_d_3[4]     8.489        0.662 
================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      2.613
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         2.613

    - Propagation time:                      3.074
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 -0.461

    Number of logic level(s):                1
    Starting point:                          u_PLL / LOCK
    Ending point:                            u_PSRAM_TOP.u_dll / STOP
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
u_PLL                 PLL      LOCK     Out     0.000     0.000 r     -         
pll_lock              Net      -        -       1.021     -           2         
pll_lock_i            INV      I        In      -         1.021 r     -         
pll_lock_i            INV      O        Out     1.032     2.053 f     -         
pll_lock_i            Net      -        -       1.021     -           1         
u_PSRAM_TOP.u_dll     DLL      STOP     In      -         3.074 f     -         
================================================================================
Total path delay (propagation time + setup) of 3.074 is 1.032(33.6%) logic and 2.042(66.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      7.827
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 0.662

    Number of logic level(s):                2
    Starting point:                          u_PSRAM_TOP.clkdiv / CLKOUT
    Ending point:                            u_PSRAM_TOP.u_psram_top1.rd_data_d[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                                                                                                Pin        Pin               Arrival     No. of    
Name                                                                                               Type       Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.clkdiv                                                                                 CLKDIV     CLKOUT     Out     0.000     0.000 r     -         
clk_out_i                                                                                          Net        -          -       5.295     -           1363      
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4     IDES4      PCLK       In      -         5.295 r     -         
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4     IDES4      Q3         Out     0.479     5.774 r     -         
rd_data_d0[0]                                                                                      Net        -          -       1.021     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[0]                                                            LUT2       I0         In      -         6.795 r     -         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[0]                                                            LUT2       F          Out     1.032     7.827 f     -         
rd_data_d_3[0]                                                                                     Net        -          -       0.000     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d[0]                                                              DFFC       D          In      -         7.827 f     -         
=================================================================================================================================================================
Total path delay (propagation time + setup) of 7.960 is 1.644(20.7%) logic and 6.316(79.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      7.827
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 0.662

    Number of logic level(s):                2
    Starting point:                          u_PSRAM_TOP.clkdiv / CLKOUT
    Ending point:                            u_PSRAM_TOP.u_psram_top1.rd_data_d[7] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                                                                                                Pin        Pin               Arrival     No. of    
Name                                                                                               Type       Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.clkdiv                                                                                 CLKDIV     CLKOUT     Out     0.000     0.000 r     -         
clk_out_i                                                                                          Net        -          -       5.295     -           1363      
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[7\]\.u_ides4     IDES4      PCLK       In      -         5.295 r     -         
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[7\]\.u_ides4     IDES4      Q3         Out     0.479     5.774 r     -         
rd_data_d0[7]                                                                                      Net        -          -       1.021     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[7]                                                            LUT2       I0         In      -         6.795 r     -         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[7]                                                            LUT2       F          Out     1.032     7.827 f     -         
rd_data_d_3[7]                                                                                     Net        -          -       0.000     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d[7]                                                              DFFC       D          In      -         7.827 f     -         
=================================================================================================================================================================
Total path delay (propagation time + setup) of 7.960 is 1.644(20.7%) logic and 6.316(79.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      7.827
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 0.662

    Number of logic level(s):                2
    Starting point:                          u_PSRAM_TOP.clkdiv / CLKOUT
    Ending point:                            u_PSRAM_TOP.u_psram_top1.rd_data_d[5] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                                                                                                Pin        Pin               Arrival     No. of    
Name                                                                                               Type       Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.clkdiv                                                                                 CLKDIV     CLKOUT     Out     0.000     0.000 r     -         
clk_out_i                                                                                          Net        -          -       5.295     -           1363      
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[5\]\.u_ides4     IDES4      PCLK       In      -         5.295 r     -         
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[5\]\.u_ides4     IDES4      Q3         Out     0.479     5.774 r     -         
rd_data_d0[5]                                                                                      Net        -          -       1.021     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[5]                                                            LUT2       I0         In      -         6.795 r     -         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[5]                                                            LUT2       F          Out     1.032     7.827 f     -         
rd_data_d_3[5]                                                                                     Net        -          -       0.000     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d[5]                                                              DFFC       D          In      -         7.827 f     -         
=================================================================================================================================================================
Total path delay (propagation time + setup) of 7.960 is 1.644(20.7%) logic and 6.316(79.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      8.622
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.489

    - Propagation time:                      7.827
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 0.662

    Number of logic level(s):                2
    Starting point:                          u_PSRAM_TOP.clkdiv / CLKOUT
    Ending point:                            u_PSRAM_TOP.u_psram_top1.rd_data_d[6] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            psram_memory_interface_top_2ch|clk_out_inferred_clock [rising] (rise=0.000 fall=4.311 period=8.622) on pin CLK

Instance / Net                                                                                                Pin        Pin               Arrival     No. of    
Name                                                                                               Type       Name       Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
u_PSRAM_TOP.clkdiv                                                                                 CLKDIV     CLKOUT     Out     0.000     0.000 r     -         
clk_out_i                                                                                          Net        -          -       5.295     -           1363      
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4     IDES4      PCLK       In      -         5.295 r     -         
u_PSRAM_TOP.u_psram_top1.u_psram_wd.data_lane_gen\[0\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4     IDES4      Q3         Out     0.479     5.774 r     -         
rd_data_d0[6]                                                                                      Net        -          -       1.021     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[6]                                                            LUT2       I0         In      -         6.795 r     -         
u_PSRAM_TOP.u_psram_top1.rd_data_d_3[6]                                                            LUT2       F          Out     1.032     7.827 f     -         
rd_data_d_3[6]                                                                                     Net        -          -       0.000     -           1         
u_PSRAM_TOP.u_psram_top1.rd_data_d[6]                                                              DFFC       D          In      -         7.827 f     -         
=================================================================================================================================================================
Total path delay (propagation time + setup) of 7.960 is 1.644(20.7%) logic and 6.316(79.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 267MB peak: 271MB)


Finished timing report (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 267MB peak: 271MB)

---------------------------------------
Resource Usage Report for psram_syn_top 

Mapping to part: gw1nr_9cmbga100pa-7
Cell usage:
ALU             660 uses
CLKDIV          1 use
DFFC            620 uses
DFFCE           754 uses
DFFP            14 uses
DFFPE           1 use
DHCEN           1 use
DLL             1 use
GSR             1 use
IDES4           16 uses
INV             20 uses
IODELAY         20 uses
OSER4           24 uses
PLL             1 use
LUT2            732 uses
LUT3            352 uses
LUT4            638 uses

I/O ports: 34
I/O primitives: 32
ELVDS_OBUF     2 uses
IBUF           2 uses
IOBUF          18 uses
OBUF           8 uses
TBUF           2 uses

I/O Register bits:                  0
Register bits not including I/Os:   1389 of 6480 (21%)
Total load per clock:
   psram_syn_top|memory_clk_inferred_clock: 35
   psram_memory_interface_top_2ch|clk_out_inferred_clock: 1363
   psram_memory_interface_top_2ch|clk_x2_inferred_clock: 40
   psram_syn_top|clk_d_inferred_clock: 31
   _~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0]: 8
   _~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0]: 2
   _~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0]: 8
   _~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0]: 2

@S |Mapping Summary:
Total  LUTs: 1722 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:11s; Memory used current: 97MB peak: 271MB)

Process took 0h:00m:13s realtime, 0h:00m:12s cputime
# Mon Feb 22 14:30:43 2021

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