Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project_1.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\ap.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
GOWIN version | V1.9.7.02Beta |
Part Number | GW1NR-LV9MG100PAC7/I6 |
Device | GW1NR-9C |
Created Time | Tue Mar 09 17:15:00 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 5338 |
Numbers of Endpoints Analyzed | 5359 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk_x2p | Base | 7.143 | 139.997 | 0.000 | 3.571 | u_PSRAM_TOP/clk_x2p | ||
clk_d | Base | 28.571 | 35.001 | 0.000 | 14.286 | clk_d | ||
clk_x2 | Base | 7.143 | 139.997 | 0.000 | 3.571 | u_PSRAM_TOP/clk_x2 | ||
clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
clk_x1 | Base | 14.286 | 69.999 | 0.000 | 7.143 | clk_x1 | ||
your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.000 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.000 | 1.563 | 4.688 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.333 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_d | 35.001(MHz) | 126.400(MHz) | 4 | TOP |
2 | clk_x1 | 69.999(MHz) | 96.123(MHz) | 5 | TOP |
No timing paths to get frequency of clk_x2p!
No timing paths to get frequency of clk_x2!
No timing paths to get frequency of clk!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_x2p | Setup | 0.000 | 0 |
clk_x2p | Hold | 0.000 | 0 |
clk_d | Setup | 0.000 | 0 |
clk_d | Hold | 0.000 | 0 |
clk_x2 | Setup | 0.000 | 0 |
clk_x2 | Hold | 0.000 | 0 |
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
clk_x1 | Setup | 0.000 | 0 |
clk_x1 | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 3.676 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.359 |
2 | 3.680 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.355 |
3 | 3.798 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.237 |
4 | 3.807 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.228 |
5 | 3.883 | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q | u_test1/curr_state.WRITE_WAITE_s0/D | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 10.107 |
6 | 3.906 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.129 |
7 | 3.919 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.116 |
8 | 4.024 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.012 |
9 | 4.024 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 3.012 |
10 | 4.146 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.889 |
11 | 4.146 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.889 |
12 | 4.158 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.877 |
13 | 4.158 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.877 |
14 | 4.166 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.869 |
15 | 4.283 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.752 |
16 | 4.283 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.752 |
17 | 4.344 | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q | u_test1/curr_state.IDLE_s0/D | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 9.645 |
18 | 4.364 | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q | u_test1/curr_state.CYC_DONE_WAITE_s0/D | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 9.626 |
19 | 4.403 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.632 |
20 | 4.408 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.627 |
21 | 4.413 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.623 |
22 | 4.414 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.621 |
23 | 4.519 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.516 |
24 | 4.519 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.516 |
25 | 4.534 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | 0.078 | 2.501 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.412 | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.423 |
2 | 0.524 | u_test1/check_data_31_s1/Q | u_test1/check_data_31_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
3 | 0.524 | u_test1/wr_data_add_62_s1/Q | u_test1/wr_data_add_62_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
4 | 0.524 | u_test0/check_data_15_s1/Q | u_test0/check_data_15_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
5 | 0.524 | u_test0/check_data_31_s1/Q | u_test0/check_data_31_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
6 | 0.524 | u_test0/wr_data_add_1_s1/Q | u_test0/wr_data_add_1_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
7 | 0.524 | u_test0/wr_data_add_36_s1/Q | u_test0/wr_data_add_36_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
8 | 0.524 | u_test0/wr_data_add_48_s1/Q | u_test0/wr_data_add_48_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
9 | 0.524 | u_test0/wr_data_add_58_s1/Q | u_test0/wr_data_add_58_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
10 | 0.524 | u_test0/curr_state.WRITE_WAITE_s0/Q | u_test0/curr_state.WRITE_WAITE_s0/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
11 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
12 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
13 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
14 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
15 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
16 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
17 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
18 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
19 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
20 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
21 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
22 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
23 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
24 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
25 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0 |
2 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0 |
3 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0 |
4 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0 |
5 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0 |
6 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0 |
7 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_num_d_1_s0 |
8 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/cs_d1_s0 |
9 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_10_s1 |
10 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 3.676 |
Data Arrival Time | 3.540 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
3.540 | 3.020 | tNET | FF | 1 | IOL2[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL2[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL2[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.020, 89.890%; tC2Q: 0.340, 10.110% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path2
Path Summary:
Slack | 3.680 |
Data Arrival Time | 3.535 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
3.535 | 3.015 | tNET | FF | 1 | IOL3[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL3[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL3[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.015, 89.876%; tC2Q: 0.340, 10.124% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path3
Path Summary:
Slack | 3.798 |
Data Arrival Time | 3.418 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
3.418 | 2.898 | tNET | FF | 1 | IOL4[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL4[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL4[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.898, 89.509%; tC2Q: 0.340, 10.491% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path4
Path Summary:
Slack | 3.807 |
Data Arrival Time | 3.409 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
3.409 | 2.889 | tNET | FF | 1 | IOL8[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL8[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL8[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.889, 89.480%; tC2Q: 0.340, 10.520% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path5
Path Summary:
Slack | 3.883 |
Data Arrival Time | 10.288 |
Data Required Time | 14.170 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
To | u_test1/curr_state.WRITE_WAITE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 151 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q |
5.967 | 5.447 | tNET | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/I1 |
6.431 | 0.464 | tINS | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/F |
6.435 | 0.004 | tNET | FF | 1 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/I2 |
7.044 | 0.609 | tINS | FF | 3 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/F |
8.363 | 1.318 | tNET | FF | 1 | R12C38[0][A] | u_test1/next_state.READ_BURST_s13/I3 |
8.972 | 0.609 | tINS | FF | 3 | R12C38[0][A] | u_test1/next_state.READ_BURST_s13/F |
9.824 | 0.852 | tNET | FF | 1 | R20C36[2][A] | u_test1/next_state.WRITE_WAITE_s10/I3 |
10.288 | 0.464 | tINS | FF | 1 | R20C36[2][A] | u_test1/next_state.WRITE_WAITE_s10/F |
10.288 | 0.000 | tNET | FF | 1 | R20C36[2][A] | u_test1/curr_state.WRITE_WAITE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R20C36[2][A] | u_test1/curr_state.WRITE_WAITE_s0/CLK |
14.170 | -0.296 | tSu | 1 | R20C36[2][A] | u_test1/curr_state.WRITE_WAITE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.146, 21.232%; route: 7.621, 75.407%; tC2Q: 0.340, 3.360% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path6
Path Summary:
Slack | 3.906 |
Data Arrival Time | 3.310 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.310 | 2.790 | tNET | FF | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.790, 89.147%; tC2Q: 0.340, 10.853% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path7
Path Summary:
Slack | 3.919 |
Data Arrival Time | 3.297 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.297 | 2.776 | tNET | FF | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.776, 89.100%; tC2Q: 0.340, 10.900% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path8
Path Summary:
Slack | 4.024 |
Data Arrival Time | 3.192 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.192 | 2.672 | tNET | FF | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.672, 88.723%; tC2Q: 0.340, 11.277% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path9
Path Summary:
Slack | 4.024 |
Data Arrival Time | 3.192 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.192 | 2.672 | tNET | FF | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.672, 88.723%; tC2Q: 0.340, 11.277% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path10
Path Summary:
Slack | 4.146 |
Data Arrival Time | 3.070 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.070 | 2.549 | tNET | FF | 1 | IOR12[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR12[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR12[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.549, 88.244%; tC2Q: 0.340, 11.756% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path11
Path Summary:
Slack | 4.146 |
Data Arrival Time | 3.070 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
3.070 | 2.549 | tNET | FF | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.549, 88.244%; tC2Q: 0.340, 11.756% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path12
Path Summary:
Slack | 4.158 |
Data Arrival Time | 3.058 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.058 | 2.537 | tNET | FF | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.537, 88.196%; tC2Q: 0.340, 11.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path13
Path Summary:
Slack | 4.158 |
Data Arrival Time | 3.058 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.058 | 2.537 | tNET | FF | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.537, 88.196%; tC2Q: 0.340, 11.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path14
Path Summary:
Slack | 4.166 |
Data Arrival Time | 3.050 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
3.050 | 2.530 | tNET | FF | 1 | IOL6[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL6[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL6[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.530, 88.163%; tC2Q: 0.340, 11.837% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path15
Path Summary:
Slack | 4.283 |
Data Arrival Time | 2.933 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.933 | 2.412 | tNET | FF | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.412, 87.659%; tC2Q: 0.340, 12.341% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path16
Path Summary:
Slack | 4.283 |
Data Arrival Time | 2.933 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
2.933 | 2.412 | tNET | FF | 1 | IOL12[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL12[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL12[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.412, 87.658%; tC2Q: 0.340, 12.342% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path17
Path Summary:
Slack | 4.344 |
Data Arrival Time | 9.826 |
Data Required Time | 14.170 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
To | u_test1/curr_state.IDLE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 151 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q |
5.967 | 5.447 | tNET | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/I1 |
6.431 | 0.464 | tINS | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/F |
6.435 | 0.004 | tNET | FF | 1 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/I2 |
7.029 | 0.594 | tINS | FR | 3 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/F |
7.341 | 0.312 | tNET | RR | 1 | R12C38[3][A] | u_test1/next_state.IDLE_s14/I3 |
8.156 | 0.814 | tINS | RF | 2 | R12C38[3][A] | u_test1/next_state.IDLE_s14/F |
9.362 | 1.207 | tNET | FF | 1 | R18C36[2][B] | u_test1/next_state.IDLE_s12/I2 |
9.826 | 0.464 | tINS | FF | 1 | R18C36[2][B] | u_test1/next_state.IDLE_s12/F |
9.826 | 0.000 | tNET | FF | 1 | R18C36[2][B] | u_test1/curr_state.IDLE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R18C36[2][B] | u_test1/curr_state.IDLE_s0/CLK |
14.170 | -0.296 | tSu | 1 | R18C36[2][B] | u_test1/curr_state.IDLE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.336, 24.223%; route: 6.969, 72.256%; tC2Q: 0.340, 3.521% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path18
Path Summary:
Slack | 4.364 |
Data Arrival Time | 9.807 |
Data Required Time | 14.170 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
To | u_test1/curr_state.CYC_DONE_WAITE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 151 | R25C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q |
5.967 | 5.447 | tNET | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/I1 |
6.431 | 0.464 | tINS | FF | 1 | R11C38[3][A] | u_test1/next_state.CYC_DONE_s14/F |
6.435 | 0.004 | tNET | FF | 1 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/I2 |
7.044 | 0.609 | tINS | FF | 3 | R11C38[0][B] | u_test1/next_state.CYC_DONE_s12/F |
8.363 | 1.318 | tNET | FF | 1 | R12C38[0][A] | u_test1/next_state.READ_BURST_s13/I3 |
8.972 | 0.609 | tINS | FF | 3 | R12C38[0][A] | u_test1/next_state.READ_BURST_s13/F |
9.343 | 0.371 | tNET | FF | 1 | R12C40[1][B] | u_test1/next_state.CYC_DONE_WAITE_s12/I0 |
9.807 | 0.464 | tINS | FF | 1 | R12C40[1][B] | u_test1/next_state.CYC_DONE_WAITE_s12/F |
9.807 | 0.000 | tNET | FF | 1 | R12C40[1][B] | u_test1/curr_state.CYC_DONE_WAITE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R12C40[1][B] | u_test1/curr_state.CYC_DONE_WAITE_s0/CLK |
14.170 | -0.296 | tSu | 1 | R12C40[1][B] | u_test1/curr_state.CYC_DONE_WAITE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.146, 22.293%; route: 7.140, 74.179%; tC2Q: 0.340, 3.528% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path19
Path Summary:
Slack | 4.403 |
Data Arrival Time | 2.813 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R25C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.813 | 2.292 | tNET | FF | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.292, 87.095%; tC2Q: 0.340, 12.905% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path20
Path Summary:
Slack | 4.408 |
Data Arrival Time | 2.808 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.808 | 2.288 | tNET | FF | 1 | IOL17[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL17[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL17[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.288, 87.073%; tC2Q: 0.340, 12.927% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path21
Path Summary:
Slack | 4.413 |
Data Arrival Time | 2.803 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.803 | 2.283 | tNET | FF | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.283, 87.050%; tC2Q: 0.340, 12.950% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path22
Path Summary:
Slack | 4.414 |
Data Arrival Time | 2.802 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_0_s0/Q |
2.802 | 2.281 | tNET | FF | 1 | IOL15[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL15[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL15[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.281, 87.043%; tC2Q: 0.340, 12.957% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path23
Path Summary:
Slack | 4.519 |
Data Arrival Time | 2.697 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.697 | 2.177 | tNET | FF | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.177, 86.503%; tC2Q: 0.340, 13.497% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path24
Path Summary:
Slack | 4.519 |
Data Arrival Time | 2.697 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R21C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.697 | 2.177 | tNET | FF | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.177, 86.503%; tC2Q: 0.340, 13.497% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Path25
Path Summary:
Slack | 4.534 |
Data Arrival Time | 2.681 |
Data Required Time | 7.216 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R22C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.681 | 2.161 | tNET | FF | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 73 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.246 | 0.103 | tNET | RR | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.216 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.216 | 0.000 | tSu | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | -0.078 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.161, 86.419%; tC2Q: 0.340, 13.581% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.103, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.412 |
Data Arrival Time | 0.560 |
Data Required Time | 0.148 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R25C20[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q |
0.560 | 0.176 | tNET | RR | 1 | R25C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK |
0.148 | 0.011 | tHld | 1 | R25C20[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path2
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/check_data_31_s1 |
To | u_test1/check_data_31_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C37[0][A] | u_test1/check_data_31_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R22C37[0][A] | u_test1/check_data_31_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R22C37[0][A] | u_test1/n1566_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R22C37[0][A] | u_test1/n1566_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R22C37[0][A] | u_test1/check_data_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C37[0][A] | u_test1/check_data_31_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C37[0][A] | u_test1/check_data_31_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path3
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/wr_data_add_62_s1 |
To | u_test1/wr_data_add_62_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C38[1][A] | u_test1/wr_data_add_62_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R15C38[1][A] | u_test1/wr_data_add_62_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R15C38[1][A] | u_test1/n652_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R15C38[1][A] | u_test1/n652_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R15C38[1][A] | u_test1/wr_data_add_62_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C38[1][A] | u_test1/wr_data_add_62_s1/CLK |
0.137 | 0.000 | tHld | 1 | R15C38[1][A] | u_test1/wr_data_add_62_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path4
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/check_data_15_s1 |
To | u_test0/check_data_15_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C10[1][A] | u_test0/check_data_15_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R16C10[1][A] | u_test0/check_data_15_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R16C10[1][A] | u_test0/n1582_s3/I2 |
0.661 | 0.276 | tINS | RF | 1 | R16C10[1][A] | u_test0/n1582_s3/F |
0.661 | 0.000 | tNET | FF | 1 | R16C10[1][A] | u_test0/check_data_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C10[1][A] | u_test0/check_data_15_s1/CLK |
0.137 | 0.000 | tHld | 1 | R16C10[1][A] | u_test0/check_data_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path5
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/check_data_31_s1 |
To | u_test0/check_data_31_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C9[0][A] | u_test0/check_data_31_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R16C9[0][A] | u_test0/check_data_31_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R16C9[0][A] | u_test0/n1566_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R16C9[0][A] | u_test0/n1566_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R16C9[0][A] | u_test0/check_data_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C9[0][A] | u_test0/check_data_31_s1/CLK |
0.137 | 0.000 | tHld | 1 | R16C9[0][A] | u_test0/check_data_31_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path6
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_1_s1 |
To | u_test0/wr_data_add_1_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C8[1][A] | u_test0/wr_data_add_1_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R9C8[1][A] | u_test0/wr_data_add_1_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R9C8[1][A] | u_test0/n713_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R9C8[1][A] | u_test0/n713_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R9C8[1][A] | u_test0/wr_data_add_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C8[1][A] | u_test0/wr_data_add_1_s1/CLK |
0.137 | 0.000 | tHld | 1 | R9C8[1][A] | u_test0/wr_data_add_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path7
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_36_s1 |
To | u_test0/wr_data_add_36_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C6[0][A] | u_test0/wr_data_add_36_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R7C6[0][A] | u_test0/wr_data_add_36_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R7C6[0][A] | u_test0/n678_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R7C6[0][A] | u_test0/n678_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R7C6[0][A] | u_test0/wr_data_add_36_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C6[0][A] | u_test0/wr_data_add_36_s1/CLK |
0.137 | 0.000 | tHld | 1 | R7C6[0][A] | u_test0/wr_data_add_36_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path8
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_48_s1 |
To | u_test0/wr_data_add_48_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R11C8[1][A] | u_test0/wr_data_add_48_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R11C8[1][A] | u_test0/wr_data_add_48_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R11C8[1][A] | u_test0/n666_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R11C8[1][A] | u_test0/n666_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R11C8[1][A] | u_test0/wr_data_add_48_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R11C8[1][A] | u_test0/wr_data_add_48_s1/CLK |
0.137 | 0.000 | tHld | 1 | R11C8[1][A] | u_test0/wr_data_add_48_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path9
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_58_s1 |
To | u_test0/wr_data_add_58_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R8C8[0][A] | u_test0/wr_data_add_58_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R8C8[0][A] | u_test0/wr_data_add_58_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R8C8[0][A] | u_test0/n656_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R8C8[0][A] | u_test0/n656_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R8C8[0][A] | u_test0/wr_data_add_58_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R8C8[0][A] | u_test0/wr_data_add_58_s1/CLK |
0.137 | 0.000 | tHld | 1 | R8C8[0][A] | u_test0/wr_data_add_58_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path10
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/curr_state.WRITE_WAITE_s0 |
To | u_test0/curr_state.WRITE_WAITE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C8[0][A] | u_test0/curr_state.WRITE_WAITE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R20C8[0][A] | u_test0/curr_state.WRITE_WAITE_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R20C8[0][A] | u_test0/next_state.WRITE_WAITE_s10/I2 |
0.661 | 0.276 | tINS | RF | 1 | R20C8[0][A] | u_test0/next_state.WRITE_WAITE_s10/F |
0.661 | 0.000 | tNET | FF | 1 | R20C8[0][A] | u_test0/curr_state.WRITE_WAITE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C8[0][A] | u_test0/curr_state.WRITE_WAITE_s0/CLK |
0.137 | 0.000 | tHld | 1 | R20C8[0][A] | u_test0/curr_state.WRITE_WAITE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path11
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/Q |
0.386 | 0.002 | tNET | RR | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1700_s4/I2 |
0.661 | 0.276 | tINS | RF | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1700_s4/F |
0.661 | 0.000 | tNET | FF | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/CLK |
0.137 | 0.000 | tHld | 1 | R17C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path12
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2382_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2382_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R25C31[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path13
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R20C32[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path14
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1701_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1701_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R17C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path15
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1698_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1698_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/CLK |
0.137 | 0.000 | tHld | 1 | R18C25[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path16
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 6 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1623_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1623_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/CLK |
0.137 | 0.000 | tHld | 1 | R23C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path17
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1621_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1621_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R25C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path18
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1618_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1618_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1/CLK |
0.137 | 0.000 | tHld | 1 | R24C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path19
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n580_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n580_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R21C24[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path20
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n579_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n579_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/CLK |
0.137 | 0.000 | tHld | 1 | R21C24[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path21
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n449_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n449_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/CLK |
0.137 | 0.000 | tHld | 1 | R16C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path22
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n438_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n438_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1/CLK |
0.137 | 0.000 | tHld | 1 | R16C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path23
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n_state.INIT_CALIB_DONE_s27/I1 |
0.661 | 0.276 | tINS | RF | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n_state.INIT_CALIB_DONE_s27/F |
0.661 | 0.000 | tNET | FF | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK |
0.137 | 0.000 | tHld | 1 | R25C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path24
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n395_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n395_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R11C35[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/LA_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path25
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n282_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n282_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1907 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1/CLK |
0.137 | 0.000 | tHld | 1 | R7C33[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/burst_cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK |
MPW2
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0/CLK |
MPW3
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0/CLK |
MPW4
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0/CLK |
MPW5
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0/CLK |
MPW6
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK |
MPW7
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_num_d_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_num_d_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/burst_num_d_1_s0/CLK |
MPW8
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/cs_d1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/cs_d1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/cs_d1_s0/CLK |
MPW9
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_10_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_10_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_10_s1/CLK |
MPW10
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_2_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1907 | clk_x1 | 3.676 | 0.195 |
153 | curr_state.WRITE_BURST | 7.534 | 2.801 |
152 | curr_state.WRITE_BURST | 8.034 | 2.446 |
151 | init_calib1_d | 3.883 | 5.447 |
150 | init_calib0_d | 4.665 | 3.506 |
86 | wr_data_63_11 | 7.451 | 2.201 |
86 | wr_data_63_11 | 5.301 | 3.041 |
76 | config_done_Z | 10.100 | 2.941 |
76 | config_done_Z | 10.038 | 1.339 |
74 | wr_data_d0_0_5 | 11.418 | 2.496 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R21C8 | 63.89% |
R22C9 | 59.72% |
R20C8 | 58.33% |
R21C9 | 58.33% |
R23C8 | 56.94% |
R8C18 | 55.56% |
R17C39 | 55.56% |
R16C25 | 54.17% |
R7C40 | 52.78% |
R15C39 | 52.78% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk_x2p -period 7.143 -waveform {0 3.571} [get_nets {u_PSRAM_TOP/clk_x2p}] |
TC_CLOCK | Actived | create_clock -name clk_d -period 28.571 -waveform {0 14.286} [get_nets {clk_d}] |
TC_CLOCK | Actived | create_clock -name clk_x2 -period 7.143 -waveform {0 3.571} [get_nets {u_PSRAM_TOP/clk_x2}] |
TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name clk_x1 -period 14.286 -waveform {0 7.143} [get_nets {clk_x1}] |