Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\apsram_syn_top.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\apsram_test.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\uhs_psram_memory_interface_2ch_v2\uhs_psram_memory_interface_2ch_v2.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW1NR-LV9MG100PAC7/I6 |
Device | GW1NR-9C |
Created Time | Tue Mar 09 17:14:52 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | psram_syn_top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 140.277MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 140.277MB Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 140.277MB Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 140.277MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 140.277MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 140.277MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 140.277MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 140.277MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 140.277MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.07s, Peak memory usage = 140.277MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 140.277MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 150.961MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.291s, Peak memory usage = 150.961MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 150.961MB |
Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 150.961MB |
Resource
Resource Usage Summary
I/O Port | 6 |
Emedded Port | 52 |
I/O Buf | 54 |
    IBUF | 2 |
    OBUF | 8 |
    TBUF | 4 |
    IOBUF | 36 |
    ELVDS_OBUF | 4 |
Register | 1822 |
    DFF | 1 |
    DFFP | 12 |
    DFFPE | 12 |
    DFFC | 873 |
    DFFCE | 924 |
LUT | 2783 |
    LUT2 | 591 |
    LUT3 | 935 |
    LUT4 | 1257 |
ALU | 234 |
    ALU | 234 |
SSRAM | 36 |
    RAM16S4 | 36 |
INV | 28 |
    INV | 28 |
IOLOGIC | 112 |
    IDES4 | 32 |
    OSER4 | 48 |
    IODELAY | 32 |
CLOCK | 4 |
    CLKDIV | 1 |
    DHCEN | 2 |
    rPLL | 1 |
Resource Utilization Summary
Logic | 3261(2811 LUTs, 234 ALUs, 36 SSRAMs) / 8640 | 38% |
Register | 1822 / 6900 | 26% |
  --Register as Latch | 0 / 6900 | 0% |
  --Register as FF | 1822 / 6900 | 26% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.0 | 1.563 | 4.688 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.3 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | u_PSRAM_TOP/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | 40.0(MHz) | 182.9(MHz) | 5 | TOP |
2 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | 80.0(MHz) | 161.6(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.342 |
Data Arrival Time | 2.224 |
Data Required Time | 4.565 |
From | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0 |
To | u_PSRAM_TOP/u_dhcen_clk_x2 |
Launch Clk | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F] |
Latch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | |||
1.259 | 1.259 | tCL | RR | 31 | your_instance_name/rpll_inst/CLKOUTD |
1.528 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK |
1.868 | 0.340 | tC2Q | RF | 9 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q |
2.224 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_dhcen_clk_x2/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
3.125 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
4.427 | 1.302 | tCL | FF | 1 | your_instance_name/rpll_inst/CLKOUT |
4.783 | 0.356 | tNET | FF | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
4.753 | -0.030 | tUnc | u_PSRAM_TOP/u_dhcen_clk_x2 | ||
4.565 | -0.188 | tSu | 1 | u_PSRAM_TOP/u_dhcen_clk_x2 |
Clock Skew: | 0.130 |
Setup Relationship: | 3.125 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.356, 100.000% |
Path 2
Path Summary:Slack | 3.876 |
Data Arrival Time | 2.224 |
Data Required Time | 6.100 |
From | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0 |
To | u_PSRAM_TOP/u_dhcen_clk_x2p |
Launch Clk | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F] |
Latch Clk | your_instance_name/rpll_inst/CLKOUTP.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | |||
1.259 | 1.259 | tCL | RR | 31 | your_instance_name/rpll_inst/CLKOUTD |
1.528 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK |
1.868 | 0.340 | tC2Q | RF | 9 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q |
2.224 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_dhcen_clk_x2p/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
4.688 | 0.000 | your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | |||
5.962 | 1.275 | tCL | FF | 1 | your_instance_name/rpll_inst/CLKOUTP |
6.318 | 0.356 | tNET | FF | 3 | u_PSRAM_TOP/u_dhcen_clk_x2p/CLKIN |
6.288 | -0.030 | tUnc | u_PSRAM_TOP/u_dhcen_clk_x2p | ||
6.100 | -0.188 | tSu | 1 | u_PSRAM_TOP/u_dhcen_clk_x2p |
Clock Skew: | 0.102 |
Setup Relationship: | 4.688 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.356, 100.000% |
Path 3
Path Summary:Slack | 6.313 |
Data Arrival Time | 6.429 |
Data Required Time | 12.742 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0 |
To | u_test1/curr_state.CYC_DONE_WAITE_s0 |
Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
0.269 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
0.538 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 24 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/Q |
1.234 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/I1 |
2.048 | 0.814 | tINS | FF | 7 | u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/F |
2.404 | 0.356 | tNET | FF | 1 | u_test1/next_state.CYC_DONE_s14/I0 |
3.168 | 0.765 | tINS | FF | 1 | u_test1/next_state.CYC_DONE_s14/F |
3.524 | 0.356 | tNET | FF | 1 | u_test1/next_state.CYC_DONE_s12/I2 |
4.133 | 0.609 | tINS | FF | 3 | u_test1/next_state.CYC_DONE_s12/F |
4.489 | 0.356 | tNET | FF | 1 | u_test1/next_state.READ_BURST_s13/I3 |
4.953 | 0.464 | tINS | FF | 3 | u_test1/next_state.READ_BURST_s13/F |
5.308 | 0.356 | tNET | FF | 1 | u_test1/next_state.CYC_DONE_WAITE_s12/I0 |
6.073 | 0.765 | tINS | FF | 1 | u_test1/next_state.CYC_DONE_WAITE_s12/F |
6.429 | 0.356 | tNET | FF | 1 | u_test1/curr_state.CYC_DONE_WAITE_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_test1/curr_state.CYC_DONE_WAITE_s0/CLK |
12.742 | -0.296 | tSu | 1 | u_test1/curr_state.CYC_DONE_WAITE_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 12.500 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Arrival Data Path Delay: | cell: 3.417, 58.005%; route: 2.134, 36.229%; tC2Q: 0.340, 5.766% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 4
Path Summary:Slack | 6.313 |
Data Arrival Time | 6.429 |
Data Required Time | 12.742 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0 |
To | u_test1/curr_state.CMD_WAITE_s0 |
Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
0.269 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
0.538 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 24 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/Q |
1.234 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/I1 |
2.048 | 0.814 | tINS | FF | 7 | u_PSRAM_TOP/u_psram_top1/cmd_rdy1_d_s/F |
2.404 | 0.356 | tNET | FF | 1 | u_test1/next_state.CYC_DONE_s14/I0 |
3.168 | 0.765 | tINS | FF | 1 | u_test1/next_state.CYC_DONE_s14/F |
3.524 | 0.356 | tNET | FF | 1 | u_test1/next_state.CYC_DONE_s12/I2 |
4.133 | 0.609 | tINS | FF | 3 | u_test1/next_state.CYC_DONE_s12/F |
4.489 | 0.356 | tNET | FF | 1 | u_test1/next_state.IDLE_s14/I3 |
4.953 | 0.464 | tINS | FF | 2 | u_test1/next_state.IDLE_s14/F |
5.308 | 0.356 | tNET | FF | 1 | u_test1/next_state.CMD_WAITE_s11/I0 |
6.073 | 0.765 | tINS | FF | 1 | u_test1/next_state.CMD_WAITE_s11/F |
6.429 | 0.356 | tNET | FF | 1 | u_test1/curr_state.CMD_WAITE_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_test1/curr_state.CMD_WAITE_s0/CLK |
12.742 | -0.296 | tSu | 1 | u_test1/curr_state.CMD_WAITE_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 12.500 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Arrival Data Path Delay: | cell: 3.417, 58.005%; route: 2.134, 36.229%; tC2Q: 0.340, 5.766% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 5
Path Summary:Slack | 6.313 |
Data Arrival Time | 6.429 |
Data Required Time | 12.742 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0 |
To | u_test0/curr_state.CYC_DONE_WAITE_s0 |
Launch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
0.269 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
0.538 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/CLK |
0.878 | 0.340 | tC2Q | RF | 24 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/c_state.IDLE_s0/Q |
1.234 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/I1 |
2.048 | 0.814 | tINS | FF | 7 | u_PSRAM_TOP/u_psram_top0/cmd_rdy0_d_s/F |
2.404 | 0.356 | tNET | FF | 1 | u_test0/next_state.CYC_DONE_s14/I0 |
3.168 | 0.765 | tINS | FF | 1 | u_test0/next_state.CYC_DONE_s14/F |
3.524 | 0.356 | tNET | FF | 1 | u_test0/next_state.CYC_DONE_s12/I2 |
4.133 | 0.609 | tINS | FF | 3 | u_test0/next_state.CYC_DONE_s12/F |
4.489 | 0.356 | tNET | FF | 1 | u_test0/next_state.READ_BURST_s13/I3 |
4.953 | 0.464 | tINS | FF | 3 | u_test0/next_state.READ_BURST_s13/F |
5.308 | 0.356 | tNET | FF | 1 | u_test0/next_state.CYC_DONE_WAITE_s12/I0 |
6.073 | 0.765 | tINS | FF | 1 | u_test0/next_state.CYC_DONE_WAITE_s12/F |
6.429 | 0.356 | tNET | FF | 1 | u_test0/curr_state.CYC_DONE_WAITE_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1907 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_test0/curr_state.CYC_DONE_WAITE_s0/CLK |
12.742 | -0.296 | tSu | 1 | u_test0/curr_state.CYC_DONE_WAITE_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 12.500 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Arrival Data Path Delay: | cell: 3.417, 58.005%; route: 2.134, 36.229%; tC2Q: 0.340, 5.766% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |