Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\apsram_syn_top.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\apsram_test.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\gowin_rpll\gowin_rpll.v E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\uhs_psram_memory_interface_2ch\uhs_psram_memory_interface_2ch.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW1NR-LV9MG100PAC7/I6 |
Device | GW1NR-9C |
Created Time | Tue Mar 09 17:33:37 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | psram_syn_top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.783s, Peak memory usage = 286.145MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 286.145MB Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 286.145MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 286.145MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 286.145MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 286.145MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 286.145MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 286.145MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 286.145MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 286.145MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 286.145MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 286.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.34s, Peak memory usage = 286.145MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 286.145MB |
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 286.145MB |
Resource
Resource Usage Summary
I/O Port | 8 |
Emedded Port | 52 |
I/O Buf | 56 |
    IBUF | 2 |
    OBUF | 10 |
    TBUF | 4 |
    IOBUF | 36 |
    ELVDS_OBUF | 4 |
Register | 1875 |
    DFF | 1 |
    DFFP | 12 |
    DFFPE | 12 |
    DFFC | 912 |
    DFFCE | 938 |
LUT | 2860 |
    LUT2 | 607 |
    LUT3 | 936 |
    LUT4 | 1317 |
ALU | 266 |
    ALU | 266 |
SSRAM | 36 |
    RAM16S4 | 36 |
INV | 29 |
    INV | 29 |
IOLOGIC | 120 |
    IDES4 | 32 |
    OSER4 | 48 |
    IODELAY | 40 |
CLOCK | 4 |
    DLL | 1 |
    CLKDIV | 1 |
    DHCEN | 1 |
    rPLL | 1 |
Resource Utilization Summary
Logic | 3371(2889 LUTs, 266 ALUs, 36 SSRAMs) / 8640 | 39% |
Register | 1875 / 6900 | 27% |
  --Register as Latch | 0 / 6900 | 0% |
  --Register as FF | 1875 / 6900 | 27% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
your_instance_name/rpll_inst/CLKOUT.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUT |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.0 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.3 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | your_instance_name/rpll_inst/CLKOUT | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | u_PSRAM_TOP/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.0(MHz) | 176.3(MHz) | 5 | TOP |
2 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | 80.0(MHz) | 287.3(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 0.373 |
Data Arrival Time | 41.692 |
Data Required Time | 42.065 |
From | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0 |
To | u_PSRAM_TOP/u_dhcen_clk_x2 |
Launch Clk | clk[F] |
Latch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.000 | 0.000 | clk | |||
40.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
40.728 | 0.728 | tINS | RR | 65 | clk_ibuf/O |
40.997 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK |
41.336 | 0.340 | tC2Q | RF | 7 | u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q |
41.692 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_dhcen_clk_x2/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
40.625 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
41.927 | 1.302 | tCL | FF | 1 | your_instance_name/rpll_inst/CLKOUT |
42.283 | 0.356 | tNET | FF | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
42.253 | -0.030 | tUnc | u_PSRAM_TOP/u_dhcen_clk_x2 | ||
42.065 | -0.188 | tSu | 1 | u_PSRAM_TOP/u_dhcen_clk_x2 |
Clock Skew: | 0.662 |
Setup Relationship: | 0.625 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.356, 100.000% |
Path 2
Path Summary:Slack | 1.020 |
Data Arrival Time | 61.692 |
Data Required Time | 62.712 |
From | u_PSRAM_TOP/u_psram_sync/cs_memsync_0_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_init/ready_d_0_s0 |
Launch Clk | clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
60.000 | 0.000 | clk | |||
60.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
60.728 | 0.728 | tINS | RR | 65 | clk_ibuf/O |
60.997 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_sync/cs_memsync_0_s0/CLK |
61.336 | 0.340 | tC2Q | RF | 7 | u_PSRAM_TOP/u_psram_sync/cs_memsync_0_s0/Q |
61.692 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_init/ready_d_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
62.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
62.769 | 0.269 | tCL | RR | 1927 | u_PSRAM_TOP/clkdiv/CLKOUT |
63.038 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_init/ready_d_0_s0/CLK |
63.008 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_init/ready_d_0_s0 | ||
62.712 | -0.296 | tSu | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_init/ready_d_0_s0 |
Clock Skew: | -0.458 |
Setup Relationship: | 2.500 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 3
Path Summary:Slack | 1.067 |
Data Arrival Time | 11.645 |
Data Required Time | 12.712 |
From | u_PSRAM_TOP/u_dll |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 |
Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
7.821 | 0.269 | tNET | RR | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
8.005 | 0.184 | tINS | RR | 82 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
8.274 | 0.269 | tNET | RR | 8 | u_PSRAM_TOP/u_dll/CLKIN |
8.694 | 0.420 | tINS | RF | 2 | u_PSRAM_TOP/u_dll/STEP[0] |
9.050 | 0.356 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s19/I1 |
9.824 | 0.774 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s19/COUT |
9.824 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s20/CIN |
9.866 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s20/COUT |
9.866 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s21/CIN |
9.908 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s21/COUT |
9.908 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s22/CIN |
9.951 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s22/COUT |
9.951 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s23/CIN |
9.993 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s23/COUT |
9.993 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s24/CIN |
10.035 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s24/COUT |
10.035 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s25/CIN |
10.077 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s25/COUT |
10.077 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s26/CIN |
10.120 | 0.042 | tINS | FF | 2 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n379_s26/COUT |
10.475 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n389_s3/I1 |
11.290 | 0.814 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/n389_s3/F |
11.645 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1927 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1/CLK |
13.008 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 | ||
12.712 | -0.296 | tSu | 1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/step_0_s1 |
Clock Skew: | -1.217 |
Setup Relationship: | 6.250 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
Arrival Data Path Delay: | cell: 2.304, 63.296%; route: 1.067, 29.314%; tC2Q: 0.269, 7.390% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 4
Path Summary:Slack | 1.272 |
Data Arrival Time | 11.440 |
Data Required Time | 12.712 |
From | u_PSRAM_TOP/u_dll |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 |
Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
7.821 | 0.269 | tNET | RR | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
8.005 | 0.184 | tINS | RR | 82 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
8.274 | 0.269 | tNET | RR | 8 | u_PSRAM_TOP/u_dll/CLKIN |
8.694 | 0.420 | tINS | RF | 2 | u_PSRAM_TOP/u_dll/STEP[0] |
9.050 | 0.356 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s19/I1 |
9.824 | 0.774 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s19/COUT |
9.824 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s20/CIN |
9.866 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s20/COUT |
9.866 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s21/CIN |
9.908 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s21/COUT |
9.908 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s22/CIN |
9.951 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s22/COUT |
9.951 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s23/CIN |
9.993 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s23/COUT |
9.993 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s24/CIN |
10.035 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s24/COUT |
10.035 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s25/CIN |
10.077 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s25/COUT |
10.077 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s26/CIN |
10.120 | 0.042 | tINS | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s26/COUT |
10.475 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n389_s3/I2 |
11.084 | 0.609 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n389_s3/F |
11.440 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1927 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1/CLK |
13.008 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 | ||
12.712 | -0.296 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_0_s1 |
Clock Skew: | -1.217 |
Setup Relationship: | 6.250 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
Arrival Data Path Delay: | cell: 2.099, 61.102%; route: 1.067, 31.066%; tC2Q: 0.269, 7.831% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |
Path 5
Path Summary:Slack | 1.446 |
Data Arrival Time | 11.530 |
Data Required Time | 12.976 |
From | u_PSRAM_TOP/u_dll |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_1_s0 |
Launch Clk | your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R] |
Latch Clk | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
6.250 | 0.000 | your_instance_name/rpll_inst/CLKOUT.default_gen_clk | |||
7.552 | 1.302 | tCL | RR | 1 | your_instance_name/rpll_inst/CLKOUT |
7.821 | 0.269 | tNET | RR | 3 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
8.005 | 0.184 | tINS | RR | 82 | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
8.274 | 0.269 | tNET | RR | 8 | u_PSRAM_TOP/u_dll/CLKIN |
8.694 | 0.420 | tINS | RF | 2 | u_PSRAM_TOP/u_dll/STEP[0] |
9.050 | 0.356 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s19/I1 |
9.824 | 0.774 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s19/COUT |
9.824 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s20/CIN |
9.866 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s20/COUT |
9.866 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s21/CIN |
9.908 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s21/COUT |
9.908 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s22/CIN |
9.951 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s22/COUT |
9.951 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s23/CIN |
9.993 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s23/COUT |
9.993 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s24/CIN |
10.035 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s24/COUT |
10.035 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s25/CIN |
10.077 | 0.042 | tINS | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s25/COUT |
10.077 | 0.000 | tNET | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s26/CIN |
10.120 | 0.042 | tINS | FF | 2 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n379_s26/COUT |
10.475 | 0.356 | tNET | FF | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n455_s1/I1 |
11.262 | 0.786 | tINS | FR | 8 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/n455_s1/F |
11.531 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_1_s0/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
12.500 | 0.000 | u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk | |||
12.769 | 0.269 | tCL | RR | 1927 | u_PSRAM_TOP/clkdiv/CLKOUT |
13.038 | 0.269 | tNET | RR | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_1_s0/CLK |
13.008 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_1_s0 | ||
12.976 | -0.032 | tSu | 1 | u_PSRAM_TOP/u_psram_top1/u_psram_wd/step_1_s0 |
Clock Skew: | -1.217 |
Setup Relationship: | 6.250 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.184, 40.607%; route: 0.269, 59.393% |
Arrival Data Path Delay: | cell: 2.276, 64.559%; route: 0.980, 27.810%; tC2Q: 0.269, 7.630% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.269, 100.000% |