Report Title |
Gowin Power Analysis Report |
Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project_1.vg |
Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\ap.cst |
Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_double_2ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
GOWIN Version |
V1.9.7.02Beta |
Part Number |
GW1NR-LV9MG100PAC7/I6 |
Device |
GW1NR-9C |
Created Time |
Tue Mar 09 17:15:00 2021
|
Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
67.526 |
Quiescent Power (mW) |
5.020 |
Dynamic Power (mW) |
62.506 |
Psram Power (mW) |
172.000 |
Junction Temperature |
25.704 |
Theta JA |
10.500 |
Max Allowed Ambient Temperature |
84.296 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.200 |
48.877 |
2.627 |
61.805 |
VCCX |
2.500 |
0.898 |
0.436 |
3.334 |
VCCO18 |
1.800 |
0.894 |
0.432 |
2.387 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
9.749 |
NA |
8.664 |
IO |
7.463
| 2.391
| 17.375
|
PLL |
3.720
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
psram_syn_top |
57.484 |
13.470(13.470) |
44.015(43.985) |
psram_syn_top/u_PSRAM_TOP/ |
34.723 |
5.570(5.569) |
29.153(29.103) |
psram_syn_top/u_PSRAM_TOP/u_psram_sync/ |
0.515 |
0.077(0.000) |
0.438(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/ |
17.576 |
2.753(2.313) |
14.823(13.237) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_init/ |
7.566 |
1.332(0.000) |
6.234(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/ |
7.984 |
0.981(0.975) |
7.003(6.899) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
5.021 |
0.581(0.000) |
4.440(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
2.853 |
0.394(0.000) |
2.459(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/ |
16.581 |
2.739(2.299) |
13.842(12.286) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_init/ |
7.215 |
1.321(0.000) |
5.894(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/ |
7.370 |
0.978(0.972) |
6.392(6.303) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
4.464 |
0.580(0.000) |
3.884(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
2.811 |
0.392(0.000) |
2.419(0.000) |
psram_syn_top/u_test0/ |
9.374 |
2.090(0.000) |
7.285(0.000) |
psram_syn_top/u_test1/ |
9.424 |
2.090(0.000) |
7.334(0.000) |
psram_syn_top/your_instance_name/ |
3.934 |
3.720(0.000) |
0.213(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
clk_x1 |
69.999 |
52.945 |
clk_d |
35.001 |
0.546 |
NO CLOCK DOMAIN |
0.000 |
0.000 |
clk |
50.000 |
3.751 |
your_instance_name/rpll_inst/CLKOUT.default_gen_clk |
160.000 |
0.096 |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk |
160.000 |
0.096 |