Timing Messages
Report Title | Gowin Timing Analysis Report |
Design File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project_1.vg |
Physical Constraints File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\ap.cst |
Timing Constraint File | E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
GOWIN version | V1.9.7.02Beta |
Part Number | GW1NR-LV9MG100PAC7/I6 |
Device | GW1NR-9C |
Created Time | Tue Mar 09 17:33:45 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C |
Hold Delay Model | Fast 1.26V 0C |
Numbers of Paths Analyzed | 5523 |
Numbers of Endpoints Analyzed | 5480 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
clk_x1 | Base | 14.286 | 69.999 | 0.000 | 7.143 | clk_x1 | ||
clk_x2 | Base | 7.143 | 139.997 | 0.000 | 3.571 | memory_clk | ||
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Generated | 6.250 | 160.000 | 0.000 | 3.125 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTP |
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Generated | 12.500 | 80.000 | 0.000 | 6.250 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 18.750 | 53.333 | 0.000 | 9.375 | clk_ibuf/I | clk | your_instance_name/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 118.184(MHz) | 5 | TOP |
2 | clk_x1 | 69.999(MHz) | 99.603(MHz) | 5 | TOP |
No timing paths to get frequency of clk_x2!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
clk_x1 | Setup | 0.000 | 0 |
clk_x1 | Hold | 0.000 | 0 |
clk_x2 | Setup | 0.000 | 0 |
clk_x2 | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 4.094 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 3.125 |
2 | 4.094 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 3.125 |
3 | 4.097 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 3.122 |
4 | 4.097 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 3.122 |
5 | 4.246 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_1_s1/CE | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 10.008 |
6 | 4.494 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_8_s1/CE | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 9.760 |
7 | 4.578 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.641 |
8 | 4.578 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.641 |
9 | 4.580 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.639 |
10 | 4.581 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.638 |
11 | 4.581 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.638 |
12 | 4.593 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.626 |
13 | 4.701 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.519 |
14 | 4.701 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.519 |
15 | 4.701 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.518 |
16 | 4.724 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.495 |
17 | 4.811 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.408 |
18 | 4.811 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.408 |
19 | 4.823 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.396 |
20 | 4.823 | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.396 |
21 | 4.824 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.395 |
22 | 4.886 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_28_s1/CE | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 9.368 |
23 | 5.013 | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.WRITE_DATA_s0/D | clk_x1:[R] | clk_x1:[R] | 14.286 | 0.000 | 8.977 |
24 | 5.053 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.166 |
25 | 5.053 | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB | clk_x1:[R] | clk_x2:[R] | 7.143 | -0.106 | 2.166 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.412 | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CE | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.423 |
2 | 0.412 | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.423 |
3 | 0.524 | u_test1/cyc_cnt_1_s3/Q | u_test1/cyc_cnt_1_s3/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
4 | 0.524 | u_test1/WR_CNT_3_s3/Q | u_test1/WR_CNT_3_s3/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
5 | 0.524 | u_test1/check_data_31_s1/Q | u_test1/check_data_31_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
6 | 0.524 | u_test1/wr_data_add_19_s1/Q | u_test1/wr_data_add_19_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
7 | 0.524 | u_test1/wr_data_add_28_s1/Q | u_test1/wr_data_add_28_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
8 | 0.524 | u_test1/wr_data_add_63_s1/Q | u_test1/wr_data_add_63_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
9 | 0.524 | u_test1/curr_state.IDLE_s0/Q | u_test1/curr_state.IDLE_s0/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
10 | 0.524 | u_test0/check_data_8_s1/Q | u_test0/check_data_8_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
11 | 0.524 | u_test0/check_data_9_s1/Q | u_test0/check_data_9_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
12 | 0.524 | u_test0/check_data_17_s1/Q | u_test0/check_data_17_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
13 | 0.524 | u_test0/wr_data_add_26_s1/Q | u_test0/wr_data_add_26_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
14 | 0.524 | u_test0/wr_data_add_31_s1/Q | u_test0/wr_data_add_31_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
15 | 0.524 | u_test0/wr_data_add_36_s1/Q | u_test0/wr_data_add_36_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
16 | 0.524 | u_test0/wr_data_add_52_s1/Q | u_test0/wr_data_add_52_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
17 | 0.524 | u_test0/curr_state.CYC_DONE_s0/Q | u_test0/curr_state.CYC_DONE_s0/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
18 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
19 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
20 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
21 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
22 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
23 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
24 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
25 | 0.524 | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/Q | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/D | clk_x1:[R] | clk_x1:[R] | 0.000 | 0.000 | 0.524 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0 |
2 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0 |
3 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_16_s0 |
4 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_8_s0 |
5 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_4_s0 |
6 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_2_s0 |
7 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/rd_data_d_1_s0 |
8 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_valid_2_s0 |
9 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_cnt_7_s1 |
10 | 6.159 | 7.085 | 0.926 | Low Pulse Width | clk_x1 | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_2_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 4.094 |
Data Arrival Time | 3.306 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.306 | 2.786 | tNET | FF | 1 | IOR26[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR26[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR26[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.786, 89.133%; tC2Q: 0.340, 10.867% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path2
Path Summary:
Slack | 4.094 |
Data Arrival Time | 3.306 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.306 | 2.786 | tNET | FF | 1 | IOR26[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR26[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR26[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.786, 89.133%; tC2Q: 0.340, 10.867% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path3
Path Summary:
Slack | 4.097 |
Data Arrival Time | 3.303 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.303 | 2.782 | tNET | FF | 1 | IOR25[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR25[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR25[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.782, 89.121%; tC2Q: 0.340, 10.879% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path4
Path Summary:
Slack | 4.097 |
Data Arrival Time | 3.303 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
3.303 | 2.782 | tNET | FF | 1 | IOR27[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR27[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR27[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.782, 89.121%; tC2Q: 0.340, 10.879% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path5
Path Summary:
Slack | 4.246 |
Data Arrival Time | 10.188 |
Data Required Time | 14.435 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_1_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/CLK |
0.520 | 0.340 | tC2Q | RF | 7 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q |
1.738 | 1.217 | tNET | FF | 1 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/I0 |
2.502 | 0.765 | tINS | FF | 33 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/F |
2.897 | 0.394 | tNET | FF | 1 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/I2 |
3.711 | 0.814 | tINS | FF | 8 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/F |
4.457 | 0.746 | tNET | FF | 1 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/I1 |
5.222 | 0.765 | tINS | FF | 36 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/F |
8.027 | 2.805 | tNET | FF | 1 | R7C26[3][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2467_s0/I2 |
8.813 | 0.786 | tINS | FR | 1 | R7C26[3][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2467_s0/F |
10.188 | 1.375 | tNET | RR | 1 | R7C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R7C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_1_s1/CLK |
14.435 | -0.032 | tSu | 1 | R7C26[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.130, 31.276%; route: 6.538, 65.331%; tC2Q: 0.340, 3.394% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path6
Path Summary:
Slack | 4.494 |
Data Arrival Time | 9.941 |
Data Required Time | 14.435 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_8_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/CLK |
0.520 | 0.340 | tC2Q | RF | 7 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q |
1.738 | 1.217 | tNET | FF | 1 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/I0 |
2.502 | 0.765 | tINS | FF | 33 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/F |
2.897 | 0.394 | tNET | FF | 1 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/I2 |
3.711 | 0.814 | tINS | FF | 8 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/F |
4.457 | 0.746 | tNET | FF | 1 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/I1 |
5.222 | 0.765 | tINS | FF | 36 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/F |
8.027 | 2.805 | tNET | FF | 1 | R7C26[0][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2460_s0/I2 |
8.813 | 0.786 | tINS | FR | 1 | R7C26[0][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2460_s0/F |
9.941 | 1.128 | tNET | RR | 1 | R7C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_8_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R7C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_8_s1/CLK |
14.435 | -0.032 | tSu | 1 | R7C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.130, 32.070%; route: 6.290, 64.451%; tC2Q: 0.340, 3.480% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path7
Path Summary:
Slack | 4.578 |
Data Arrival Time | 2.822 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.822 | 2.301 | tNET | FF | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR18[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.301, 87.139%; tC2Q: 0.340, 12.861% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path8
Path Summary:
Slack | 4.578 |
Data Arrival Time | 2.822 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.822 | 2.301 | tNET | FF | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR21[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.301, 87.139%; tC2Q: 0.340, 12.861% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path9
Path Summary:
Slack | 4.580 |
Data Arrival Time | 2.820 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.820 | 2.300 | tNET | FF | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR3[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.300, 87.132%; tC2Q: 0.340, 12.868% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path10
Path Summary:
Slack | 4.581 |
Data Arrival Time | 2.819 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.819 | 2.299 | tNET | FF | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR6[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.299, 87.126%; tC2Q: 0.340, 12.874% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path11
Path Summary:
Slack | 4.581 |
Data Arrival Time | 2.819 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.819 | 2.299 | tNET | FF | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR6[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.299, 87.126%; tC2Q: 0.340, 12.874% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path12
Path Summary:
Slack | 4.593 |
Data Arrival Time | 2.806 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.806 | 2.286 | tNET | FF | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL27[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.286, 87.065%; tC2Q: 0.340, 12.935% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path13
Path Summary:
Slack | 4.701 |
Data Arrival Time | 2.699 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.699 | 2.179 | tNET | FF | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR20[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 86.515%; tC2Q: 0.340, 13.485% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path14
Path Summary:
Slack | 4.701 |
Data Arrival Time | 2.699 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[2][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q |
2.699 | 2.179 | tNET | FF | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR20[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.179, 86.515%; tC2Q: 0.340, 13.485% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path15
Path Summary:
Slack | 4.701 |
Data Arrival Time | 2.698 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.698 | 2.178 | tNET | FF | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR4[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.178, 86.510%; tC2Q: 0.340, 13.490% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path16
Path Summary:
Slack | 4.724 |
Data Arrival Time | 2.675 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.675 | 2.155 | tNET | FF | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL25[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.155, 86.386%; tC2Q: 0.340, 13.614% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path17
Path Summary:
Slack | 4.811 |
Data Arrival Time | 2.588 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.588 | 2.068 | tNET | FF | 1 | IOL20[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL20[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL20[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.068, 85.894%; tC2Q: 0.340, 14.106% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path18
Path Summary:
Slack | 4.811 |
Data Arrival Time | 2.588 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.588 | 2.068 | tNET | FF | 1 | IOL20[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL20[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL20[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.068, 85.894%; tC2Q: 0.340, 14.106% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path19
Path Summary:
Slack | 4.823 |
Data Arrival Time | 2.577 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.577 | 2.056 | tNET | FF | 1 | IOL26[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL26[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL26[B] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.056, 85.826%; tC2Q: 0.340, 14.174% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path20
Path Summary:
Slack | 4.823 |
Data Arrival Time | 2.577 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R14C12[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/calib_1_s0/Q |
2.577 | 2.056 | tNET | FF | 1 | IOL26[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOL26[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOL26[A] | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.056, 85.826%; tC2Q: 0.340, 14.174% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path21
Path Summary:
Slack | 4.824 |
Data Arrival Time | 2.576 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.576 | 2.055 | tNET | FF | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR14[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.055, 85.820%; tC2Q: 0.340, 14.180% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path22
Path Summary:
Slack | 4.886 |
Data Arrival Time | 9.549 |
Data Required Time | 14.435 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_28_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/CLK |
0.520 | 0.340 | tC2Q | RF | 7 | R13C26[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].wr_ptr_1_s1/Q |
1.738 | 1.217 | tNET | FF | 1 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/I0 |
2.502 | 0.765 | tINS | FF | 33 | R7C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s2/F |
2.897 | 0.394 | tNET | FF | 1 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/I2 |
3.711 | 0.814 | tINS | FF | 8 | R5C24[3][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2404_s0/F |
4.457 | 0.746 | tNET | FF | 1 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/I1 |
5.222 | 0.765 | tINS | FF | 36 | R7C22[1][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n3118_s4/F |
7.661 | 2.440 | tNET | FF | 1 | R7C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2440_s0/I2 |
8.421 | 0.760 | tINS | FR | 1 | R7C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n2440_s0/F |
9.549 | 1.128 | tNET | RR | 1 | R7C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_28_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R7C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_28_s1/CLK |
14.435 | -0.032 | tSu | 1 | R7C28[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_28_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 3.104, 33.134%; route: 5.925, 63.241%; tC2Q: 0.340, 3.625% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path23
Path Summary:
Slack | 5.013 |
Data Arrival Time | 9.158 |
Data Required Time | 14.170 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.WRITE_DATA_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R9C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 149 | R9C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q |
2.471 | 1.951 | tNET | FF | 1 | R12C27[1][A] | u_PSRAM_TOP/u_psram_top1/cmd_en_d_s0/I2 |
3.286 | 0.814 | tINS | FF | 40 | R12C27[1][A] | u_PSRAM_TOP/u_psram_top1/cmd_en_d_s0/F |
6.672 | 3.386 | tNET | FF | 1 | R18C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n_state.IDLE_s16/I0 |
7.486 | 0.814 | tINS | FF | 5 | R18C27[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n_state.IDLE_s16/F |
8.343 | 0.857 | tNET | FF | 1 | R22C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n_state.WRITE_DATA_s15/I0 |
9.158 | 0.814 | tINS | FF | 1 | R22C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/n_state.WRITE_DATA_s15/F |
9.158 | 0.000 | tNET | FF | 1 | R22C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.WRITE_DATA_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
14.286 | 14.286 | active clock edge time | ||||
14.286 | 0.000 | clk_x1 | ||||
14.286 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
14.467 | 0.181 | tNET | RR | 1 | R22C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.WRITE_DATA_s0/CLK |
14.170 | -0.296 | tSu | 1 | R22C28[2][B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/c_state.WRITE_DATA_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 14.286 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 2.443, 27.215%; route: 6.194, 69.001%; tC2Q: 0.340, 3.783% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Path24
Path Summary:
Slack | 5.053 |
Data Arrival Time | 2.347 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.347 | 1.827 | tNET | FF | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR13[A] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.827, 84.322%; tC2Q: 0.340, 15.678% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Path25
Path Summary:
Slack | 5.053 |
Data Arrival Time | 2.347 |
Data Required Time | 7.400 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x2:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.181 | 0.181 | tNET | RR | 1 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/CLK |
0.520 | 0.340 | tC2Q | RF | 11 | R11C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_0_s0/Q |
2.347 | 1.827 | tNET | FF | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
7.143 | 7.143 | active clock edge time | ||||
7.143 | 0.000 | clk_x2 | ||||
7.143 | 0.000 | tCL | RR | 1 | PLL_R | your_instance_name/rpll_inst/CLKOUT |
7.143 | 0.000 | tNET | RR | 3 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN |
7.327 | 0.184 | tINS | RR | 82 | - | u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT |
7.430 | 0.103 | tNET | RR | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK |
7.400 | -0.030 | tUnc | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 | |||
7.400 | 0.000 | tSu | 1 | IOR13[B] | u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4 |
Path Statistics:
Clock Skew | 0.106 |
Setup Relationship | 7.143 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.181, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.827, 84.322%; tC2Q: 0.340, 15.678% |
Required Clock Path Delay | cell: 0.184, 64.110%; route: 0.103, 35.890% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.412 |
Data Arrival Time | 0.560 |
Data Required Time | 0.148 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C18[0][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R9C18[0][B] | u_PSRAM_TOP/u_psram_top1/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q |
0.560 | 0.176 | tNET | RR | 1 | R9C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK |
0.148 | 0.011 | tHld | 1 | R9C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path2
Path Summary:
Slack | 0.412 |
Data Arrival Time | 0.560 |
Data Required Time | 0.148 |
From | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0 |
To | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C15[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R15C15[0][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q |
0.560 | 0.176 | tNET | RR | 1 | R15C15[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C15[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK |
0.148 | 0.011 | tHld | 1 | R15C15[1][A] | u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path3
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/cyc_cnt_1_s3 |
To | u_test1/cyc_cnt_1_s3 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C41[1][A] | u_test1/cyc_cnt_1_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R12C41[1][A] | u_test1/cyc_cnt_1_s3/Q |
0.386 | 0.002 | tNET | RR | 1 | R12C41[1][A] | u_test1/n1427_s3/I2 |
0.661 | 0.276 | tINS | RF | 1 | R12C41[1][A] | u_test1/n1427_s3/F |
0.661 | 0.000 | tNET | FF | 1 | R12C41[1][A] | u_test1/cyc_cnt_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C41[1][A] | u_test1/cyc_cnt_1_s3/CLK |
0.137 | 0.000 | tHld | 1 | R12C41[1][A] | u_test1/cyc_cnt_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path4
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/WR_CNT_3_s3 |
To | u_test1/WR_CNT_3_s3 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C30[1][A] | u_test1/WR_CNT_3_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R9C30[1][A] | u_test1/WR_CNT_3_s3/Q |
0.386 | 0.002 | tNET | RR | 1 | R9C30[1][A] | u_test1/n153_s4/I2 |
0.661 | 0.276 | tINS | RF | 1 | R9C30[1][A] | u_test1/n153_s4/F |
0.661 | 0.000 | tNET | FF | 1 | R9C30[1][A] | u_test1/WR_CNT_3_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C30[1][A] | u_test1/WR_CNT_3_s3/CLK |
0.137 | 0.000 | tHld | 1 | R9C30[1][A] | u_test1/WR_CNT_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path5
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/check_data_31_s1 |
To | u_test1/check_data_31_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R14C34[1][A] | u_test1/check_data_31_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R14C34[1][A] | u_test1/check_data_31_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R14C34[1][A] | u_test1/n1566_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R14C34[1][A] | u_test1/n1566_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R14C34[1][A] | u_test1/check_data_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R14C34[1][A] | u_test1/check_data_31_s1/CLK |
0.137 | 0.000 | tHld | 1 | R14C34[1][A] | u_test1/check_data_31_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path6
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/wr_data_add_19_s1 |
To | u_test1/wr_data_add_19_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C35[0][A] | u_test1/wr_data_add_19_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R9C35[0][A] | u_test1/wr_data_add_19_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R9C35[0][A] | u_test1/n695_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R9C35[0][A] | u_test1/n695_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R9C35[0][A] | u_test1/wr_data_add_19_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C35[0][A] | u_test1/wr_data_add_19_s1/CLK |
0.137 | 0.000 | tHld | 1 | R9C35[0][A] | u_test1/wr_data_add_19_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path7
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/wr_data_add_28_s1 |
To | u_test1/wr_data_add_28_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R8C36[0][A] | u_test1/wr_data_add_28_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R8C36[0][A] | u_test1/wr_data_add_28_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R8C36[0][A] | u_test1/n686_s6/I0 |
0.661 | 0.276 | tINS | RF | 1 | R8C36[0][A] | u_test1/n686_s6/F |
0.661 | 0.000 | tNET | FF | 1 | R8C36[0][A] | u_test1/wr_data_add_28_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R8C36[0][A] | u_test1/wr_data_add_28_s1/CLK |
0.137 | 0.000 | tHld | 1 | R8C36[0][A] | u_test1/wr_data_add_28_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path8
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/wr_data_add_63_s1 |
To | u_test1/wr_data_add_63_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C32[0][A] | u_test1/wr_data_add_63_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R9C32[0][A] | u_test1/wr_data_add_63_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R9C32[0][A] | u_test1/n651_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R9C32[0][A] | u_test1/n651_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R9C32[0][A] | u_test1/wr_data_add_63_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C32[0][A] | u_test1/wr_data_add_63_s1/CLK |
0.137 | 0.000 | tHld | 1 | R9C32[0][A] | u_test1/wr_data_add_63_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path9
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test1/curr_state.IDLE_s0 |
To | u_test1/curr_state.IDLE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R6C37[0][A] | u_test1/curr_state.IDLE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 42 | R6C37[0][A] | u_test1/curr_state.IDLE_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R6C37[0][A] | u_test1/next_state.IDLE_s12/I1 |
0.661 | 0.276 | tINS | RF | 1 | R6C37[0][A] | u_test1/next_state.IDLE_s12/F |
0.661 | 0.000 | tNET | FF | 1 | R6C37[0][A] | u_test1/curr_state.IDLE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R6C37[0][A] | u_test1/curr_state.IDLE_s0/CLK |
0.137 | 0.000 | tHld | 1 | R6C37[0][A] | u_test1/curr_state.IDLE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path10
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/check_data_8_s1 |
To | u_test0/check_data_8_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C42[0][A] | u_test0/check_data_8_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R22C42[0][A] | u_test0/check_data_8_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R22C42[0][A] | u_test0/n1589_s4/I1 |
0.661 | 0.276 | tINS | RF | 1 | R22C42[0][A] | u_test0/n1589_s4/F |
0.661 | 0.000 | tNET | FF | 1 | R22C42[0][A] | u_test0/check_data_8_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C42[0][A] | u_test0/check_data_8_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C42[0][A] | u_test0/check_data_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path11
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/check_data_9_s1 |
To | u_test0/check_data_9_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C42[0][A] | u_test0/check_data_9_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R21C42[0][A] | u_test0/check_data_9_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R21C42[0][A] | u_test0/n1588_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R21C42[0][A] | u_test0/n1588_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R21C42[0][A] | u_test0/check_data_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R21C42[0][A] | u_test0/check_data_9_s1/CLK |
0.137 | 0.000 | tHld | 1 | R21C42[0][A] | u_test0/check_data_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path12
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/check_data_17_s1 |
To | u_test0/check_data_17_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C44[0][A] | u_test0/check_data_17_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R20C44[0][A] | u_test0/check_data_17_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R20C44[0][A] | u_test0/n1580_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R20C44[0][A] | u_test0/n1580_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R20C44[0][A] | u_test0/check_data_17_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R20C44[0][A] | u_test0/check_data_17_s1/CLK |
0.137 | 0.000 | tHld | 1 | R20C44[0][A] | u_test0/check_data_17_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path13
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_26_s1 |
To | u_test0/wr_data_add_26_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C42[1][A] | u_test0/wr_data_add_26_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R18C42[1][A] | u_test0/wr_data_add_26_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R18C42[1][A] | u_test0/n688_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R18C42[1][A] | u_test0/n688_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R18C42[1][A] | u_test0/wr_data_add_26_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C42[1][A] | u_test0/wr_data_add_26_s1/CLK |
0.137 | 0.000 | tHld | 1 | R18C42[1][A] | u_test0/wr_data_add_26_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path14
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_31_s1 |
To | u_test0/wr_data_add_31_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C40[0][A] | u_test0/wr_data_add_31_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R17C40[0][A] | u_test0/wr_data_add_31_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R17C40[0][A] | u_test0/n683_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R17C40[0][A] | u_test0/n683_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R17C40[0][A] | u_test0/wr_data_add_31_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R17C40[0][A] | u_test0/wr_data_add_31_s1/CLK |
0.137 | 0.000 | tHld | 1 | R17C40[0][A] | u_test0/wr_data_add_31_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path15
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_36_s1 |
To | u_test0/wr_data_add_36_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C41[0][A] | u_test0/wr_data_add_36_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R18C41[0][A] | u_test0/wr_data_add_36_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R18C41[0][A] | u_test0/n678_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R18C41[0][A] | u_test0/n678_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R18C41[0][A] | u_test0/wr_data_add_36_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R18C41[0][A] | u_test0/wr_data_add_36_s1/CLK |
0.137 | 0.000 | tHld | 1 | R18C41[0][A] | u_test0/wr_data_add_36_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path16
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/wr_data_add_52_s1 |
To | u_test0/wr_data_add_52_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C36[0][A] | u_test0/wr_data_add_52_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R22C36[0][A] | u_test0/wr_data_add_52_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R22C36[0][A] | u_test0/n662_s1/I2 |
0.661 | 0.276 | tINS | RF | 1 | R22C36[0][A] | u_test0/n662_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R22C36[0][A] | u_test0/wr_data_add_52_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C36[0][A] | u_test0/wr_data_add_52_s1/CLK |
0.137 | 0.000 | tHld | 1 | R22C36[0][A] | u_test0/wr_data_add_52_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path17
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_test0/curr_state.CYC_DONE_s0 |
To | u_test0/curr_state.CYC_DONE_s0 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C31[1][A] | u_test0/curr_state.CYC_DONE_s0/CLK |
0.384 | 0.247 | tC2Q | RR | 35 | R22C31[1][A] | u_test0/curr_state.CYC_DONE_s0/Q |
0.386 | 0.002 | tNET | RR | 1 | R22C31[1][A] | u_test0/next_state.CYC_DONE_s11/I2 |
0.661 | 0.276 | tINS | RF | 1 | R22C31[1][A] | u_test0/next_state.CYC_DONE_s11/F |
0.661 | 0.000 | tNET | FF | 1 | R22C31[1][A] | u_test0/curr_state.CYC_DONE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R22C31[1][A] | u_test0/curr_state.CYC_DONE_s0/CLK |
0.137 | 0.000 | tHld | 1 | R22C31[1][A] | u_test0/curr_state.CYC_DONE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path18
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/CLK |
0.384 | 0.247 | tC2Q | RR | 6 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/Q |
0.386 | 0.002 | tNET | RR | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n546_s4/I0 |
0.661 | 0.276 | tINS | RF | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n546_s4/F |
0.661 | 0.000 | tNET | FF | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3/CLK |
0.137 | 0.000 | tHld | 1 | R12C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path19
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R9C21[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path20
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 3 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1698_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1698_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1/CLK |
0.137 | 0.000 | tHld | 1 | R12C18[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path21
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 6 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1623_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1623_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1/CLK |
0.137 | 0.000 | tHld | 1 | R5C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path22
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 4 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1621_s3/I1 |
0.661 | 0.276 | tINS | RF | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n1621_s3/F |
0.661 | 0.000 | tNET | FF | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R7C23[1][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path23
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 2 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n579_s1/I3 |
0.661 | 0.276 | tINS | RF | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n579_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1/CLK |
0.137 | 0.000 | tHld | 1 | R15C21[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path24
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n544_s2/I2 |
0.661 | 0.276 | tINS | RF | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n544_s2/F |
0.661 | 0.000 | tNET | FF | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1/CLK |
0.137 | 0.000 | tHld | 1 | R14C23[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Path25
Path Summary:
Slack | 0.524 |
Data Arrival Time | 0.661 |
Data Required Time | 0.137 |
From | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
To | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
Launch Clk | clk_x1:[R] |
Latch Clk | clk_x1:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/CLK |
0.384 | 0.247 | tC2Q | RR | 5 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/Q |
0.386 | 0.002 | tNET | RR | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n449_s1/I0 |
0.661 | 0.276 | tINS | RF | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/n449_s1/F |
0.661 | 0.000 | tNET | FF | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_x1 | ||||
0.000 | 0.000 | tCL | RR | 1927 | RIGHTSIDE[0] | u_PSRAM_TOP/clkdiv/CLKOUT |
0.137 | 0.137 | tNET | RR | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1/CLK |
0.137 | 0.000 | tHld | 1 | R5C18[0][A] | u_PSRAM_TOP/u_psram_top1/u_psram_init/tvcs_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.137, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK |
MPW2
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK |
MPW3
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_16_s0/CLK |
MPW4
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_8_s0/CLK |
MPW5
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_4_s0/CLK |
MPW6
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_2_s0/CLK |
MPW7
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/rd_data_d_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/rd_data_d_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/rd_data_d_1_s0/CLK |
MPW8
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_valid_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_valid_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_valid_2_s0/CLK |
MPW9
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_cnt_7_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_cnt_7_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top0/u_psram_init/read_cnt_7_s1/CLK |
MPW10
MPW Summary:
Slack: | 6.159 |
Actual Width: | 7.085 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk_x1 |
Objects: | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
7.143 | 0.000 | active clock edge time | ||
7.143 | 0.000 | clk_x1 | ||
7.143 | 0.000 | tCL | FF | u_PSRAM_TOP/clkdiv/CLKOUT |
7.338 | 0.195 | tNET | FF | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
14.286 | 0.000 | active clock edge time | ||
14.286 | 0.000 | clk_x1 | ||
14.286 | 0.000 | tCL | RR | u_PSRAM_TOP/clkdiv/CLKOUT |
14.423 | 0.137 | tNET | RR | u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_2_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1927 | clk_x1 | 4.094 | 0.195 |
153 | curr_state.WRITE_BURST | 6.074 | 2.199 |
153 | curr_state.WRITE_BURST | 6.929 | 2.967 |
150 | init_calib0_d | 5.188 | 4.272 |
149 | init_calib1_d | 5.013 | 3.856 |
86 | wr_data_63_11 | 6.343 | 2.347 |
86 | wr_data_63_11 | 7.866 | 1.720 |
76 | config_done_Z | 8.884 | 4.302 |
76 | config_done_Z | 9.271 | 2.443 |
74 | wr_data_d0_0_5 | 11.792 | 2.099 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R18C5 | 62.50% |
R15C21 | 61.11% |
R11C39 | 58.33% |
R13C21 | 56.94% |
R8C38 | 55.56% |
R11C40 | 54.17% |
R7C24 | 54.17% |
R9C22 | 54.17% |
R21C9 | 52.78% |
R14C21 | 52.78% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
TC_CLOCK | Actived | create_clock -name clk_x1 -period 14.286 -waveform {0 7.143} [get_nets {clk_x1}] |
TC_CLOCK | Actived | create_clock -name clk_x2 -period 7.143 -waveform {0 3.571} [get_nets {memory_clk}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {clk_x1 clk_x2}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk_x1}] -to [get_clocks {clk clk_x2}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk_x2}] -to [get_clocks {clk_x1 clk}] |