Report Title |
Gowin Power Analysis Report |
Design File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\impl\gwsynthesis\fpga_project_1.vg |
Physical Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\ap.cst |
Timing Constraints File |
E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\apsram_solo_2ch_Refdesign\project\fpga_project\src\fpga_project.sdc |
GOWIN Version |
V1.9.7.02Beta |
Part Number |
GW1NR-LV9MG100PAC7/I6 |
Device |
GW1NR-9C |
Created Time |
Tue Mar 09 17:33:45 2021
|
Legal Announcement |
Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
80.038 |
Quiescent Power (mW) |
5.137 |
Dynamic Power (mW) |
74.901 |
Psram Power (mW) |
172.000 |
Junction Temperature |
25.835 |
Theta JA |
10.500 |
Max Allowed Ambient Temperature |
84.165 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.200 |
59.160 |
2.650 |
74.172 |
VCCX |
2.500 |
0.911 |
0.457 |
3.418 |
VCCO18 |
1.800 |
0.907 |
0.453 |
2.447 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
10.280 |
NA |
8.651 |
IO |
7.620
| 2.505
| 17.133
|
PLL |
4.463
| NA |
NA |
DLL |
8.601
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
psram_syn_top |
69.837 |
23.344(23.229) |
46.493(45.942) |
psram_syn_top/u_PSRAM_TOP/ |
44.849 |
14.568(5.965) |
30.281(29.811) |
psram_syn_top/u_PSRAM_TOP/u_psram_sync/ |
0.661 |
0.115(0.000) |
0.546(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/ |
17.645 |
2.936(2.495) |
14.709(12.977) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_init/ |
7.261 |
1.330(0.000) |
5.931(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/ |
8.211 |
1.165(0.970) |
7.046(6.805) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
4.904 |
0.577(0.000) |
4.327(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
2.871 |
0.392(0.000) |
2.479(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/ |
17.470 |
2.914(2.474) |
14.556(12.905) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_init/ |
7.343 |
1.326(0.000) |
6.017(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/ |
8.035 |
1.147(0.952) |
6.888(6.560) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
4.498 |
0.565(0.000) |
3.933(0.000) |
psram_syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
3.014 |
0.387(0.000) |
2.627(0.000) |
psram_syn_top/u_test0/ |
10.268 |
2.101(0.000) |
8.167(0.000) |
psram_syn_top/u_test1/ |
9.506 |
2.097(0.000) |
7.409(0.000) |
psram_syn_top/your_instance_name/ |
4.547 |
4.463(0.000) |
0.084(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
clk_x1 |
69.999 |
54.847 |
clk |
50.000 |
5.812 |
NO CLOCK DOMAIN |
0.000 |
0.000 |
clk_x2 |
139.997 |
9.127 |