Project Settings
Project Name fpga_project_1 Device Name rev_1: GOWIN-GW1NR : GW1NR_9C
Implementation Name rev_1 Top Module psram_syn_top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 52 90 0 - 00m:03s - 2021/2/22
14:30:25
(premap)Complete 12 10 0 0m:02s 0m:02s 245MB 2021/2/22
14:30:29
(fpga_mapper)Complete 195 50 0 0m:11s 0m:13s 271MB 2021/2/22
14:30:43
Multi-srs Generator Complete2021/2/22
14:30:26

Area Summary
I/O ports (io_port) 34 Non I/O Register bits (non_io_reg) 1389 (21%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 0 (26) Block Multipliers (dsp_used) 0 (10)
LUTs (total_luts) 1722 (19%)

Timing Summary
Clock NameReq FreqEst FreqSlack
_~apsram_init_psram_memory_interface_top_2ch__0|read_calibration[0]_VALUE_derived_clock[0]0.1 MHzNANA
_~apsram_init_psram_memory_interface_top_2ch__1|read_calibration[0]_VALUE_derived_clock[0]0.1 MHzNANA
_~apsram_wd_psram_memory_interface_top_2ch__0|step_derived_clock[0]0.1 MHzNANA
_~apsram_wd_psram_memory_interface_top_2ch__1|step_derived_clock[0]0.1 MHzNANA
psram_memory_interface_top_2ch|clk_out_inferred_clock116.0 MHz98.6 MHz-1.522
psram_memory_interface_top_2ch|clk_x2_inferred_clock100.0 MHzNANA
psram_syn_top|clk_d_inferred_clock168.5 MHz143.2 MHz-1.047
psram_syn_top|memory_clk_inferred_clock178.1 MHz151.4 MHz-0.991
System382.7 MHz325.3 MHz-0.461

Optimizations Summary
Combined Clock Conversion 4 / 4