Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2CH_1\data\APSRAM_TOP.v C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2CH_1\data\apsram_32_code.v |
GowinSynthesis Constraints File | --- |
GowinSynthesis Version | GowinSynthesis V1.9.7.02Beta |
Part Number | GW1NR-LV9MG100PAC7/I6 |
Device | GW1NR-9C |
Created Time | Tue Mar 09 17:17:19 2021 |
Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | UHS_PSRAM_Memory_Interface_2CH_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.125MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 51.125MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.157s, Peak memory usage = 51.125MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s, Peak memory usage = 51.125MB Optimizing Phase 2: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.24s, Peak memory usage = 51.125MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 51.125MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 51.125MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 51.125MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 51.125MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.263s, Peak memory usage = 51.125MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 51.125MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 51.125MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 66.484MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.35s, Peak memory usage = 66.484MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 66.484MB |
Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 66.484MB |
Resource
Resource Usage Summary
I/O Port | 353 |
Emedded Port | 52 |
I/O Buf | 399 |
    IBUF | 216 |
    OBUF | 139 |
    TBUF | 4 |
    IOBUF | 36 |
    ELVDS_OBUF | 4 |
Register | 1144 |
    DFF | 1 |
    DFFP | 8 |
    DFFPE | 12 |
    DFFC | 633 |
    DFFCE | 490 |
LUT | 1978 |
    LUT2 | 468 |
    LUT3 | 782 |
    LUT4 | 728 |
ALU | 84 |
    ALU | 84 |
SSRAM | 36 |
    RAM16S4 | 36 |
INV | 29 |
    INV | 29 |
IOLOGIC | 120 |
    IDES4 | 32 |
    OSER4 | 48 |
    IODELAY | 40 |
CLOCK | 3 |
    DLL | 1 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Logic | 2307(2007 LUTs, 84 ALUs, 36 SSRAMs) / 8640 | 27% |
Register | 1144 / 6900 | 17% |
  --Register as Latch | 0 / 6900 | 0% |
  --Register as FF | 1144 / 6900 | 17% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
clkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 100.0(MHz) | 177.9(MHz) | 5 | TOP |
2 | clkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 287.3(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.175 |
Data Arrival Time | 1.692 |
Data Required Time | 5.867 |
From | u_psram_sync/cs_memsync_4_s0 |
To | u_dhcen_clk_x2 |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_sync/cs_memsync_4_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_psram_sync/cs_memsync_4_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_dhcen_clk_x2/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.729 | 0.729 | tINS | FF | 1 | memory_clk_ibuf/O |
6.085 | 0.356 | tNET | FF | 3 | u_dhcen_clk_x2/CLKIN |
6.055 | -0.030 | tUnc | u_dhcen_clk_x2 | ||
5.867 | -0.188 | tSu | 1 | u_dhcen_clk_x2 |
Clock Skew: | 0.089 |
Setup Relationship: | 5.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 2
Path Summary:Slack | 4.378 |
Data Arrival Time | 6.322 |
Data Required Time | 10.700 |
From | u_psram_sync/cs_memsync_5_s0 |
To | u_psram_sync/flag_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_sync/cs_memsync_5_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_psram_sync/cs_memsync_5_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_sync/n348_s11/I1 |
2.506 | 0.814 | tINS | FF | 5 | u_psram_sync/n348_s11/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_sync/n282_s19/I0 |
3.627 | 0.765 | tINS | FF | 4 | u_psram_sync/n282_s19/F |
3.982 | 0.356 | tNET | FF | 1 | u_psram_sync/n348_s7/I1 |
4.797 | 0.814 | tINS | FF | 1 | u_psram_sync/n348_s7/F |
5.152 | 0.356 | tNET | FF | 1 | u_psram_sync/n348_s5/I1 |
5.967 | 0.814 | tINS | FF | 1 | u_psram_sync/n348_s5/F |
6.322 | 0.356 | tNET | FF | 1 | u_psram_sync/flag_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_sync/flag_1_s0/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_sync/flag_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:Slack | 4.778 |
Data Arrival Time | 5.922 |
Data Required Time | 10.700 |
From | u_psram_sync/cs_memsync_5_s0 |
To | u_psram_sync/cs_memsync_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_sync/cs_memsync_5_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_psram_sync/cs_memsync_5_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_sync/n348_s11/I1 |
2.506 | 0.814 | tINS | FF | 5 | u_psram_sync/n348_s11/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_sync/n282_s19/I0 |
3.627 | 0.765 | tINS | FF | 4 | u_psram_sync/n282_s19/F |
3.982 | 0.356 | tNET | FF | 1 | u_psram_sync/n337_s13/I3 |
4.446 | 0.464 | tINS | FF | 1 | u_psram_sync/n337_s13/F |
4.802 | 0.356 | tNET | FF | 1 | u_psram_sync/n337_s12/I0 |
5.567 | 0.765 | tINS | FF | 1 | u_psram_sync/n337_s12/F |
5.922 | 0.356 | tNET | FF | 1 | u_psram_sync/cs_memsync_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_sync/cs_memsync_0_s0/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_sync/cs_memsync_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.808, 57.000%; route: 1.778, 36.105%; tC2Q: 0.340, 6.895% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:Slack | 4.884 |
Data Arrival Time | 5.816 |
Data Required Time | 10.700 |
From | u_psram_sync/count_2_s0 |
To | u_psram_sync/count_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_sync/count_2_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 6 | u_psram_sync/count_2_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_sync/n282_s17/I1 |
2.506 | 0.814 | tINS | FF | 1 | u_psram_sync/n282_s17/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_sync/n315_s13/I3 |
3.326 | 0.464 | tINS | FF | 2 | u_psram_sync/n315_s13/F |
3.681 | 0.356 | tNET | FF | 1 | u_psram_sync/n389_s2/I2 |
4.291 | 0.609 | tINS | FF | 3 | u_psram_sync/n389_s2/F |
4.646 | 0.356 | tNET | FF | 1 | u_psram_sync/n389_s1/I1 |
5.461 | 0.814 | tINS | FF | 1 | u_psram_sync/n389_s1/F |
5.816 | 0.356 | tNET | FF | 1 | u_psram_sync/count_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_sync/count_0_s0/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_sync/count_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.702, 56.055%; route: 1.778, 36.898%; tC2Q: 0.340, 7.047% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 5
Path Summary:Slack | 4.884 |
Data Arrival Time | 5.816 |
Data Required Time | 10.700 |
From | u_psram_sync/lock_cnt_1_s3 |
To | u_psram_sync/lock_cnt_14_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_psram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_psram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_psram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_psram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_psram_sync/n43_s2/I1 |
3.676 | 0.814 | tINS | FF | 7 | u_psram_sync/n43_s2/F |
4.032 | 0.356 | tNET | FF | 1 | u_psram_sync/n37_s2/I2 |
4.641 | 0.609 | tINS | FF | 2 | u_psram_sync/n37_s2/F |
4.997 | 0.356 | tNET | FF | 1 | u_psram_sync/n37_s5/I3 |
5.461 | 0.464 | tINS | FF | 1 | u_psram_sync/n37_s5/F |
5.816 | 0.356 | tNET | FF | 1 | u_psram_sync/lock_cnt_14_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
10.997 | 0.269 | tNET | RR | 1 | u_psram_sync/lock_cnt_14_s3/CLK |
10.700 | -0.296 | tSu | 1 | u_psram_sync/lock_cnt_14_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.702, 56.055%; route: 1.778, 36.898%; tC2Q: 0.340, 7.047% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |