Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2CH_2\data\APSRAM_TOP.v
C:\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\UHS_PSRAM_2CH_2\data\apsram_32_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9C
Created Time Tue Mar 09 17:14:22 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UHS_PSRAM_Memory_Interface_2CH_V2_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 51.063MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 51.063MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.157s, Peak memory usage = 51.063MB
    Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.201s, Peak memory usage = 51.063MB
    Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 51.063MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 51.063MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 51.063MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 51.063MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 51.063MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 51.063MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 51.063MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 51.063MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 66.176MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.383s, Peak memory usage = 66.176MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 66.176MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 66.176MB

Resource

Resource Usage Summary

I/O Port 354
Emedded Port 52
I/O Buf 400
    IBUF 217
    OBUF 139
    TBUF 4
    IOBUF 36
    ELVDS_OBUF 4
Register 1124
    DFF 1
    DFFP 8
    DFFPE 12
    DFFC 631
    DFFCE 472
LUT 1981
    LUT2 454
    LUT3 804
    LUT4 723
ALU 52
    ALU 52
SSRAM 36
    RAM16S4 36
INV 28
    INV 28
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
CLOCK 3
    CLKDIV 1
    DHCEN 2

Resource Utilization Summary

Logic 2277(2009 LUTs, 52 ALUs, 36 SSRAMs) / 8640 26%
Register 1124 / 6900 16%
  --Register as Latch 0 / 6900 0%
  --Register as FF 1124 / 6900 16%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
memory_clk_p Base 10.000 100.0 0.000 5.000 memory_clk_p_ibuf/I
clk_d Base 10.000 100.0 0.000 5.000 clk_d_ibuf/I
clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_d 100.0(MHz) 182.9(MHz) 5 TOP
2 clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 176.3(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.175
Data Arrival Time 1.692
Data Required Time 5.867
From u_psram_sync/cs_memsync_4_s0
To u_dhcen_clk_x2p
Launch Clk clk_d[F]
Latch Clk memory_clk_p[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.728 0.728 tINS RR 31 clk_d_ibuf/O
0.997 0.269 tNET RR 1 u_psram_sync/cs_memsync_4_s0/CLK
1.336 0.340 tC2Q RF 9 u_psram_sync/cs_memsync_4_s0/Q
1.692 0.356 tNET FF 1 u_dhcen_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk_p
5.000 0.000 tCL FF 1 memory_clk_p_ibuf/I
5.729 0.729 tINS FF 1 memory_clk_p_ibuf/O
6.085 0.356 tNET FF 3 u_dhcen_clk_x2p/CLKIN
6.055 -0.030 tUnc u_dhcen_clk_x2p
5.867 -0.188 tSu 1 u_dhcen_clk_x2p
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 2

Path Summary:
Slack 4.175
Data Arrival Time 1.692
Data Required Time 5.867
From u_psram_sync/cs_memsync_4_s0
To u_dhcen_clk_x2
Launch Clk clk_d[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.728 0.728 tINS RR 31 clk_d_ibuf/O
0.997 0.269 tNET RR 1 u_psram_sync/cs_memsync_4_s0/CLK
1.336 0.340 tC2Q RF 9 u_psram_sync/cs_memsync_4_s0/Q
1.692 0.356 tNET FF 1 u_dhcen_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 memory_clk
5.000 0.000 tCL FF 1 memory_clk_ibuf/I
5.729 0.729 tINS FF 1 memory_clk_ibuf/O
6.085 0.356 tNET FF 3 u_dhcen_clk_x2/CLKIN
6.055 -0.030 tUnc u_dhcen_clk_x2
5.867 -0.188 tSu 1 u_dhcen_clk_x2
Path Statistics:
Clock Skew: 0.089
Setup Relationship: 5.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.729, 67.222%; route: 0.356, 32.778%

Path 3

Path Summary:
Slack 4.533
Data Arrival Time 6.167
Data Required Time 10.700
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_11_s1
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.728 0.728 tINS RR 31 clk_d_ibuf/O
0.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 4 u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_psram_sync/n43_s2/I1
3.676 0.814 tINS FF 6 u_psram_sync/n43_s2/F
4.032 0.356 tNET FF 1 u_psram_sync/n41_s2/I2
4.641 0.609 tINS FF 2 u_psram_sync/n41_s2/F
4.997 0.356 tNET FF 1 u_psram_sync/n40_s1/I1
5.811 0.814 tINS FF 1 u_psram_sync/n40_s1/F
6.167 0.356 tNET FF 1 u_psram_sync/lock_cnt_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.728 0.728 tINS RR 31 clk_d_ibuf/O
10.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_11_s1/CLK
10.700 -0.296 tSu 1 u_psram_sync/lock_cnt_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 3.052, 59.034%; route: 1.778, 34.397%; tC2Q: 0.340, 6.569%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 4

Path Summary:
Slack 4.679
Data Arrival Time 6.022
Data Required Time 10.700
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_14_s3
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.728 0.728 tINS RR 31 clk_d_ibuf/O
0.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 4 u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_psram_sync/n43_s2/I1
3.676 0.814 tINS FF 6 u_psram_sync/n43_s2/F
4.032 0.356 tNET FF 1 u_psram_sync/n37_s3/I1
4.846 0.814 tINS FF 2 u_psram_sync/n37_s3/F
5.202 0.356 tNET FF 1 u_psram_sync/n37_s6/I3
5.666 0.464 tINS FF 1 u_psram_sync/n37_s6/F
6.022 0.356 tNET FF 1 u_psram_sync/lock_cnt_14_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.728 0.728 tINS RR 31 clk_d_ibuf/O
10.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_14_s3/CLK
10.700 -0.296 tSu 1 u_psram_sync/lock_cnt_14_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.907, 57.850%; route: 1.778, 35.391%; tC2Q: 0.340, 6.759%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%

Path 5

Path Summary:
Slack 4.679
Data Arrival Time 6.022
Data Required Time 10.700
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_15_s4
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.728 0.728 tINS RR 31 clk_d_ibuf/O
0.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.336 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.692 0.356 tNET FF 1 u_psram_sync/n47_s2/I1
2.506 0.814 tINS FF 4 u_psram_sync/n47_s2/F
2.862 0.356 tNET FF 1 u_psram_sync/n43_s2/I1
3.676 0.814 tINS FF 6 u_psram_sync/n43_s2/F
4.032 0.356 tNET FF 1 u_psram_sync/n37_s3/I1
4.846 0.814 tINS FF 2 u_psram_sync/n37_s3/F
5.202 0.356 tNET FF 1 u_psram_sync/n36_s4/I3
5.666 0.464 tINS FF 1 u_psram_sync/n36_s4/F
6.022 0.356 tNET FF 1 u_psram_sync/lock_cnt_15_s4/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.728 0.728 tINS RR 31 clk_d_ibuf/O
10.997 0.269 tNET RR 1 u_psram_sync/lock_cnt_15_s4/CLK
10.700 -0.296 tSu 1 u_psram_sync/lock_cnt_15_s4
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%
Arrival Data Path Delay: cell: 2.907, 57.850%; route: 1.778, 35.391%; tC2Q: 0.340, 6.759%
Required Clock Path Delay: cell: 0.728, 73.009%; route: 0.269, 26.991%