#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro #OS: Windows 8 6.2 #Hostname: JN-IP-SHANGYAN # Mon Feb 22 14:30:22 2021 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v" (library work) @I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_local_define.v" (library work) @I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_define.v" (library work) @I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_param.v" (library work) @I:"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_init.v":"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_local_param.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_lane.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_syn_top.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_sync.v" (library work) @N:CG346 : apsram_sync.v(159) | Read full_case directive. @N:CG347 : apsram_sync.v(159) | Read a parallel_case directive. @W:CG286 : apsram_sync.v(159) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive. @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_test.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_top_level0.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_top_level1.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_wd.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\fifo_sc.v" (library work) @I::"D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\gowin_rpll\gowin_rpll.v" (library work) @N:CG1306 : gowin_rpll.v(25) | Loading library file E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\IDE\data\hardware_core\gw1n\prim_syn.v into library work @I::"E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\IDE\data\hardware_core\gw1n\prim_syn.v" (library work) Verilog syntax check successful! File D:\datasheet\PROJECT\2_22\apsram_double_MBGA100PA\fpga_project_1\src\apsram_syn_top.v changed - recompiling Selecting top level module psram_syn_top @N:CG364 : gw1n.v(2181) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gw1n.v(2299) | Synthesizing module DLL in library work. Running optimization stage 1 on DLL ....... @N:CG364 : gw1n.v(2357) | Synthesizing module DHCEN in library work. Running optimization stage 1 on DHCEN ....... @N:CG364 : gw1n.v(2288) | Synthesizing module CLKDIV in library work. Running optimization stage 1 on CLKDIV ....... @N:CG364 : apsram_sync.v(4) | Synthesizing module \~apsram_sync.psram_memory_interface_top_2ch in library work. @N:CG179 : apsram_sync.v(121) | Removing redundant assignment. @W:CG133 : apsram_sync.v(50) | Object lock_d1 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on \~apsram_sync.psram_memory_interface_top_2ch ....... @W:CL177 : apsram_sync.v(139) | Sharing sequential element ddr_rst_d1. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : apsram_wd.v(4) | Synthesizing module \~apsram_wd.psram_memory_interface_top_2ch in library work. @N:CG364 : gw1n.v(388) | Synthesizing module OSER4 in library work. Running optimization stage 1 on OSER4 ....... @N:CG364 : apsram_lane.v(4) | Synthesizing module \~apsram_lane.psram_memory_interface_top_2ch in library work. @N:CG364 : gw1n.v(356) | Synthesizing module IDES4 in library work. Running optimization stage 1 on IDES4 ....... @W:CG133 : apsram_lane.v(101) | Object cs_st_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_lane.v(102) | Object init_cs_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_lane.v(108) | Object dqstx0_dd is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_lane.v(118) | Object wr_en_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : apsram_lane.v(127) | Removing wire wr_data_d, as there is no assignment to it. @W:CG360 : apsram_lane.v(128) | Removing wire data_mask_d, as there is no assignment to it. @W:CG360 : apsram_lane.v(134) | Removing wire cs_d5, as there is no assignment to it. @W:CG360 : apsram_lane.v(140) | Removing wire in_dqs, as there is no assignment to it. Running optimization stage 1 on \~apsram_lane.psram_memory_interface_top_2ch ....... @W:CL318 : apsram_lane.v(70) | *Output recalib has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : apsram_lane.v(87) | *Output test0 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL169 : apsram_lane.v(494) | Pruning unused register dqstx1_d. Make sure that there are no unused intermediate registers. @W:CL169 : apsram_lane.v(485) | Pruning unused register genblk7.dqtx_dd0. Make sure that there are no unused intermediate registers. @W:CL169 : apsram_lane.v(475) | Pruning unused register genblk7.dqtx_dd. Make sure that there are no unused intermediate registers. @W:CL169 : apsram_lane.v(393) | Pruning unused register cs_dd. Make sure that there are no unused intermediate registers. @W:CL113 : apsram_lane.v(682) | Feedback mux created for signal rd_data_valid_d1[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL177 : apsram_lane.v(457) | Sharing sequential element dqtx0_d. Add a syn_preserve attribute to the element to prevent sharing. @W:CL250 : apsram_lane.v(682) | All reachable assignments to rd_data_valid_d1[2] assign 0, register removed by optimization @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_lane.v(170) | Optimizing register bit CA_reg[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : apsram_lane.v(170) | Pruning register bits 30 to 22 of CA_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CG781 : apsram_wd.v(127) | Input clk_x2p on instance u_psram_lane is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @N:CG364 : gw1n.v(318) | Synthesizing module IOBUF in library work. Running optimization stage 1 on IOBUF ....... @N:CG364 : gw1n.v(433) | Synthesizing module IODELAY in library work. Running optimization stage 1 on IODELAY ....... @N:CG179 : apsram_wd.v(250) | Removing redundant assignment. @N:CG364 : gw1n.v(2247) | Synthesizing module ELVDS_OBUF in library work. Running optimization stage 1 on ELVDS_OBUF ....... @N:CG364 : gw1n.v(314) | Synthesizing module TBUF in library work. Running optimization stage 1 on TBUF ....... @N:CG364 : gw1n.v(310) | Synthesizing module OBUF in library work. Running optimization stage 1 on OBUF ....... @W:CG360 : apsram_wd.v(85) | Removing wire dqs_ts, as there is no assignment to it. @W:CG360 : apsram_wd.v(91) | Removing wire clkn_out_d, as there is no assignment to it. @W:CG360 : apsram_wd.v(94) | Removing wire wr_en_delay, as there is no assignment to it. @W:CG360 : apsram_wd.v(97) | Removing wire out_init, as there is no assignment to it. @W:CG360 : apsram_wd.v(98) | Removing wire out_inits, as there is no assignment to it. @W:CG360 : apsram_wd.v(99) | Removing wire out_ca, as there is no assignment to it. @W:CG360 : apsram_wd.v(100) | Removing wire out_cats, as there is no assignment to it. @W:CG360 : apsram_wd.v(101) | Removing wire out_data, as there is no assignment to it. @W:CG360 : apsram_wd.v(102) | Removing wire out_datats, as there is no assignment to it. Running optimization stage 1 on \~apsram_wd.psram_memory_interface_top_2ch ....... @N:CG364 : apsram_init.v(4) | Synthesizing module \~apsram_init.psram_memory_interface_top_2ch in library work. @N:CG179 : apsram_init.v(270) | Removing redundant assignment. @N:CG179 : apsram_init.v(286) | Removing redundant assignment. @N:CG179 : apsram_init.v(296) | Removing redundant assignment. @N:CG179 : apsram_init.v(304) | Removing redundant assignment. @N:CG179 : apsram_init.v(314) | Removing redundant assignment. @N:CG179 : apsram_init.v(431) | Removing redundant assignment. @N:CG179 : apsram_init.v(587) | Removing redundant assignment. @N:CG179 : apsram_init.v(619) | Removing redundant assignment. @N:CG179 : apsram_init.v(629) | Removing redundant assignment. @W:CG133 : apsram_init.v(69) | Object STEN is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_init.v(66) | Object cnt_clr is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on \~apsram_init.psram_memory_interface_top_2ch ....... @W:CL207 : apsram_init.v(442) | All reachable assignments to addr[21:0] assign 0, register removed by optimization. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_init.v(442) | Optimizing register bit wr_data[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : apsram_init.v(442) | Pruning register bit 25 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : apsram_init.v(442) | Pruning register bit 16 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : apsram_init.v(442) | Pruning register bits 11 to 10 of wr_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : apsram_init.v(442) | Pruning register bit 5 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : apsram_init.v(442) | Pruning register bit 1 of wr_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : apsram_top_level0.v(4) | Synthesizing module \~apsram_top.psram_memory_interface_top_2ch in library work. @W:CG133 : apsram_top_level0.v(66) | Object calib_cnt is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_top_level0.v(67) | Object calib_div0 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : apsram_top_level0.v(68) | Object calib_div1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : apsram_top_level0.v(85) | Removing wire wr_cs, as there is no assignment to it. @W:CG360 : apsram_top_level0.v(99) | Removing wire dell_step, as there is no assignment to it. @W:CG360 : apsram_top_level0.v(109) | Removing wire clk_x2p, as there is no assignment to it. @W:CG360 : apsram_top_level0.v(110) | Removing wire clk_x1p, as there is no assignment to it. @W:CG360 : apsram_top_level0.v(112) | Removing wire calib_div, as there is no assignment to it. Running optimization stage 1 on \~apsram_top.psram_memory_interface_top_2ch ....... @N:CG364 : apsram_top_level1.v(5) | Synthesizing module psram_memory_interface_top_2ch in library work. @W:CG781 : apsram_top_level1.v(147) | Input pll_lock on instance u_psram_top0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : apsram_top_level1.v(175) | Input pll_lock on instance u_psram_top1 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG360 : apsram_top_level1.v(86) | Removing wire clk_x1p, as there is no assignment to it. @W:CG360 : apsram_top_level1.v(87) | Removing wire clk_x2p, as there is no assignment to it. Running optimization stage 1 on psram_memory_interface_top_2ch ....... @N:CG364 : apsram_test.v(2) | Synthesizing module apsram_test in library work. @W:CS142 : apsram_test.v(9) | Range of port wr_data in port declaration and body are different. @N:CG179 : apsram_test.v(186) | Removing redundant assignment. @A:CG412 : apsram_test.v(276) | Treating === and !== as == and != -- possible simulation mismatch Running optimization stage 1 on apsram_test ....... @W:CL207 : apsram_test.v(156) | All reachable assignments to data_mask[3:0] assign 0, register removed by optimization. @W:CL190 : apsram_test.v(156) | Optimizing register bit addr_add_r[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : apsram_test.v(156) | Optimizing register bit addr_add_w[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr_add_r[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr_add_w[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : apsram_syn_top.v(2) | Synthesizing module psram_syn_top in library work. @W:CS263 : apsram_syn_top.v(184) | Port-width mismatch for port wr_data. The port definition is 64 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CS263 : apsram_syn_top.v(202) | Port-width mismatch for port wr_data. The port definition is 64 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CG360 : apsram_syn_top.v(49) | Removing wire init_done0, as there is no assignment to it. @W:CG360 : apsram_syn_top.v(58) | Removing wire init_done1, as there is no assignment to it. Running optimization stage 1 on psram_syn_top ....... Running optimization stage 2 on psram_syn_top ....... @W:CL260 : apsram_syn_top.v(74) | Pruning register bit 1 of led[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on apsram_test ....... @W:CL190 : apsram_test.v(156) | Optimizing register bit addr[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : apsram_test.v(156) | Pruning register bit 0 of addr[21:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : apsram_test.v(84) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Running optimization stage 2 on psram_memory_interface_top_2ch ....... Running optimization stage 2 on \~apsram_top.psram_memory_interface_top_2ch ....... @W:CL156 : apsram_top_level0.v(110) | *Input clk_x1p to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : apsram_top_level0.v(109) | *Input clk_x2p to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @N:CL159 : apsram_top_level0.v(37) | Input clk is unused. @N:CL159 : apsram_top_level0.v(41) | Input pll_lock is unused. Running optimization stage 2 on \~apsram_init.psram_memory_interface_top_2ch ....... @W:CL260 : apsram_init.v(345) | Pruning register bit 31 of genblk1.init_dq[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : apsram_init.v(345) | Pruning register bits 29 to 3 of genblk1.init_dq[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL177 : apsram_init.v(363) | Sharing sequential element init_dqts. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : apsram_init.v(169) | Trying to extract state machine for register c_state. Extracted state machine for register c_state State machine has 19 reachable states with original encodings of: 0000000000000000001 0000000000000000010 0000000000000000100 0000000000000001000 0000000000000010000 0000000000000100000 0000000000001000000 0000000000010000000 0000000000100000000 0000000001000000000 0000000010000000000 0000000100000000000 0000001000000000000 0000010000000000000 0000100000000000000 0001000000000000000 0010000000000000000 0100000000000000000 1000000000000000000 @W:CL279 : apsram_init.v(442) | Pruning register bits 2 to 1 of burst_num[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : apsram_init.v(442) | Pruning register bits 9 to 7 of wr_data[9:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : apsram_init.v(442) | Pruning register bit 15 of wr_data[15:12]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : apsram_init.v(442) | Pruning register bits 24 to 20 of wr_data[24:17]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : apsram_init.v(442) | Pruning register bits 31 to 29 of wr_data[31:26]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @A:CL153 : apsram_init.v(69) | *Unassigned bits of STEN[0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : apsram_init.v(56) | Input DF is unused. Running optimization stage 2 on OBUF ....... Running optimization stage 2 on TBUF ....... Running optimization stage 2 on ELVDS_OBUF ....... Running optimization stage 2 on IODELAY ....... Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on IDES4 ....... Running optimization stage 2 on \~apsram_lane.psram_memory_interface_top_2ch ....... @W:CL177 : apsram_lane.v(544) | Sharing sequential element genblk8.dqtx1. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : apsram_lane.v(184) | Trying to extract state machine for register c_state. Extracted state machine for register c_state State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 @N:CL159 : apsram_lane.v(51) | Input clk_x2p is unused. @N:CL159 : apsram_lane.v(59) | Input wr_en is unused. @N:CL159 : apsram_lane.v(68) | Input dqs is unused. Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on \~apsram_wd.psram_memory_interface_top_2ch ....... @N:CL159 : apsram_wd.v(46) | Input clk_x1p is unused. @N:CL159 : apsram_wd.v(48) | Input clk_x2p is unused. @N:CL159 : apsram_wd.v(67) | Input STEN is unused. Running optimization stage 2 on \~apsram_sync.psram_memory_interface_top_2ch ....... @N:CL201 : apsram_sync.v(139) | Trying to extract state machine for register flag. Extracted state machine for register flag State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on DHCEN ....... Running optimization stage 2 on DLL ....... Running optimization stage 2 on PLL ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 113MB peak: 119MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Feb 22 14:30:25 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: E:\gwide\47874\Gowin\Gowin_V1.9.7.02Beta1\SynplifyPro OS: Windows 6.2 Hostname: JN-IP-SHANGYAN Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Feb 22 14:30:25 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: fpga_project_1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 33MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Mon Feb 22 14:30:25 2021 ###########################################################]