Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AT-LV60UG225C1/I0
Device GW5AT-60
Device Version B
Created Time Thu May 8 17:46:25 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module \~upar_arbiter_wrap.SerDes_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.829s, Peak memory usage = 69.988MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 69.988MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 69.988MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 69.988MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 69.988MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 69.988MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 69.988MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 69.988MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.988MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 69.988MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 69.988MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 69.988MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.385s, Peak memory usage = 93.027MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 93.027MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 93.027MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.027MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 511
I/O Buf 511
    IBUF 299
    OBUF 212
Register 282
    DFFPE 4
    DFFCE 278
LUT 369
    LUT2 132
    LUT3 165
    LUT4 72
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 370(370 LUT, 0 ALU) / 59904 <1%
Register 282 / 60231 <1%
  --Register as Latch 0 / 60231 0%
  --Register as FF 282 / 60231 <1%
BSRAM 0 / 118 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 upar_clk_i Base 10.000 100.000 0.000 5.000 upar_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 upar_clk_i 100.000(MHz) 289.017(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.540
Data Arrival Time 3.771
Data Required Time 10.311
From u_upar_arbiter/cur_grant_3_s0
To u_upar_arbiter/drp_num_1_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/CLK
0.757 0.382 tC2Q RR 2 u_upar_arbiter/cur_grant_3_s0/Q
1.132 0.375 tNET RR 1 u_upar_arbiter/n341_s2/I2
1.594 0.461 tINS RR 4 u_upar_arbiter/n341_s2/F
1.969 0.375 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_1_s1/I0
2.495 0.526 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_1_s1/F
2.870 0.375 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_1_s0/I0
3.396 0.526 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_1_s0/F
3.771 0.375 tNET RR 1 u_upar_arbiter/drp_num_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.375 0.375 tNET RR 1 u_upar_arbiter/drp_num_1_s0/CLK
10.311 -0.064 tSu 1 u_upar_arbiter/drp_num_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.514, 44.572%; route: 1.500, 44.166%; tC2Q: 0.382, 11.262%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 6.605
Data Arrival Time 3.706
Data Required Time 10.311
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/cur_state_0_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.375 0.375 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.757 0.382 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
1.132 0.375 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.659 0.526 tINS RR 2 u_upar_arbiter/n689_s2/F
2.034 0.375 tNET RR 1 u_upar_arbiter/next_state_0_s7/I2
2.495 0.461 tINS RR 1 u_upar_arbiter/next_state_0_s7/F
2.870 0.375 tNET RR 1 u_upar_arbiter/next_state_0_s5/I2
3.331 0.461 tINS RR 1 u_upar_arbiter/next_state_0_s5/F
3.706 0.375 tNET RR 1 u_upar_arbiter/cur_state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.375 0.375 tNET RR 1 u_upar_arbiter/cur_state_0_s0/CLK
10.311 -0.064 tSu 1 u_upar_arbiter/cur_state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.449, 43.490%; route: 1.500, 45.028%; tC2Q: 0.382, 11.482%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 6.670
Data Arrival Time 3.641
Data Required Time 10.311
From u_upar_arbiter/cur_grant_2_s0
To u_upar_arbiter/drp_num_0_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/CLK
0.757 0.382 tC2Q RR 1 u_upar_arbiter/cur_grant_2_s0/Q
1.132 0.375 tNET RR 1 u_upar_arbiter/n341_s3/I2
1.594 0.461 tINS RR 6 u_upar_arbiter/n341_s3/F
1.969 0.375 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_0_s1/I2
2.430 0.461 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_0_s1/F
2.805 0.375 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_0_s0/I2
3.266 0.461 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_0_s0/F
3.641 0.375 tNET RR 1 u_upar_arbiter/drp_num_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.375 0.375 tNET RR 1 u_upar_arbiter/drp_num_0_s0/CLK
10.311 -0.064 tSu 1 u_upar_arbiter/drp_num_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.384, 42.365%; route: 1.500, 45.924%; tC2Q: 0.382, 11.711%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 6.670
Data Arrival Time 3.641
Data Required Time 10.311
From u_upar_arbiter/cur_grant_2_s0
To u_upar_arbiter/cur_grant_1_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/CLK
0.757 0.382 tC2Q RR 1 u_upar_arbiter/cur_grant_2_s0/Q
1.132 0.375 tNET RR 1 u_upar_arbiter/n341_s3/I2
1.594 0.461 tINS RR 6 u_upar_arbiter/n341_s3/F
1.969 0.375 tNET RR 1 u_upar_arbiter/n343_s1/I2
2.430 0.461 tINS RR 1 u_upar_arbiter/n343_s1/F
2.805 0.375 tNET RR 1 u_upar_arbiter/n343_s0/I2
3.266 0.461 tINS RR 1 u_upar_arbiter/n343_s0/F
3.641 0.375 tNET RR 1 u_upar_arbiter/cur_grant_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_1_s0/CLK
10.311 -0.064 tSu 1 u_upar_arbiter/cur_grant_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.384, 42.365%; route: 1.500, 45.924%; tC2Q: 0.382, 11.711%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 7.068
Data Arrival Time 3.244
Data Required Time 10.311
From u_upar_arbiter/cur_grant_0_s0
To u_upar_arbiter/cur_grant_3_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_0_s0/CLK
0.757 0.382 tC2Q RR 3 u_upar_arbiter/cur_grant_0_s0/Q
1.132 0.375 tNET RR 1 u_upar_arbiter/n341_s6/I2
1.594 0.461 tINS RR 2 u_upar_arbiter/n341_s6/F
1.969 0.375 tNET RR 1 u_upar_arbiter/n341_s7/I3
2.231 0.262 tINS RR 3 u_upar_arbiter/n341_s7/F
2.606 0.375 tNET RR 1 u_upar_arbiter/n341_s0/I3
2.869 0.262 tINS RR 1 u_upar_arbiter/n341_s0/F
3.244 0.375 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.375 0.375 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/CLK
10.311 -0.064 tSu 1 u_upar_arbiter/cur_grant_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 0.986, 34.379%; route: 1.500, 52.288%; tC2Q: 0.382, 13.333%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%