Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\USB30DEVICECONTROLLER\data\USB30_Device_Controller_Top.v
C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\USB30DEVICECONTROLLER\data\usb30_device_controller.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Wed May 8 15:54:04 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB30_Device_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.836s, Peak memory usage = 160.164MB
Running netlist conversion:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.098s, Peak memory usage = 160.164MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.842s, Peak memory usage = 160.164MB
    Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 160.164MB
    Optimizing Phase 2: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.975s, Peak memory usage = 160.164MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 160.164MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 160.164MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 160.164MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 160.164MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.953s, Elapsed time = 0h 0m 0.953s, Peak memory usage = 160.164MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.249s, Peak memory usage = 160.164MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.369s, Peak memory usage = 160.164MB
    Tech-Mapping Phase 3: CPU time = 0h 2m 17s, Elapsed time = 0h 2m 17s, Peak memory usage = 185.082MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.525s, Peak memory usage = 185.082MB
Generate output files:
    CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.522s, Peak memory usage = 186.887MB
Total Time and Memory Usage CPU time = 0h 2m 23s, Elapsed time = 0h 2m 23s, Peak memory usage = 186.887MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 347
I/O Buf 347
    IBUF 139
    OBUF 208
Register 2983
    DFFSE 112
    DFFRE 1738
    DFFPE 74
    DFFCE 1059
LUT 4978
    LUT2 614
    LUT3 1403
    LUT4 2961
ALU 157
    ALU 157
INV 34
    INV 34
DSP
    MULTALU27X18 1
BSRAM 4
    SDPB 4

Resource Utilization Summary

Resource Usage Utilization
Logic 5169(5012 LUT, 157 ALU) / 138240 4%
Register 2983 / 139140 3%
  --Register as Latch 0 / 139140 0%
  --Register as FF 2983 / 139140 3%
BSRAM 4 / 340 2%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
phy_clk_i Base 10.000 100.0 0.000 5.000 phy_clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 phy_clk_i 100.000(MHz) 101.574(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.155
Data Arrival Time 10.194
Data Required Time 10.349
From usb30_device_controller_inst/iu3lt/dc_6_s0
To usb30_device_controller_inst/iu3lt/state_3_s0
Launch Clk phy_clk_i[R]
Latch Clk phy_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 phy_clk_i
0.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
0.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
0.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_6_s0/CLK
0.795 0.382 tC2Q RR 7 usb30_device_controller_inst/iu3lt/dc_6_s0/Q
1.207 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s83/I0
1.786 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s83/F
2.199 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s84/I2
2.706 0.507 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s84/F
3.119 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s74/I0
3.698 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1685_s74/F
4.110 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s65/I2
4.618 0.507 tINS RR 10 usb30_device_controller_inst/iu3lt/n1685_s65/F
5.030 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s70/I0
5.609 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s70/F
6.021 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s59/I0
6.600 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s59/F
7.013 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s95/I2
7.520 0.507 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s95/F
7.933 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s89/I1
8.083 0.150 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s89/O
8.495 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s86/I1
8.581 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s86/O
8.994 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s40/I0
9.080 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s40/O
9.493 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n2673_s2/I3
9.781 0.289 tINS RR 1 usb30_device_controller_inst/iu3lt/n2673_s2/F
10.194 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 phy_clk_i
10.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
10.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
10.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_3_s0/CLK
10.349 -0.064 tSu 1 usb30_device_controller_inst/iu3lt/state_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.449, 45.482%; route: 4.950, 50.607%; tC2Q: 0.382, 3.911%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 0.592
Data Arrival Time 9.756
Data Required Time 10.349
From usb30_device_controller_inst/iu3lt/polling_lfps_sent_0_s3
To usb30_device_controller_inst/iu3lt/state_4_s0
Launch Clk phy_clk_i[R]
Latch Clk phy_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 phy_clk_i
0.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
0.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
0.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/polling_lfps_sent_0_s3/CLK
0.795 0.382 tC2Q RR 6 usb30_device_controller_inst/iu3lt/polling_lfps_sent_0_s3/Q
1.207 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1743_s12/I0
1.786 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1743_s12/F
2.199 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1743_s10/I0
2.778 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1743_s10/F
3.190 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1743_s8/I2
3.697 0.507 tINS RR 2 usb30_device_controller_inst/iu3lt/n1743_s8/F
4.110 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s55/I0
4.689 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s55/F
5.101 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n401_s4/I3
5.390 0.289 tINS RR 1 usb30_device_controller_inst/iu3lt/n401_s4/F
5.803 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n401_s2/I3
6.091 0.289 tINS RR 3 usb30_device_controller_inst/iu3lt/n401_s2/F
6.504 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s99/I0
7.083 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s99/F
7.495 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s94/I0
7.645 0.150 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s94/O
8.058 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s91/I1
8.144 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s91/O
8.556 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s41/I0
8.643 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s41/O
9.055 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n2672_s2/I3
9.344 0.289 tINS RR 1 usb30_device_controller_inst/iu3lt/n2672_s2/F
9.756 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 phy_clk_i
10.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
10.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
10.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_4_s0/CLK
10.349 -0.064 tSu 1 usb30_device_controller_inst/iu3lt/state_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.011, 42.930%; route: 4.950, 52.976%; tC2Q: 0.382, 4.094%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 1.295
Data Arrival Time 9.054
Data Required Time 10.349
From usb30_device_controller_inst/iu3lt/dc_6_s0
To usb30_device_controller_inst/iu3lt/state_0_s1
Launch Clk phy_clk_i[R]
Latch Clk phy_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 phy_clk_i
0.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
0.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
0.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_6_s0/CLK
0.795 0.382 tC2Q RR 7 usb30_device_controller_inst/iu3lt/dc_6_s0/Q
1.207 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s83/I0
1.786 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s83/F
2.199 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s84/I2
2.706 0.507 tINS RR 1 usb30_device_controller_inst/iu3lt/n1685_s84/F
3.119 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s74/I0
3.698 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1685_s74/F
4.110 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s65/I2
4.618 0.507 tINS RR 10 usb30_device_controller_inst/iu3lt/n1685_s65/F
5.030 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1689_s106/I1
5.598 0.567 tINS RR 1 usb30_device_controller_inst/iu3lt/n1689_s106/F
6.010 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1689_s95/I0
6.589 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1689_s95/F
7.001 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1689_s112/I0
7.580 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1689_s112/F
7.993 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1689_s109/I1
8.142 0.150 tINS RR 1 usb30_device_controller_inst/iu3lt/n1689_s109/O
8.555 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1689_s86/I0
8.641 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1689_s86/O
9.054 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 phy_clk_i
10.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
10.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
10.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/state_0_s1/CLK
10.349 -0.064 tSu 1 usb30_device_controller_inst/iu3lt/state_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.134, 47.838%; route: 4.125, 47.736%; tC2Q: 0.382, 4.426%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 1.295
Data Arrival Time 9.054
Data Required Time 10.349
From usb30_device_controller_inst/iu3lt/dc_6_s0
To usb30_device_controller_inst/iu3lt/dc_1_s0
Launch Clk phy_clk_i[R]
Latch Clk phy_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 phy_clk_i
0.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
0.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
0.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_6_s0/CLK
0.795 0.382 tC2Q RR 7 usb30_device_controller_inst/iu3lt/dc_6_s0/Q
1.207 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s83/I0
1.786 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s83/F
2.199 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s80/I0
2.778 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s80/F
3.190 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s74/I2
3.697 0.507 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s74/F
4.110 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s69/I2
4.618 0.507 tINS RR 9 usb30_device_controller_inst/iu3lt/n1685_s69/F
5.030 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1728_s45/I0
5.609 0.579 tINS RR 10 usb30_device_controller_inst/iu3lt/n1728_s45/F
6.021 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1697_s53/I1
6.589 0.567 tINS RR 23 usb30_device_controller_inst/iu3lt/n1697_s53/F
7.001 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1720_s61/I0
7.580 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1720_s61/F
7.993 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1720_s57/I1
8.142 0.150 tINS RR 1 usb30_device_controller_inst/iu3lt/n1720_s57/O
8.555 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1720_s45/I1
8.641 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1720_s45/O
9.054 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 phy_clk_i
10.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
10.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
10.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_1_s0/CLK
10.349 -0.064 tSu 1 usb30_device_controller_inst/iu3lt/dc_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.134, 47.838%; route: 4.125, 47.736%; tC2Q: 0.382, 4.426%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 1.295
Data Arrival Time 9.054
Data Required Time 10.349
From usb30_device_controller_inst/iu3lt/dc_6_s0
To usb30_device_controller_inst/iu3lt/dc_2_s0
Launch Clk phy_clk_i[R]
Latch Clk phy_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 phy_clk_i
0.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
0.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
0.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_6_s0/CLK
0.795 0.382 tC2Q RR 7 usb30_device_controller_inst/iu3lt/dc_6_s0/Q
1.207 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s83/I0
1.786 0.579 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s83/F
2.199 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s80/I0
2.778 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1686_s80/F
3.190 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1686_s74/I2
3.697 0.507 tINS RR 2 usb30_device_controller_inst/iu3lt/n1686_s74/F
4.110 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1685_s69/I2
4.618 0.507 tINS RR 9 usb30_device_controller_inst/iu3lt/n1685_s69/F
5.030 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1728_s45/I0
5.609 0.579 tINS RR 10 usb30_device_controller_inst/iu3lt/n1728_s45/F
6.021 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1697_s53/I1
6.589 0.567 tINS RR 23 usb30_device_controller_inst/iu3lt/n1697_s53/F
7.001 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1719_s59/I0
7.580 0.579 tINS RR 1 usb30_device_controller_inst/iu3lt/n1719_s59/F
7.993 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1719_s55/I1
8.142 0.150 tINS RR 1 usb30_device_controller_inst/iu3lt/n1719_s55/O
8.555 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/n1719_s45/I1
8.641 0.086 tINS RR 1 usb30_device_controller_inst/iu3lt/n1719_s45/O
9.054 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 phy_clk_i
10.000 0.000 tCL RR 1 phy_clk_i_ibuf/I
10.000 0.000 tINS RR 2992 phy_clk_i_ibuf/O
10.413 0.413 tNET RR 1 usb30_device_controller_inst/iu3lt/dc_2_s0/CLK
10.349 -0.064 tSu 1 usb30_device_controller_inst/iu3lt/dc_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.134, 47.838%; route: 4.125, 47.736%; tC2Q: 0.382, 4.426%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%