Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy_top.v
D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Apr 25 14:28:33 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB3_0_PHY_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.489s, Peak memory usage = 83.137MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 83.137MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 83.137MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 83.137MB
    Optimizing Phase 2: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.252s, Peak memory usage = 83.137MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 83.137MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 83.137MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 83.137MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 83.137MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 83.137MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 83.137MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 83.137MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 111.605MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 111.605MB
Generate output files:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 111.605MB
Total Time and Memory Usage CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 111.605MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 394
I/O Buf 295
    IBUF 98
    OBUF 197
Register 684
    DFFSE 5
    DFFRE 5
    DFFPE 12
    DFFCE 662
LUT 1369
    LUT2 135
    LUT3 434
    LUT4 800
ALU 7
    ALU 7
INV 8
    INV 8
CLOCK 1
    DCE 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1384(1377 LUT, 7 ALU) / 138240 2%
Register 684 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 684 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
serdes_pcs_tx_clk_i Base 10.000 100.0 0.000 5.000 serdes_pcs_tx_clk_i_ibuf/I
serdes_upar_clk_i Base 10.000 100.0 0.000 5.000 serdes_upar_clk_i_ibuf/I
Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d Base 10.000 100.0 0.000 5.000 Inst_usb3_0_phy/Inst_clk_out/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_upar_clk_i 100.000(MHz) 197.190(MHz) 5 TOP
2 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d 100.000(MHz) 103.883(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.374
Data Arrival Time 9.975
Data Required Time 10.349
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_0_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Launch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Latch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
0.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
0.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_0_s0/CLK
0.795 0.382 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_0_s0/Q
1.207 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s24/I0
1.786 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s24/F
2.199 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s17/I0
2.778 0.579 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s17/F
3.190 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s19/I0
3.769 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s19/F
4.181 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s10/I0
4.760 0.579 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s10/F
5.173 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s49/I0
5.751 0.579 tINS RR 4 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s49/F
6.164 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s14/I2
6.671 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s14/F
7.084 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s14/I0
7.663 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s14/F
8.075 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s6/I1
8.643 0.567 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s6/F
9.055 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s3/I2
9.563 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s3/F
9.975 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
10.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
10.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CLK
10.349 -0.064 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.055, 52.863%; route: 4.125, 43.137%; tC2Q: 0.382, 4.000%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 1.058
Data Arrival Time 9.044
Data Required Time 10.101
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1
Launch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Latch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
0.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
0.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.795 0.382 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
1.207 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/I0
1.786 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/F
2.199 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/I0
2.778 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/F
3.190 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/I1
3.758 0.567 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/F
4.170 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/I2
4.678 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/F
5.090 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/I0
5.669 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/F
6.081 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/I0
6.660 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/F
7.073 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/I0
7.651 0.579 tINS RR 20 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/F
8.064 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/I1
8.631 0.567 tINS RR 14 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/F
9.044 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
10.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
10.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/CLK
10.101 -0.311 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.536, 52.556%; route: 3.712, 43.012%; tC2Q: 0.382, 4.432%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 1.058
Data Arrival Time 9.044
Data Required Time 10.101
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1
Launch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Latch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
0.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
0.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.795 0.382 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
1.207 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/I0
1.786 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/F
2.199 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/I0
2.778 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/F
3.190 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/I1
3.758 0.567 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/F
4.170 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/I2
4.678 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/F
5.090 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/I0
5.669 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/F
6.081 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/I0
6.660 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/F
7.073 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/I0
7.651 0.579 tINS RR 20 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/F
8.064 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/I1
8.631 0.567 tINS RR 14 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/F
9.044 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
10.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
10.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1/CLK
10.101 -0.311 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.536, 52.556%; route: 3.712, 43.012%; tC2Q: 0.382, 4.432%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 1.058
Data Arrival Time 9.044
Data Required Time 10.101
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_7_s1
Launch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Latch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
0.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
0.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.795 0.382 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
1.207 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/I0
1.786 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/F
2.199 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/I0
2.778 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/F
3.190 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/I1
3.758 0.567 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/F
4.170 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/I2
4.678 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/F
5.090 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/I0
5.669 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/F
6.081 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/I0
6.660 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/F
7.073 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/I0
7.651 0.579 tINS RR 20 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/F
8.064 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/I1
8.631 0.567 tINS RR 14 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/F
9.044 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_7_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
10.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
10.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_7_s1/CLK
10.101 -0.311 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.536, 52.556%; route: 3.712, 43.012%; tC2Q: 0.382, 4.432%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 1.058
Data Arrival Time 9.044
Data Required Time 10.101
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_10_s1
Launch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Latch Clk Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
0.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
0.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.795 0.382 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
1.207 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/I0
1.786 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s106/F
2.199 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/I0
2.778 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s105/F
3.190 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/I1
3.758 0.567 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s104/F
4.170 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/I2
4.678 0.507 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s103/F
5.090 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/I0
5.669 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s99/F
6.081 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/I0
6.660 0.579 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s97/F
7.073 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/I0
7.651 0.579 tINS RR 20 Inst_usb3_0_phy/Inst_usb_pipe_interface/n32_s96/F
8.064 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/I1
8.631 0.567 tINS RR 14 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s5/F
9.044 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_10_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Inst_usb3_0_phy/serdes_fabric_rx_clk_o_d
10.000 0.000 tCL RR 637 Inst_usb3_0_phy/Inst_clk_out/CLKOUT
10.413 0.413 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_10_s1/CLK
10.101 -0.311 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 4.536, 52.556%; route: 3.712, 43.012%; tC2Q: 0.382, 4.432%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%