Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\haogang\Desktop\Gowin_USB3.0_UVC_ISO_RefDeign_want_change\Gowin_USB30_UVC_ISO_RefDeign\prj\src\line_fifo\temp\FIFO\fifo_define.v
C:\Users\haogang\Desktop\Gowin_USB3.0_UVC_ISO_RefDeign_want_change\Gowin_USB30_UVC_ISO_RefDeign\prj\src\line_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AT-LV60UG225C1/I0
Device GW5AT-60
Device Version B
Created Time Fri May 9 18:09:34 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module line_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.873s, Peak memory usage = 82.348MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 82.348MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 82.348MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 82.348MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 82.348MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 82.348MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 82.348MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 82.348MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 82.348MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 82.348MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 82.348MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 82.348MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.834s, Peak memory usage = 97.465MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 97.465MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 97.465MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 97.465MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 72
I/O Buf 72
    IBUF 37
    OBUF 35
Register 74
    DFFPE 6
    DFFCE 68
LUT 106
    LUT2 25
    LUT3 31
    LUT4 50
ALU 21
    ALU 21
SSRAM 3
    RAM16S4 3
INV 3
    INV 3
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 148(109 LUT, 21 ALU, 3 RAM16) / 59904 <1%
Register 74 / 60231 <1%
  --Register as Latch 0 / 60231 0%
  --Register as FF 74 / 60231 <1%
BSRAM 2 / 118 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.000 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.000 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 113.395(MHz) 11 TOP
2 WrClk 100.000(MHz) 226.436(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.181
Data Arrival Time 9.130
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 33 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 9 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s12/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Equal.rq1_wptr_0_s12/DO[0]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_6_s1/I0
2.560 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_6_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_6_s0/I0
3.461 0.526 tINS RR 4 fifo_inst/Equal.wcount_r_6_s0/F
3.836 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_4_s0/I0
4.362 0.526 tINS RR 2 fifo_inst/Equal.wcount_r_4_s0/F
4.737 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I0
5.264 0.526 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
5.639 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
6.195 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
6.195 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
6.245 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
6.245 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
6.295 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
6.295 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
6.345 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
6.345 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
6.589 0.244 tINS RR 1 fifo_inst/rcnt_sub_6_s/SUM
6.964 0.375 tNET RR 1 fifo_inst/arempty_val_s3/I1
7.480 0.516 tINS RR 1 fifo_inst/arempty_val_s3/F
7.855 0.375 tNET RR 1 fifo_inst/arempty_val_s2/I3
8.118 0.262 tINS RR 1 fifo_inst/arempty_val_s2/F
8.493 0.375 tNET RR 1 fifo_inst/arempty_val_s0/I3
8.755 0.262 tINS RR 1 fifo_inst/arempty_val_s0/F
9.130 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 33 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.622, 52.798%; route: 3.750, 42.833%; tC2Q: 0.382, 4.369%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 3.880
Data Arrival Time 6.431
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 33 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I3
2.296 0.262 tINS RR 7 fifo_inst/rbin_num_next_5_s4/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I1
3.188 0.516 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
3.562 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
4.024 0.461 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
4.399 0.375 tNET RR 2 fifo_inst/n202_s0/I0
4.955 0.556 tINS RF 1 fifo_inst/n202_s0/COUT
4.955 0.000 tNET FF 2 fifo_inst/n203_s0/CIN
5.005 0.050 tINS FR 1 fifo_inst/n203_s0/COUT
5.005 0.000 tNET RR 2 fifo_inst/n204_s0/CIN
5.055 0.050 tINS RR 1 fifo_inst/n204_s0/COUT
5.055 0.000 tNET RR 2 fifo_inst/n205_s0/CIN
5.105 0.050 tINS RR 1 fifo_inst/n205_s0/COUT
5.105 0.000 tNET RR 2 fifo_inst/n206_s0/CIN
5.155 0.050 tINS RR 1 fifo_inst/n206_s0/COUT
5.530 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I0
6.056 0.526 tINS RR 1 fifo_inst/rempty_val_s1/F
6.431 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 33 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.049, 50.340%; route: 2.625, 43.344%; tC2Q: 0.382, 6.316%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 5.584
Data Arrival Time 4.727
Data Required Time 10.311
From fifo_inst/Full_s0
To fifo_inst/Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 48 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Full_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_2_s1/I0
1.659 0.526 tINS RR 21 fifo_inst/Equal.wgraynext_2_s1/F
2.034 0.375 tNET RR 1 fifo_inst/Equal.wgraynext_7_s1/I1
2.550 0.516 tINS RR 2 fifo_inst/Equal.wgraynext_7_s1/F
2.925 0.375 tNET RR 1 fifo_inst/wfull_val_s1/I0
3.451 0.526 tINS RR 1 fifo_inst/wfull_val_s1/F
3.826 0.375 tNET RR 1 fifo_inst/wfull_val_s0/I0
4.352 0.526 tINS RR 1 fifo_inst/wfull_val_s0/F
4.727 0.375 tNET RR 1 fifo_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 48 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Full_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.095, 48.133%; route: 1.875, 43.079%; tC2Q: 0.382, 8.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 5.912
Data Arrival Time 4.399
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_5_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 33 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I3
2.296 0.262 tINS RR 7 fifo_inst/rbin_num_next_5_s4/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I1
3.188 0.516 tINS RR 2 fifo_inst/rbin_num_next_6_s3/F
3.562 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_5_s1/I2
4.024 0.461 tINS RR 2 fifo_inst/Equal.rgraynext_5_s1/F
4.399 0.375 tNET RR 1 fifo_inst/Equal.rptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 33 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Equal.rptr_5_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Equal.rptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.766, 43.896%; route: 1.875, 46.598%; tC2Q: 0.382, 9.506%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 5.912
Data Arrival Time 4.399
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Equal.rptr_7_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 33 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I3
2.296 0.262 tINS RR 7 fifo_inst/rbin_num_next_5_s4/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_7_s3/I2
3.133 0.461 tINS RR 3 fifo_inst/rbin_num_next_7_s3/F
3.508 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_7_s0/I1
4.024 0.516 tINS RR 2 fifo_inst/Equal.rgraynext_7_s0/F
4.399 0.375 tNET RR 1 fifo_inst/Equal.rptr_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 33 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Equal.rptr_7_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Equal.rptr_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.766, 43.896%; route: 1.875, 46.598%; tC2Q: 0.382, 9.506%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%