Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\payload_fifo\temp\FIFO\fifo_define.v D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\payload_fifo\temp\FIFO\fifo_parameter.v D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\edc.v D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo.v D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo_top.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Thu Oct 10 10:00:21 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | payload_fifo |
Synthesis Process | Running parser: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.371s, Peak memory usage = 120.277MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.277MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.277MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.277MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 120.277MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.277MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.277MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.277MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.277MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 120.277MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.277MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.277MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.415s, Peak memory usage = 134.707MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 134.707MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 134.707MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.794s, Elapsed time = 0h 0m 0.843s, Peak memory usage = 134.707MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 70 |
I/O Buf | 70 |
    IBUF | 36 |
    OBUF | 34 |
Register | 112 |
    DFFRE | 112 |
LUT | 97 |
    LUT2 | 25 |
    LUT3 | 25 |
    LUT4 | 47 |
ALU | 13 |
    ALU | 13 |
BSRAM | 16 |
    SDPB | 16 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 110(97 LUT, 13 ALU) / 138240 | <1% |
Register | 112 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 112 / 139140 | <1% |
BSRAM | 16 / 340 | 5% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | RdClk_ibuf/I | ||
2 | WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 | WrClk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | RdClk | 100.000(MHz) | 128.329(MHz) | 9 | TOP |
2 | WrClk | 100.000(MHz) | 171.969(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.207 |
Data Arrival Time | 8.141 |
Data Required Time | 10.349 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Empty_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | fifo_inst/n28_s0/I0 |
1.786 | 0.579 | tINS | RR | 18 | fifo_inst/n28_s0/F |
2.199 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_3_s4/I0 |
2.778 | 0.579 | tINS | RR | 11 | fifo_inst/rbin_num_next_3_s4/F |
3.190 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_9_s1/I0 |
3.769 | 0.579 | tINS | RR | 7 | fifo_inst/Equal.rgraynext_9_s1/F |
4.181 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s1/I0 |
4.760 | 0.579 | tINS | RR | 4 | fifo_inst/Equal.rgraynext_11_s1/F |
5.173 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s0/I0 |
5.751 | 0.579 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_11_s0/F |
6.164 | 0.413 | tNET | RR | 2 | fifo_inst/n212_s0/I0 |
6.759 | 0.595 | tINS | RF | 1 | fifo_inst/n212_s0/COUT |
6.759 | 0.000 | tNET | FF | 2 | fifo_inst/n213_s0/CIN |
6.809 | 0.050 | tINS | FR | 1 | fifo_inst/n213_s0/COUT |
7.221 | 0.413 | tNET | RR | 1 | fifo_inst/rempty_val_s1/I2 |
7.729 | 0.507 | tINS | RR | 1 | fifo_inst/rempty_val_s1/F |
8.141 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
10.349 | -0.064 | tSu | 1 | fifo_inst/Empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 4.046, 52.353%; route: 3.300, 42.698%; tC2Q: 0.382, 4.949% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 4.185 |
Data Arrival Time | 6.164 |
Data Required Time | 10.349 |
From | fifo_inst/Full_s0 |
To | fifo_inst/Full_s0 |
Launch Clk | WrClk[R] |
Latch Clk | WrClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | WrClk | |||
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
0.000 | 0.000 | tINS | RR | 72 | WrClk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | fifo_inst/Full_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0 |
1.786 | 0.579 | tINS | RR | 20 | fifo_inst/Equal.wgraynext_2_s1/F |
2.199 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_12_s4/I0 |
2.778 | 0.579 | tINS | RR | 4 | fifo_inst/Equal.wbinnext_12_s4/F |
3.190 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_12_s3/I0 |
3.769 | 0.579 | tINS | RR | 3 | fifo_inst/Equal.wbinnext_12_s3/F |
4.181 | 0.413 | tNET | RR | 1 | fifo_inst/wfull_val_s1/I0 |
4.760 | 0.579 | tINS | RR | 1 | fifo_inst/wfull_val_s1/F |
5.173 | 0.413 | tNET | RR | 1 | fifo_inst/wfull_val_s0/I0 |
5.751 | 0.579 | tINS | RR | 1 | fifo_inst/wfull_val_s0/F |
6.164 | 0.413 | tNET | RR | 1 | fifo_inst/Full_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | WrClk | |||
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I |
10.000 | 0.000 | tINS | RR | 72 | WrClk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Full_s0/CLK |
10.349 | -0.064 | tSu | 1 | fifo_inst/Full_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 4.185 |
Data Arrival Time | 6.164 |
Data Required Time | 10.349 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Equal.rptr_11_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | fifo_inst/n28_s0/I0 |
1.786 | 0.579 | tINS | RR | 18 | fifo_inst/n28_s0/F |
2.199 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_3_s4/I0 |
2.778 | 0.579 | tINS | RR | 11 | fifo_inst/rbin_num_next_3_s4/F |
3.190 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_9_s1/I0 |
3.769 | 0.579 | tINS | RR | 7 | fifo_inst/Equal.rgraynext_9_s1/F |
4.181 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s1/I0 |
4.760 | 0.579 | tINS | RR | 4 | fifo_inst/Equal.rgraynext_11_s1/F |
5.173 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s0/I0 |
5.751 | 0.579 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_11_s0/F |
6.164 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_11_s0/CLK |
10.349 | -0.064 | tSu | 1 | fifo_inst/Equal.rptr_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 4.185 |
Data Arrival Time | 6.164 |
Data Required Time | 10.349 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Equal.rptr_12_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | fifo_inst/n28_s0/I0 |
1.786 | 0.579 | tINS | RR | 18 | fifo_inst/n28_s0/F |
2.199 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_3_s4/I0 |
2.778 | 0.579 | tINS | RR | 11 | fifo_inst/rbin_num_next_3_s4/F |
3.190 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_9_s1/I0 |
3.769 | 0.579 | tINS | RR | 7 | fifo_inst/Equal.rgraynext_9_s1/F |
4.181 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s1/I0 |
4.760 | 0.579 | tINS | RR | 4 | fifo_inst/Equal.rgraynext_11_s1/F |
5.173 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_12_s0/I0 |
5.751 | 0.579 | tINS | RR | 2 | fifo_inst/Equal.rgraynext_12_s0/F |
6.164 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_12_s0/CLK |
10.349 | -0.064 | tSu | 1 | fifo_inst/Equal.rptr_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 4.185 |
Data Arrival Time | 6.164 |
Data Required Time | 10.349 |
From | fifo_inst/Empty_s0 |
To | fifo_inst/Equal.rptr_13_s0 |
Launch Clk | RdClk[R] |
Latch Clk | RdClk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | RdClk | |||
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
0.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK |
0.795 | 0.382 | tC2Q | RR | 5 | fifo_inst/Empty_s0/Q |
1.207 | 0.413 | tNET | RR | 1 | fifo_inst/n28_s0/I0 |
1.786 | 0.579 | tINS | RR | 18 | fifo_inst/n28_s0/F |
2.199 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_3_s4/I0 |
2.778 | 0.579 | tINS | RR | 11 | fifo_inst/rbin_num_next_3_s4/F |
3.190 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_9_s1/I0 |
3.769 | 0.579 | tINS | RR | 7 | fifo_inst/Equal.rgraynext_9_s1/F |
4.181 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rgraynext_11_s1/I0 |
4.760 | 0.579 | tINS | RR | 4 | fifo_inst/Equal.rgraynext_11_s1/F |
5.173 | 0.413 | tNET | RR | 1 | fifo_inst/rbin_num_next_13_s2/I0 |
5.751 | 0.579 | tINS | RR | 2 | fifo_inst/rbin_num_next_13_s2/F |
6.164 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_13_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | RdClk | |||
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I |
10.000 | 0.000 | tINS | RR | 72 | RdClk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | fifo_inst/Equal.rptr_13_s0/CLK |
10.349 | -0.064 | tSu | 1 | fifo_inst/Equal.rptr_13_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 2.894, 50.315%; route: 2.475, 43.034%; tC2Q: 0.382, 6.651% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |