Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\dp_data_fifo_top\temp\FIFO\fifo_define.v
D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\dp_data_fifo_top\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW5AT-LV60PG484AC1/I0
Device GW5AT-60
Device Version B
Created Time Wed Oct 9 15:46:42 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module dp_data_fifo_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.37s, Peak memory usage = 120.566MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 120.566MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 120.566MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.566MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 120.566MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.566MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.566MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.566MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.566MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 120.566MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.566MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.566MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.367s, Peak memory usage = 135.000MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 135.000MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 135.000MB
Total Time and Memory Usage CPU time = 0h 0m 0.746s, Elapsed time = 0h 0m 0.79s, Peak memory usage = 135.000MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 198
I/O Buf 198
    IBUF 99
    OBUF 99
Register 44
    DFFSE 2
    DFFRE 42
LUT 107
    LUT2 31
    LUT3 30
    LUT4 46
ALU 28
    ALU 28
SSRAM 6
    RAM16S4 6
INV 2
    INV 2
BSRAM 3
    SDPB 3

Resource Utilization Summary

Resource Usage Utilization
Logic 173(109 LUT, 28 ALU, 6 RAM16) / 59904 <1%
Register 44 / 60783 <1%
  --Register as Latch 0 / 60783 0%
  --Register as FF 44 / 60783 <1%
BSRAM 3 / 118 3%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 117.561(MHz) 12 TOP
2 WrClk 100.000(MHz) 125.569(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.494
Data Arrival Time 8.509
Data Required Time 10.002
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 28 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 7 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s6/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Equal.rq1_wptr_0_s6/DO[3]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_6_s1/I0
2.560 0.526 tINS RR 4 fifo_inst/Equal.wcount_r_6_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_3_s0/I3
3.197 0.262 tINS RR 4 fifo_inst/Equal.wcount_r_3_s0/F
3.572 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I1
4.089 0.516 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.464 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.020 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.020 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.070 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.070 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.120 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.120 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.170 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.170 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.220 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.220 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.270 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.270 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.320 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.695 0.375 tNET RR 1 fifo_inst/n636_s6/I3
5.958 0.262 tINS RR 1 fifo_inst/n636_s6/F
6.333 0.375 tNET RR 1 fifo_inst/n636_s4/I0
6.859 0.526 tINS RR 1 fifo_inst/n636_s4/F
7.234 0.375 tNET RR 1 fifo_inst/n636_s2/I3
7.496 0.262 tINS RR 2 fifo_inst/n636_s2/F
7.871 0.375 tNET RR 1 fifo_inst/n633_s30/I3
8.134 0.262 tINS RR 1 fifo_inst/n633_s30/F
8.509 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/SET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 28 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.002 -0.373 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.001, 49.193%; route: 3.750, 46.104%; tC2Q: 0.382, 4.703%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 1.802
Data Arrival Time 8.509
Data Required Time 10.311
From fifo_inst/Equal.rq1_wptr_0_s2
To fifo_inst/Almost_Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 28 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.rq1_wptr_0_s2/CLK
0.757 0.382 tC2Q RR 7 fifo_inst/Equal.rq1_wptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.rq1_wptr_0_s6/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Equal.rq1_wptr_0_s6/DO[3]
2.034 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_6_s1/I0
2.560 0.526 tINS RR 4 fifo_inst/Equal.wcount_r_6_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_3_s0/I3
3.197 0.262 tINS RR 4 fifo_inst/Equal.wcount_r_3_s0/F
3.572 0.375 tNET RR 1 fifo_inst/Equal.wcount_r_2_s0/I1
4.089 0.516 tINS RR 1 fifo_inst/Equal.wcount_r_2_s0/F
4.464 0.375 tNET RR 2 fifo_inst/rcnt_sub_2_s/I0
5.020 0.556 tINS RF 1 fifo_inst/rcnt_sub_2_s/COUT
5.020 0.000 tNET FF 2 fifo_inst/rcnt_sub_3_s/CIN
5.070 0.050 tINS FR 1 fifo_inst/rcnt_sub_3_s/COUT
5.070 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.120 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.120 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.170 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.170 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.220 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.220 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.270 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.270 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.320 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.695 0.375 tNET RR 1 fifo_inst/n636_s6/I3
5.958 0.262 tINS RR 1 fifo_inst/n636_s6/F
6.333 0.375 tNET RR 1 fifo_inst/n636_s4/I0
6.859 0.526 tINS RR 1 fifo_inst/n636_s4/F
7.234 0.375 tNET RR 1 fifo_inst/n636_s2/I3
7.496 0.262 tINS RR 2 fifo_inst/n636_s2/F
7.871 0.375 tNET RR 1 fifo_inst/n636_s0/I3
8.134 0.262 tINS RR 1 fifo_inst/n636_s0/F
8.509 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 28 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.001, 49.193%; route: 3.750, 46.104%; tC2Q: 0.382, 4.703%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 2.036
Data Arrival Time 8.275
Data Required Time 10.311
From fifo_inst/Equal.wq1_rptr_0_s2
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 28 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.wq1_rptr_0_s2/CLK
0.757 0.382 tC2Q RR 7 fifo_inst/Equal.wq1_rptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.wq1_rptr_0_s6/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Equal.wq1_rptr_0_s6/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_6_s1/I0
2.560 0.526 tINS RR 4 fifo_inst/Equal.rcount_w_6_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_3_s0/I3
3.197 0.262 tINS RR 4 fifo_inst/Equal.rcount_w_3_s0/F
3.572 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_2_s0/I1
4.089 0.516 tINS RR 1 fifo_inst/Equal.rcount_w_2_s0/F
4.464 0.375 tNET RR 2 fifo_inst/wcnt_sub_2_s/I1
5.026 0.562 tINS RF 1 fifo_inst/wcnt_sub_2_s/COUT
5.026 0.000 tNET FF 2 fifo_inst/wcnt_sub_3_s/CIN
5.076 0.050 tINS FR 1 fifo_inst/wcnt_sub_3_s/COUT
5.076 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
5.126 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
5.126 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
5.176 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
5.176 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
5.226 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
5.470 0.244 tINS RR 1 fifo_inst/wcnt_sub_7_s/SUM
5.845 0.375 tNET RR 1 fifo_inst/n638_s32/I1
6.361 0.516 tINS RR 1 fifo_inst/n638_s32/F
6.736 0.375 tNET RR 1 fifo_inst/n638_s30/I3
6.999 0.262 tINS RR 2 fifo_inst/n638_s30/F
7.374 0.375 tNET RR 1 fifo_inst/n640_s0/I0
7.900 0.526 tINS RR 1 fifo_inst/n640_s0/F
8.275 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 28 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.143, 52.436%; route: 3.375, 42.722%; tC2Q: 0.382, 4.842%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.629
Data Arrival Time 7.374
Data Required Time 10.002
From fifo_inst/Equal.wq1_rptr_0_s2
To fifo_inst/Almost_Full_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 28 WrClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Equal.wq1_rptr_0_s2/CLK
0.757 0.382 tC2Q RR 7 fifo_inst/Equal.wq1_rptr_0_s2/Q
1.132 0.375 tNET RR 4 fifo_inst/Equal.wq1_rptr_0_s6/AD[0]
1.659 0.526 tINS RR 3 fifo_inst/Equal.wq1_rptr_0_s6/DO[2]
2.034 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_6_s1/I0
2.560 0.526 tINS RR 4 fifo_inst/Equal.rcount_w_6_s1/F
2.935 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_3_s0/I3
3.197 0.262 tINS RR 4 fifo_inst/Equal.rcount_w_3_s0/F
3.572 0.375 tNET RR 1 fifo_inst/Equal.rcount_w_2_s0/I1
4.089 0.516 tINS RR 1 fifo_inst/Equal.rcount_w_2_s0/F
4.464 0.375 tNET RR 2 fifo_inst/wcnt_sub_2_s/I1
5.026 0.562 tINS RF 1 fifo_inst/wcnt_sub_2_s/COUT
5.026 0.000 tNET FF 2 fifo_inst/wcnt_sub_3_s/CIN
5.076 0.050 tINS FR 1 fifo_inst/wcnt_sub_3_s/COUT
5.076 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
5.126 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
5.126 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
5.176 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
5.176 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
5.226 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
5.226 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
5.470 0.244 tINS RR 1 fifo_inst/wcnt_sub_7_s/SUM
5.845 0.375 tNET RR 1 fifo_inst/n638_s32/I1
6.361 0.516 tINS RR 1 fifo_inst/n638_s32/F
6.736 0.375 tNET RR 1 fifo_inst/n638_s30/I3
6.999 0.262 tINS RR 2 fifo_inst/n638_s30/F
7.374 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/SET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 28 WrClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Almost_Full_s0/CLK
10.002 -0.373 tSu 1 fifo_inst/Almost_Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.616, 51.670%; route: 3.000, 42.865%; tC2Q: 0.382, 5.465%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 3.980
Data Arrival Time 6.331
Data Required Time 10.311
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 28 RdClk_ibuf/O
0.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_inst/rbin_num_next_2_s4/I0
1.659 0.526 tINS RR 7 fifo_inst/rbin_num_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I3
2.296 0.262 tINS RR 6 fifo_inst/rbin_num_next_5_s4/F
2.671 0.375 tNET RR 1 fifo_inst/rbin_num_next_6_s3/I1
3.188 0.516 tINS RR 3 fifo_inst/rbin_num_next_6_s3/F
3.562 0.375 tNET RR 1 fifo_inst/Equal.rgraynext_6_s0/I0
4.089 0.526 tINS RR 2 fifo_inst/Equal.rgraynext_6_s0/F
4.464 0.375 tNET RR 2 fifo_inst/n443_s0/I0
5.020 0.556 tINS RF 1 fifo_inst/n443_s0/COUT
5.020 0.000 tNET FF 2 fifo_inst/n444_s0/CIN
5.070 0.050 tINS FR 1 fifo_inst/n444_s0/COUT
5.070 0.000 tNET RR 2 fifo_inst/n445_s0/CIN
5.120 0.050 tINS RR 1 fifo_inst/n445_s0/COUT
5.495 0.375 tNET RR 1 fifo_inst/rempty_val_s1/I2
5.956 0.461 tINS RR 1 fifo_inst/rempty_val_s1/F
6.331 0.375 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 28 RdClk_ibuf/O
10.375 0.375 tNET RR 1 fifo_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.949, 49.507%; route: 2.625, 44.071%; tC2Q: 0.382, 6.422%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%