Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy_top.v D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5AT-LV60UG225C1/I0 |
Device | GW5AT-60 |
Device Version | B |
Created Time | Tue Feb 25 09:52:20 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | USB3_0_PHY_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 122.711MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 122.711MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 122.711MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 122.711MB Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 122.711MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 122.711MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 122.711MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 122.711MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 122.711MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.184s, Peak memory usage = 122.711MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 122.711MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 122.711MB Tech-Mapping Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 154.672MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 154.672MB Generate output files: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 154.672MB |
Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 154.672MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 395 |
I/O Buf | 327 |
    IBUF | 130 |
    OBUF | 197 |
Register | 999 |
    DFFSE | 5 |
    DFFRE | 143 |
    DFFPE | 18 |
    DFFCE | 833 |
LUT | 2124 |
    LUT2 | 205 |
    LUT3 | 623 |
    LUT4 | 1296 |
ALU | 20 |
    ALU | 20 |
INV | 8 |
    INV | 8 |
BSRAM | 1 |
    SDPX9B | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2152(2132 LUT, 20 ALU) / 59904 | 4% |
Register | 999 / 60231 | 2% |
  --Register as Latch | 0 / 60231 | 0% |
  --Register as FF | 999 / 60231 | 2% |
BSRAM | 1 / 118 | <1% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | serdes_upar_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_upar_clk_i_ibuf/I | ||
2 | serdes_pcs_tx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
3 | ref_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | ref_clk_ibuf/I |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | serdes_upar_clk_i | 100.000(MHz) | 145.773(MHz) | 8 | TOP |
2 | serdes_pcs_tx_clk_i | 100.000(MHz) | 121.951(MHz) | 10 | TOP |
3 | ref_clk | 100.000(MHz) | 125.530(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 1.800 |
Data Arrival Time | 8.511 |
Data Required Time | 10.311 |
From | Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_21_s0 |
To | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_21_s0/CLK |
0.757 | 0.382 | tC2Q | RR | 5 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_21_s0/Q |
1.132 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s40/I0 |
1.659 | 0.526 | tINS | RR | 5 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s40/F |
2.034 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s25/I1 |
2.550 | 0.516 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s25/F |
2.925 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s17/I0 |
3.451 | 0.526 | tINS | RR | 3 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s17/F |
3.826 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s10/I0 |
4.352 | 0.526 | tINS | RR | 4 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s10/F |
4.727 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s26/I2 |
5.189 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s26/F |
5.564 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s11/I2 |
6.025 | 0.461 | tINS | RR | 2 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s11/F |
6.400 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s5/I3 |
6.662 | 0.262 | tINS | RR | 3 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s5/F |
7.037 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s3/I3 |
7.300 | 0.262 | tINS | RR | 2 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s3/F |
7.675 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1003_s2/I2 |
8.136 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1003_s2/F |
8.511 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CLK |
10.311 | -0.064 | tSu | 1 | Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 10 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 4.004, 49.209%; route: 3.750, 46.090%; tC2Q: 0.382, 4.701% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:Slack | 1.806 |
Data Arrival Time | 8.257 |
Data Required Time | 10.064 |
From | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3 |
To | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0 |
1.659 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F |
2.034 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I0 |
2.560 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F |
2.935 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/I1 |
3.451 | 0.516 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/F |
3.826 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2 |
4.287 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F |
4.662 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0 |
5.189 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F |
5.564 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0 |
6.090 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F |
6.465 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I0 |
6.991 | 0.526 | tINS | RR | 16 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F |
7.366 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1 |
7.882 | 0.516 | tINS | RR | 18 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F |
8.257 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/CLK |
10.064 | -0.311 | tSu | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 4.125, 52.331%; route: 3.375, 42.816%; tC2Q: 0.382, 4.853% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:Slack | 1.806 |
Data Arrival Time | 8.257 |
Data Required Time | 10.064 |
From | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3 |
To | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0 |
1.659 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F |
2.034 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I0 |
2.560 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F |
2.935 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/I1 |
3.451 | 0.516 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/F |
3.826 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2 |
4.287 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F |
4.662 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0 |
5.189 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F |
5.564 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0 |
6.090 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F |
6.465 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I0 |
6.991 | 0.526 | tINS | RR | 16 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F |
7.366 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1 |
7.882 | 0.516 | tINS | RR | 18 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F |
8.257 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1/CLK |
10.064 | -0.311 | tSu | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 4.125, 52.331%; route: 3.375, 42.816%; tC2Q: 0.382, 4.853% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:Slack | 1.806 |
Data Arrival Time | 8.257 |
Data Required Time | 10.064 |
From | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3 |
To | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0 |
1.659 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F |
2.034 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I0 |
2.560 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F |
2.935 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/I1 |
3.451 | 0.516 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/F |
3.826 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2 |
4.287 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F |
4.662 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0 |
5.189 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F |
5.564 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0 |
6.090 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F |
6.465 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I0 |
6.991 | 0.526 | tINS | RR | 16 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F |
7.366 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1 |
7.882 | 0.516 | tINS | RR | 18 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F |
8.257 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1/CLK |
10.064 | -0.311 | tSu | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 4.125, 52.331%; route: 3.375, 42.816%; tC2Q: 0.382, 4.853% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:Slack | 1.806 |
Data Arrival Time | 8.257 |
Data Required Time | 10.064 |
From | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3 |
To | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_27_s1 |
Launch Clk | serdes_pcs_tx_clk_i[R] |
Latch Clk | serdes_pcs_tx_clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
0.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
0.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK |
0.757 | 0.382 | tC2Q | RR | 6 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q |
1.132 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0 |
1.659 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F |
2.034 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I0 |
2.560 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F |
2.935 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/I1 |
3.451 | 0.516 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/F |
3.826 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2 |
4.287 | 0.461 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F |
4.662 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0 |
5.189 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F |
5.564 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0 |
6.090 | 0.526 | tINS | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F |
6.465 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I0 |
6.991 | 0.526 | tINS | RR | 16 | Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F |
7.366 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1 |
7.882 | 0.516 | tINS | RR | 18 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F |
8.257 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_27_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
10.000 | 0.000 | tINS | RR | 406 | serdes_pcs_tx_clk_i_ibuf/O |
10.375 | 0.375 | tNET | RR | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_27_s1/CLK |
10.064 | -0.311 | tSu | 1 | Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_27_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Arrival Data Path Delay: | cell: 4.125, 52.331%; route: 3.375, 42.816%; tC2Q: 0.382, 4.853% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |