Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\yuv_data_fifo\temp\FIFO\fifo_define.v
D:\MXY\project_202410\usb30_uvc_dp_60k\prj\src\yuv_data_fifo\temp\FIFO\fifo_parameter.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\edc.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo.v
D:\Gowin\Gowin_V1.9.10.01_x64\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Mon Oct 14 15:29:32 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module yuv_data_fifo
Synthesis Process Running parser:
    CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.39s, Peak memory usage = 120.227MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.227MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.227MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.227MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 120.227MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 120.227MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.227MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 120.227MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 120.227MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 120.227MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.227MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 120.227MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.552s, Peak memory usage = 134.848MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 134.848MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 134.848MB
Total Time and Memory Usage CPU time = 0h 0m 0.934s, Elapsed time = 0h 0m 1s, Peak memory usage = 134.848MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 102
I/O Buf 102
    IBUF 38
    OBUF 64
Register 150
    DFFPE 1
    DFFCE 149
LUT 139
    LUT2 31
    LUT3 43
    LUT4 65
ALU 44
    ALU 44
BSRAM 32
    SDPB 32

Resource Utilization Summary

Resource Usage Utilization
Logic 183(139 LUT, 44 ALU) / 138240 <1%
Register 150 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 150 / 139140 <1%
BSRAM 32 / 340 10%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 RdClk Base 10.000 100.0 0.000 5.000 RdClk_ibuf/I
2 WrClk Base 10.000 100.0 0.000 5.000 WrClk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 RdClk 100.000(MHz) 134.976(MHz) 9 TOP
2 WrClk 100.000(MHz) 153.227(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.591
Data Arrival Time 7.758
Data Required Time 10.349
From fifo_inst/Empty_s0
To fifo_inst/Empty_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 107 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
0.795 0.382 tC2Q RR 6 fifo_inst/Empty_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_2_s1/I0
1.786 0.579 tINS RR 7 fifo_inst/Equal.rgraynext_2_s1/F
2.199 0.413 tNET RR 1 fifo_inst/rbin_num_next_5_s4/I3
2.487 0.289 tINS RR 10 fifo_inst/rbin_num_next_5_s4/F
2.900 0.413 tNET RR 1 fifo_inst/rbin_num_next_6_s4/I1
3.468 0.567 tINS RR 1 fifo_inst/rbin_num_next_6_s4/F
3.880 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_12_s1/I2
4.388 0.507 tINS RR 5 fifo_inst/Equal.rgraynext_12_s1/F
4.800 0.413 tNET RR 1 fifo_inst/Equal.rgraynext_12_s0/I1
5.368 0.567 tINS RR 2 fifo_inst/Equal.rgraynext_12_s0/F
5.780 0.413 tNET RR 2 fifo_inst/n217_s0/I0
6.375 0.595 tINS RF 1 fifo_inst/n217_s0/COUT
6.375 0.000 tNET FF 2 fifo_inst/n218_s0/CIN
6.425 0.050 tINS FR 1 fifo_inst/n218_s0/COUT
6.838 0.413 tNET RR 1 fifo_inst/rempty_val_s1/I2
7.345 0.507 tINS RR 1 fifo_inst/rempty_val_s1/F
7.758 0.413 tNET RR 1 fifo_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 107 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Empty_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.662, 49.863%; route: 3.300, 44.929%; tC2Q: 0.382, 5.208%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 3.474
Data Arrival Time 6.875
Data Required Time 10.349
From fifo_inst/Equal.wq2_rptr_12_s0
To fifo_inst/Wnum_14_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 107 WrClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.wq2_rptr_12_s0/CLK
0.795 0.382 tC2Q RR 3 fifo_inst/Equal.wq2_rptr_12_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_12_s1/I0
1.786 0.579 tINS RR 3 fifo_inst/Equal.rcount_w_12_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_10_s0/I2
2.706 0.507 tINS RR 3 fifo_inst/Equal.rcount_w_10_s0/F
3.119 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_8_s0/I2
3.626 0.507 tINS RR 4 fifo_inst/Equal.rcount_w_8_s0/F
4.039 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_1_s0/I1
4.606 0.567 tINS RR 1 fifo_inst/Equal.rcount_w_1_s0/F
5.019 0.413 tNET RR 2 fifo_inst/wcnt_sub_1_s/I1
5.619 0.600 tINS RF 1 fifo_inst/wcnt_sub_1_s/COUT
5.619 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
5.669 0.050 tINS FR 1 fifo_inst/wcnt_sub_2_s/COUT
5.669 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
5.719 0.050 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
5.719 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
5.769 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
5.769 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
5.819 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
5.819 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
5.869 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
5.869 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
5.919 0.050 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
5.919 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
5.969 0.050 tINS RR 1 fifo_inst/wcnt_sub_8_s/COUT
5.969 0.000 tNET RR 2 fifo_inst/wcnt_sub_9_s/CIN
6.019 0.050 tINS RR 1 fifo_inst/wcnt_sub_9_s/COUT
6.019 0.000 tNET RR 2 fifo_inst/wcnt_sub_10_s/CIN
6.069 0.050 tINS RR 1 fifo_inst/wcnt_sub_10_s/COUT
6.069 0.000 tNET RR 2 fifo_inst/wcnt_sub_11_s/CIN
6.119 0.050 tINS RR 1 fifo_inst/wcnt_sub_11_s/COUT
6.119 0.000 tNET RR 2 fifo_inst/wcnt_sub_12_s/CIN
6.169 0.050 tINS RR 1 fifo_inst/wcnt_sub_12_s/COUT
6.169 0.000 tNET RR 2 fifo_inst/wcnt_sub_13_s/CIN
6.219 0.050 tINS RR 1 fifo_inst/wcnt_sub_13_s/COUT
6.219 0.000 tNET RR 2 fifo_inst/wcnt_sub_14_s/CIN
6.463 0.244 tINS RR 1 fifo_inst/wcnt_sub_14_s/SUM
6.875 0.413 tNET RR 1 fifo_inst/Wnum_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 107 WrClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Wnum_14_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Wnum_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.605, 55.783%; route: 2.475, 38.298%; tC2Q: 0.382, 5.919%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 3.479
Data Arrival Time 6.870
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_12_s0
To fifo_inst/Rnum_14_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 107 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_12_s0/CLK
0.795 0.382 tC2Q RR 3 fifo_inst/Equal.rq2_wptr_12_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_12_s1/I0
1.786 0.579 tINS RR 3 fifo_inst/Equal.wcount_r_12_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_10_s0/I2
2.706 0.507 tINS RR 3 fifo_inst/Equal.wcount_r_10_s0/F
3.119 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I2
3.626 0.507 tINS RR 4 fifo_inst/Equal.wcount_r_8_s0/F
4.039 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I1
4.606 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_1_s0/F
5.019 0.413 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
5.614 0.595 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.614 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.664 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
5.664 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.714 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.714 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.764 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.764 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.814 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.814 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.864 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.864 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.914 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.914 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.964 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.964 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.014 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.014 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.064 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.064 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.114 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.114 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.164 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
6.164 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.214 0.050 tINS RR 1 fifo_inst/rcnt_sub_13_s/COUT
6.214 0.000 tNET RR 2 fifo_inst/rcnt_sub_14_s/CIN
6.458 0.244 tINS RR 1 fifo_inst/rcnt_sub_14_s/SUM
6.870 0.413 tNET RR 1 fifo_inst/Rnum_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 107 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_14_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.600, 55.749%; route: 2.475, 38.328%; tC2Q: 0.382, 5.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 3.524
Data Arrival Time 6.825
Data Required Time 10.349
From fifo_inst/Equal.wq2_rptr_12_s0
To fifo_inst/Wnum_13_s0
Launch Clk WrClk[R]
Latch Clk WrClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 WrClk
0.000 0.000 tCL RR 1 WrClk_ibuf/I
0.000 0.000 tINS RR 107 WrClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.wq2_rptr_12_s0/CLK
0.795 0.382 tC2Q RR 3 fifo_inst/Equal.wq2_rptr_12_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_12_s1/I0
1.786 0.579 tINS RR 3 fifo_inst/Equal.rcount_w_12_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_10_s0/I2
2.706 0.507 tINS RR 3 fifo_inst/Equal.rcount_w_10_s0/F
3.119 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_8_s0/I2
3.626 0.507 tINS RR 4 fifo_inst/Equal.rcount_w_8_s0/F
4.039 0.413 tNET RR 1 fifo_inst/Equal.rcount_w_1_s0/I1
4.606 0.567 tINS RR 1 fifo_inst/Equal.rcount_w_1_s0/F
5.019 0.413 tNET RR 2 fifo_inst/wcnt_sub_1_s/I1
5.619 0.600 tINS RF 1 fifo_inst/wcnt_sub_1_s/COUT
5.619 0.000 tNET FF 2 fifo_inst/wcnt_sub_2_s/CIN
5.669 0.050 tINS FR 1 fifo_inst/wcnt_sub_2_s/COUT
5.669 0.000 tNET RR 2 fifo_inst/wcnt_sub_3_s/CIN
5.719 0.050 tINS RR 1 fifo_inst/wcnt_sub_3_s/COUT
5.719 0.000 tNET RR 2 fifo_inst/wcnt_sub_4_s/CIN
5.769 0.050 tINS RR 1 fifo_inst/wcnt_sub_4_s/COUT
5.769 0.000 tNET RR 2 fifo_inst/wcnt_sub_5_s/CIN
5.819 0.050 tINS RR 1 fifo_inst/wcnt_sub_5_s/COUT
5.819 0.000 tNET RR 2 fifo_inst/wcnt_sub_6_s/CIN
5.869 0.050 tINS RR 1 fifo_inst/wcnt_sub_6_s/COUT
5.869 0.000 tNET RR 2 fifo_inst/wcnt_sub_7_s/CIN
5.919 0.050 tINS RR 1 fifo_inst/wcnt_sub_7_s/COUT
5.919 0.000 tNET RR 2 fifo_inst/wcnt_sub_8_s/CIN
5.969 0.050 tINS RR 1 fifo_inst/wcnt_sub_8_s/COUT
5.969 0.000 tNET RR 2 fifo_inst/wcnt_sub_9_s/CIN
6.019 0.050 tINS RR 1 fifo_inst/wcnt_sub_9_s/COUT
6.019 0.000 tNET RR 2 fifo_inst/wcnt_sub_10_s/CIN
6.069 0.050 tINS RR 1 fifo_inst/wcnt_sub_10_s/COUT
6.069 0.000 tNET RR 2 fifo_inst/wcnt_sub_11_s/CIN
6.119 0.050 tINS RR 1 fifo_inst/wcnt_sub_11_s/COUT
6.119 0.000 tNET RR 2 fifo_inst/wcnt_sub_12_s/CIN
6.169 0.050 tINS RR 1 fifo_inst/wcnt_sub_12_s/COUT
6.169 0.000 tNET RR 2 fifo_inst/wcnt_sub_13_s/CIN
6.413 0.244 tINS RR 1 fifo_inst/wcnt_sub_13_s/SUM
6.825 0.413 tNET RR 1 fifo_inst/Wnum_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 WrClk
10.000 0.000 tCL RR 1 WrClk_ibuf/I
10.000 0.000 tINS RR 107 WrClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Wnum_13_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Wnum_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.555, 55.439%; route: 2.475, 38.596%; tC2Q: 0.382, 5.965%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 3.529
Data Arrival Time 6.820
Data Required Time 10.349
From fifo_inst/Equal.rq2_wptr_12_s0
To fifo_inst/Rnum_13_s0
Launch Clk RdClk[R]
Latch Clk RdClk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 RdClk
0.000 0.000 tCL RR 1 RdClk_ibuf/I
0.000 0.000 tINS RR 107 RdClk_ibuf/O
0.413 0.413 tNET RR 1 fifo_inst/Equal.rq2_wptr_12_s0/CLK
0.795 0.382 tC2Q RR 3 fifo_inst/Equal.rq2_wptr_12_s0/Q
1.207 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_12_s1/I0
1.786 0.579 tINS RR 3 fifo_inst/Equal.wcount_r_12_s1/F
2.199 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_10_s0/I2
2.706 0.507 tINS RR 3 fifo_inst/Equal.wcount_r_10_s0/F
3.119 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_8_s0/I2
3.626 0.507 tINS RR 4 fifo_inst/Equal.wcount_r_8_s0/F
4.039 0.413 tNET RR 1 fifo_inst/Equal.wcount_r_1_s0/I1
4.606 0.567 tINS RR 1 fifo_inst/Equal.wcount_r_1_s0/F
5.019 0.413 tNET RR 2 fifo_inst/rcnt_sub_1_s/I0
5.614 0.595 tINS RF 1 fifo_inst/rcnt_sub_1_s/COUT
5.614 0.000 tNET FF 2 fifo_inst/rcnt_sub_2_s/CIN
5.664 0.050 tINS FR 1 fifo_inst/rcnt_sub_2_s/COUT
5.664 0.000 tNET RR 2 fifo_inst/rcnt_sub_3_s/CIN
5.714 0.050 tINS RR 1 fifo_inst/rcnt_sub_3_s/COUT
5.714 0.000 tNET RR 2 fifo_inst/rcnt_sub_4_s/CIN
5.764 0.050 tINS RR 1 fifo_inst/rcnt_sub_4_s/COUT
5.764 0.000 tNET RR 2 fifo_inst/rcnt_sub_5_s/CIN
5.814 0.050 tINS RR 1 fifo_inst/rcnt_sub_5_s/COUT
5.814 0.000 tNET RR 2 fifo_inst/rcnt_sub_6_s/CIN
5.864 0.050 tINS RR 1 fifo_inst/rcnt_sub_6_s/COUT
5.864 0.000 tNET RR 2 fifo_inst/rcnt_sub_7_s/CIN
5.914 0.050 tINS RR 1 fifo_inst/rcnt_sub_7_s/COUT
5.914 0.000 tNET RR 2 fifo_inst/rcnt_sub_8_s/CIN
5.964 0.050 tINS RR 1 fifo_inst/rcnt_sub_8_s/COUT
5.964 0.000 tNET RR 2 fifo_inst/rcnt_sub_9_s/CIN
6.014 0.050 tINS RR 1 fifo_inst/rcnt_sub_9_s/COUT
6.014 0.000 tNET RR 2 fifo_inst/rcnt_sub_10_s/CIN
6.064 0.050 tINS RR 1 fifo_inst/rcnt_sub_10_s/COUT
6.064 0.000 tNET RR 2 fifo_inst/rcnt_sub_11_s/CIN
6.114 0.050 tINS RR 1 fifo_inst/rcnt_sub_11_s/COUT
6.114 0.000 tNET RR 2 fifo_inst/rcnt_sub_12_s/CIN
6.164 0.050 tINS RR 1 fifo_inst/rcnt_sub_12_s/COUT
6.164 0.000 tNET RR 2 fifo_inst/rcnt_sub_13_s/CIN
6.408 0.244 tINS RR 1 fifo_inst/rcnt_sub_13_s/SUM
6.820 0.413 tNET RR 1 fifo_inst/Rnum_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 RdClk
10.000 0.000 tCL RR 1 RdClk_ibuf/I
10.000 0.000 tINS RR 107 RdClk_ibuf/O
10.413 0.413 tNET RR 1 fifo_inst/Rnum_13_s0/CLK
10.349 -0.064 tSu 1 fifo_inst/Rnum_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.550, 55.403%; route: 2.475, 38.627%; tC2Q: 0.382, 5.970%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%