Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\impl\gwsynthesis\prj.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\top.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\top.sdc
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AT-LV60UG225C1/I0
Device GW5AT-60
Device Version B
Created Time Fri Feb 28 10:51:44 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.855V 0C C1/I0
Hold Delay Model Fast 0.945V 85C C1/I0
Numbers of Paths Analyzed 15181
Numbers of Endpoints Analyzed 22080
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 pclk Base 8.000 125.000 0.000 4.000 pclk
2 sys_clk_p Base 5.000 200.000 0.000 2.500 sys_clk_p
3 drp_clk_o Base 10.000 100.000 0.000 5.000 SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]
4 Inst_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Generated 8.000 125.000 0.000 4.000 Inst_sys_clk_in/I sys_clk_p Inst_Gowin_PLL/PLLA_inst/CLKOUT0

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pclk 125.000(MHz) 125.039(MHz) 9 TOP
2 drp_clk_o 100.000(MHz) 120.409(MHz) 8 TOP

No timing paths to get frequency of sys_clk_p!

No timing paths to get frequency of Inst_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
pclk Setup 0.000 0
pclk Hold 0.000 0
sys_clk_p Setup 0.000 0
sys_clk_p Hold 0.000 0
drp_clk_o Setup 0.000 0
drp_clk_o Hold 0.000 0
Inst_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Setup 0.000 0
Inst_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.003 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[9] pclk:[R] pclk:[R] 8.000 0.000 8.070
2 0.003 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/DataTransfer_inst/payload_fifo_b_has_data_len_13_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.181
3 0.020 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_5_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.164
4 0.023 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CE pclk:[R] pclk:[R] 8.000 -0.019 7.685
5 0.029 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_1_s0/D pclk:[R] pclk:[R] 8.000 -0.009 7.916
6 0.030 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/D pclk:[R] pclk:[R] 8.000 -0.019 7.925
7 0.037 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1/CE pclk:[R] pclk:[R] 8.000 0.009 7.643
8 0.045 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[8] pclk:[R] pclk:[R] 8.000 0.000 8.028
9 0.055 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[7] pclk:[R] pclk:[R] 8.000 0.000 8.017
10 0.065 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/D pclk:[R] pclk:[R] 8.000 0.000 7.871
11 0.068 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_3_s/ADB[7] pclk:[R] pclk:[R] 8.000 -0.009 8.014
12 0.087 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/reset_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/ADB[3] pclk:[R] pclk:[R] 8.000 0.000 7.986
13 0.107 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_9_s0/D pclk:[R] pclk:[R] 8.000 -0.009 7.839
14 0.111 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/ADB[9] pclk:[R] pclk:[R] 8.000 -0.019 7.980
15 0.135 SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_9_s0/D pclk:[R] pclk:[R] 8.000 -0.019 7.820
16 0.141 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_1_s0/CE pclk:[R] pclk:[R] 8.000 0.514 7.034
17 0.141 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_2_s0/CE pclk:[R] pclk:[R] 8.000 0.514 7.034
18 0.141 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_3_s0/CE pclk:[R] pclk:[R] 8.000 0.514 7.034
19 0.141 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_4_s0/CE pclk:[R] pclk:[R] 8.000 0.514 7.034
20 0.143 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_7_s0/CE pclk:[R] pclk:[R] 8.000 0.514 7.032
21 0.148 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_0_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.037
22 0.148 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_6_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.037
23 0.148 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_13_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.037
24 0.148 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_14_s0/CE pclk:[R] pclk:[R] 8.000 0.504 7.037
25 0.157 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_5_s0/CE pclk:[R] pclk:[R] 8.000 0.495 7.037

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.186 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_6_s0/CE pclk:[R] pclk:[R] 0.000 -0.197 0.314
2 0.186 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_22_s0/CE pclk:[R] pclk:[R] 0.000 -0.197 0.314
3 0.192 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_0_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[0] pclk:[R] pclk:[R] 0.000 -0.004 0.246
4 0.194 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.004 0.240
5 0.194 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[1] pclk:[R] pclk:[R] 0.000 0.004 0.240
6 0.197 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.004 0.243
7 0.197 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s2/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[1] pclk:[R] pclk:[R] 0.000 0.004 0.243
8 0.197 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_0_s2/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[0] pclk:[R] pclk:[R] 0.000 0.004 0.243
9 0.197 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_1_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[1] pclk:[R] pclk:[R] 0.000 0.004 0.243
10 0.202 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.000 0.252
11 0.205 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/WAD[1] pclk:[R] pclk:[R] 0.000 0.000 0.255
12 0.206 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.000 0.256
13 0.206 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[2] pclk:[R] pclk:[R] 0.000 -0.004 0.260
14 0.206 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[0] pclk:[R] pclk:[R] 0.000 -0.004 0.260
15 0.208 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.000 0.258
16 0.208 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_1_s/WAD[2] pclk:[R] pclk:[R] 0.000 0.000 0.258
17 0.210 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/WAD[0] pclk:[R] pclk:[R] 0.000 0.000 0.260
18 0.214 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_3_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[3] pclk:[R] pclk:[R] 0.000 0.000 0.264
19 0.230 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3p/phy_power_down_1_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/port_tx_elecidle_s0/D pclk:[R] pclk:[R] 0.000 -0.197 0.452
20 0.232 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[9] pclk:[R] pclk:[R] 0.000 0.000 0.269
21 0.237 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[7] pclk:[R] pclk:[R] 0.000 0.004 0.270
22 0.238 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[9] pclk:[R] pclk:[R] 0.000 0.004 0.271
23 0.239 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[6] pclk:[R] pclk:[R] 0.000 0.004 0.272
24 0.239 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[6] pclk:[R] pclk:[R] 0.000 0.000 0.276
25 0.241 UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/Q UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[7] pclk:[R] pclk:[R] 0.000 0.008 0.270

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.459 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_0_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.689
2 0.459 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_3_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.689
3 0.459 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_5_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.689
4 0.459 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_6_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.689
5 0.459 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_6_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.689
6 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_2_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
7 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_3_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
8 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_4_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
9 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_5_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
10 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_7_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
11 0.634 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_8_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.505
12 0.639 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_2_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.509
13 0.639 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_3_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.509
14 0.639 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_5_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.509
15 0.639 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_6_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.509
16 0.639 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_7_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.509
17 0.643 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_ready_s3/PRESET pclk:[R] pclk:[R] 8.000 0.504 6.505
18 0.643 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_0_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.505
19 0.643 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_hasdata_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.505
20 0.662 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_4_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.486
21 0.662 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_1_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.486
22 0.670 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/rd_setup_pkt_dval_d_s0/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.469
23 0.670 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/packet_setup_latch_act_s0/CLEAR pclk:[R] pclk:[R] 8.000 0.514 6.469
24 0.671 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_1_s1/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.478
25 0.671 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/dev_address_4_s0/CLEAR pclk:[R] pclk:[R] 8.000 0.504 6.477

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.406 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_1_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.357
2 0.467 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_4_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.414
3 0.467 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_10_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.414
4 0.467 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.414
5 0.468 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.415
6 0.468 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_8_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.415
7 0.500 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_0_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.451
8 0.500 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_5_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.451
9 0.502 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_3_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.453
10 0.512 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_1_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.459
11 0.512 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_3_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.459
12 0.512 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_7_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.459
13 0.551 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_5_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.498
14 0.551 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_9_s0/PRESET pclk:[R] pclk:[R] 0.000 0.000 0.498
15 0.555 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_7_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.506
16 0.555 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.506
17 0.597 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_0_s0/PRESET pclk:[R] pclk:[R] 0.000 0.004 0.540
18 0.597 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_2_s0/PRESET pclk:[R] pclk:[R] 0.000 0.004 0.540
19 0.597 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_4_s0/PRESET pclk:[R] pclk:[R] 0.000 0.004 0.540
20 0.597 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_10_s0/PRESET pclk:[R] pclk:[R] 0.000 0.004 0.540
21 0.597 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_11_s0/PRESET pclk:[R] pclk:[R] 0.000 0.004 0.540
22 0.602 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_15_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.553
23 0.602 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_8_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.553
24 0.611 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_14_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.562
25 0.626 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_2_s0/PRESET pclk:[R] pclk:[R] 0.000 -0.004 0.577

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 1.272 2.272 1.000 Low Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s
2 1.272 2.272 1.000 Low Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s
3 1.272 2.272 1.000 Low Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_1_s
4 1.272 2.272 1.000 Low Pulse Width pclk UserLayer_top_inst/DataTransfer_inst/payload_fifo_a/fifo_inst/Equal.mem_Equal.mem_0_0_s
5 1.272 2.272 1.000 Low Pulse Width pclk UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_0_s
6 1.272 2.272 1.000 Low Pulse Width pclk UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s
7 1.272 2.272 1.000 Low Pulse Width pclk UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_1_s
8 1.272 2.272 1.000 Low Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_2_s
9 1.276 2.276 1.000 High Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s
10 1.276 2.276 1.000 High Pulse Width pclk USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.003
Data Arrival Time 10.162
Data Required Time 10.165
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/CLK
2.460 0.368 tC2Q RF 43 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q
3.004 0.544 tNET FF 4 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/RAD[0]
3.530 0.526 tINS FR 3 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/DO[0]
3.690 0.160 tNET RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/I1
4.211 0.521 tINS RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/F
4.459 0.248 tNET RR 1 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/I0
4.724 0.265 tINS RR 2 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/F
5.054 0.330 tNET RR 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/I0
5.344 0.290 tINS RF 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/F
5.670 0.326 tNET FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/I1
5.960 0.290 tINS FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/F
6.102 0.142 tNET FF 1 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/I0
6.517 0.415 tINS FR 12 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/F
7.081 0.564 tNET RR 1 R50C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15194_s12/I1
7.344 0.262 tINS RR 4 R50C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15194_s12/F
7.734 0.390 tNET RR 1 R48C72[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_6_s0/I0
8.024 0.290 tINS RF 5 R48C72[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_6_s0/F
10.163 2.139 tNET FF 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/CLKB
10.165 0.072 tSu 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 2.860, 35.440%; route: 4.843, 60.006%; tC2Q: 0.368, 4.554%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path2

Path Summary:

Slack 0.003
Data Arrival Time 9.788
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/DataTransfer_inst/payload_fifo_b_has_data_len_13_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.831 3.236 tNET RR 1 R48C99[3][A] UserLayer_top_inst/DataTransfer_inst/n2719_s0/I0
9.246 0.415 tINS RR 2 R48C99[3][A] UserLayer_top_inst/DataTransfer_inst/n2719_s0/F
9.788 0.541 tNET RR 1 R46C102[2][A] UserLayer_top_inst/DataTransfer_inst/payload_fifo_b_has_data_len_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R46C102[2][A] UserLayer_top_inst/DataTransfer_inst/payload_fifo_b_has_data_len_13_s0/CLK
9.791 -0.311 tSu 1 R46C102[2][A] UserLayer_top_inst/DataTransfer_inst/payload_fifo_b_has_data_len_13_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.931, 12.968%; route: 5.868, 81.706%; tC2Q: 0.382, 5.326%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path3

Path Summary:

Slack 0.020
Data Arrival Time 9.771
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R52C96[3][B] UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_15_s2/I3
9.237 0.415 tINS RR 16 R52C96[3][B] UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_15_s2/F
9.771 0.534 tNET RR 1 R50C94[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R50C94[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_5_s0/CLK
9.791 -0.311 tSu 1 R50C94[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_resp_len_latch_5_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.931, 12.998%; route: 5.851, 81.663%; tC2Q: 0.382, 5.339%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path4

Path Summary:

Slack 0.023
Data Arrival Time 9.777
Data Required Time 9.800
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R16C75[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/CLK
2.475 0.382 tC2Q RR 7 R16C75[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q
3.210 0.735 tNET RR 1 R16C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s9/I2
3.500 0.290 tINS RF 5 R16C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s9/F
3.652 0.153 tNET FF 1 R15C78[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s20/I2
3.915 0.262 tINS FR 5 R15C78[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s20/F
4.270 0.355 tNET RR 1 R14C79[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I3
4.685 0.415 tINS RR 3 R14C79[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
5.655 0.970 tNET RR 1 R9C79[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s13/I3
6.181 0.526 tINS RR 3 R9C79[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s13/F
6.534 0.352 tNET RR 1 R8C80[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I2
6.796 0.262 tINS RR 1 R8C80[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
6.954 0.157 tNET RR 1 R8C79[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I1
7.480 0.526 tINS RR 2 R8C79[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
8.327 0.848 tNET RR 1 R14C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.742 0.415 tINS RR 7 R14C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
9.777 1.035 tNET RR 1 R7C81[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 R7C81[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CLK
9.800 -0.311 tSu 1 R7C81[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1

Path Statistics:

Clock Skew 0.019
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 2.697, 35.101%; route: 4.605, 59.922%; tC2Q: 0.382, 4.977%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Path5

Path Summary:

Slack 0.029
Data Arrival Time 10.009
Data Required Time 10.038
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/CLK
2.460 0.368 tC2Q RF 21 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q
4.040 1.580 tNET FF 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/I1
4.556 0.516 tINS FR 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/F
4.714 0.157 tNET RR 1 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/I0
5.129 0.415 tINS RR 8 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/F
5.990 0.861 tNET RR 1 R12C85[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s13/I0
6.405 0.415 tINS RR 23 R12C85[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s13/F
7.150 0.745 tNET RR 1 R21C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s4/I3
7.647 0.498 tINS RR 1 R21C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s4/F
7.650 0.003 tNET RR 1 R21C75[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s2/I0
8.111 0.461 tINS RR 1 R21C75[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s2/F
8.649 0.537 tNET RR 1 R20C78[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s1/I0
9.110 0.461 tINS RR 1 R20C78[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s1/F
9.493 0.382 tNET RR 1 R20C82[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s6/I2
10.009 0.516 tINS RR 1 R20C82[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_4_s6/F
10.009 0.000 tNET RR 1 R20C82[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R20C82[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_1_s0/CLK
10.038 -0.064 tSu 1 R20C82[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_1_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 3.283, 41.465%; route: 4.266, 53.892%; tC2Q: 0.368, 4.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path6

Path Summary:

Slack 0.030
Data Arrival Time 10.017
Data Required Time 10.047
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R16C75[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/CLK
2.475 0.382 tC2Q RR 7 R16C75[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q
3.210 0.735 tNET RR 1 R16C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s9/I2
3.500 0.290 tINS RF 5 R16C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s9/F
3.652 0.153 tNET FF 1 R15C78[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s20/I2
3.915 0.262 tINS FR 5 R15C78[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s20/F
4.270 0.355 tNET RR 1 R14C79[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I3
4.685 0.415 tINS RR 3 R14C79[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
5.655 0.970 tNET RR 1 R9C79[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s13/I3
6.181 0.526 tINS RR 3 R9C79[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s13/F
6.534 0.352 tNET RR 1 R8C80[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I2
6.796 0.262 tINS RR 1 R8C80[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
6.954 0.157 tNET RR 1 R8C79[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I1
7.480 0.526 tINS RR 2 R8C79[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
8.327 0.848 tNET RR 1 R14C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.742 0.415 tINS RR 7 R14C75[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
10.017 1.275 tNET RR 1 R17C85[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 R17C85[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/CLK
10.047 -0.064 tSu 1 R17C85[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 2.697, 34.038%; route: 4.845, 61.136%; tC2Q: 0.382, 4.826%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Path7

Path Summary:

Slack 0.037
Data Arrival Time 9.744
Data Required Time 9.781
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.102 2.102 tNET RR 1 R18C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/CLK
2.469 0.368 tC2Q RF 4 R18C78[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/Q
2.973 0.504 tNET FF 1 R18C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I2
3.494 0.521 tINS FR 1 R18C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
3.818 0.324 tNET RR 1 R21C77[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I0
4.081 0.262 tINS RR 1 R21C77[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
4.238 0.157 tNET RR 1 R21C76[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/I1
4.501 0.262 tINS RR 1 R21C76[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s103/F
4.658 0.157 tNET RR 1 R20C76[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
5.156 0.498 tINS RR 1 R20C76[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
5.669 0.514 tNET RR 1 R17C75[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
6.186 0.516 tINS RR 1 R17C75[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
6.758 0.572 tNET RR 1 R12C75[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
7.284 0.526 tINS RR 1 R12C75[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
7.667 0.382 tNET RR 1 R15C75[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I0
7.929 0.262 tINS RR 16 R15C75[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
8.657 0.728 tNET RR 1 R20C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
8.922 0.265 tINS RR 18 R20C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
9.744 0.822 tNET RR 1 R15C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R15C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1/CLK
9.781 -0.311 tSu 1 R15C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1

Path Statistics:

Clock Skew -0.009
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%
Arrival Data Path Delay cell: 3.114, 40.743%; route: 4.161, 54.449%; tC2Q: 0.368, 4.809%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path8

Path Summary:

Slack 0.045
Data Arrival Time 10.120
Data Required Time 10.165
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/CLK
2.460 0.368 tC2Q RF 43 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q
3.004 0.544 tNET FF 4 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/RAD[0]
3.530 0.526 tINS FR 3 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/DO[0]
3.690 0.160 tNET RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/I1
4.211 0.521 tINS RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/F
4.459 0.248 tNET RR 1 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/I0
4.724 0.265 tINS RR 2 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/F
5.054 0.330 tNET RR 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/I0
5.344 0.290 tINS RF 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/F
5.670 0.326 tNET FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/I1
5.960 0.290 tINS FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/F
6.102 0.142 tNET FF 1 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/I0
6.517 0.415 tINS FR 12 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/F
7.059 0.541 tNET RR 1 R49C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_5_s2/I0
7.349 0.290 tINS RF 3 R49C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_5_s2/F
7.501 0.153 tNET FF 1 R49C72[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_5_s0/I3
8.017 0.516 tINS FR 5 R49C72[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_5_s0/F
10.120 2.103 tNET RR 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/CLKB
10.165 0.072 tSu 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 3.114, 38.789%; route: 4.546, 56.633%; tC2Q: 0.368, 4.578%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path9

Path Summary:

Slack 0.055
Data Arrival Time 10.110
Data Required Time 10.165
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/CLK
2.460 0.368 tC2Q RF 43 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q
3.004 0.544 tNET FF 4 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/RAD[0]
3.530 0.526 tINS FR 3 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/DO[0]
3.690 0.160 tNET RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/I1
4.211 0.521 tINS RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/F
4.459 0.248 tNET RR 1 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/I0
4.724 0.265 tINS RR 2 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/F
5.054 0.330 tNET RR 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/I0
5.344 0.290 tINS RF 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/F
5.670 0.326 tNET FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/I1
5.960 0.290 tINS FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/F
6.102 0.142 tNET FF 1 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/I0
6.517 0.415 tINS FR 12 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/F
7.079 0.561 tNET RR 1 R49C70[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_4_s2/I0
7.341 0.262 tINS RR 3 R49C70[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_4_s2/F
7.622 0.281 tNET RR 1 R48C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_4_s0/I3
8.144 0.521 tINS RR 5 R48C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_4_s0/F
10.110 1.966 tNET RR 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/ADB[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s/CLKB
10.165 0.072 tSu 1 BSRAM_R56[6] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_2_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 3.091, 38.556%; route: 4.559, 56.860%; tC2Q: 0.368, 4.584%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path10

Path Summary:

Slack 0.065
Data Arrival Time 9.964
Data Required Time 10.029
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R23C79[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
2.475 0.382 tC2Q RR 6 R23C79[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
3.191 0.716 tNET RR 1 R18C77[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n267_s3/I0
3.454 0.262 tINS RR 3 R18C77[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n267_s3/F
3.782 0.329 tNET RR 1 R21C77[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n265_s3/I2
4.299 0.516 tINS RR 4 R21C77[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n265_s3/F
4.309 0.010 tNET RR 1 R21C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n262_s3/I3
4.806 0.498 tINS RR 4 R21C77[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n262_s3/F
5.056 0.250 tNET RR 1 R20C76[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n259_s3/I3
5.517 0.461 tINS RR 4 R20C76[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n259_s3/F
6.520 1.002 tNET RR 1 R17C75[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n256_s3/I3
7.046 0.526 tINS RR 4 R17C75[2][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n256_s3/F
7.246 0.200 tNET RR 1 R15C75[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n251_s3/I2
7.767 0.521 tINS RR 7 R15C75[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n251_s3/F
8.160 0.392 tNET RR 1 R12C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n242_s3/I1
8.621 0.461 tINS RR 3 R12C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n242_s3/F
8.784 0.162 tNET RR 1 R13C75[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n241_s3/I1
9.310 0.526 tINS RR 1 R13C75[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n241_s3/F
9.448 0.137 tNET RR 1 R13C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n240_s2/I1
9.964 0.516 tINS RR 1 R13C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/n240_s2/F
9.964 0.000 tNET RR 1 R13C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R13C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/CLK
10.029 -0.064 tSu 1 R13C75[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 4.289, 54.486%; route: 3.200, 40.654%; tC2Q: 0.382, 4.859%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path11

Path Summary:

Slack 0.068
Data Arrival Time 10.106
Data Required Time 10.174
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_3_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/CLK
2.460 0.368 tC2Q RF 43 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q
3.004 0.544 tNET FF 4 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/RAD[0]
3.530 0.526 tINS FR 3 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/DO[0]
3.690 0.160 tNET RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/I1
4.211 0.521 tINS RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/F
4.459 0.248 tNET RR 1 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/I0
4.724 0.265 tINS RR 2 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/F
5.054 0.330 tNET RR 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/I0
5.344 0.290 tINS RF 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/F
5.670 0.326 tNET FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/I1
5.960 0.290 tINS FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/F
6.102 0.142 tNET FF 1 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/I0
6.517 0.415 tINS FR 12 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/F
7.079 0.561 tNET RR 1 R49C70[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_4_s2/I0
7.341 0.262 tINS RR 3 R49C70[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_4_s2/F
7.622 0.281 tNET RR 1 R48C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_4_s0/I3
8.144 0.521 tINS RR 5 R48C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_4_s0/F
10.106 1.962 tNET RR 1 BSRAM_R56[7][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_3_s/ADB[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 BSRAM_R56[7][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_3_s/CLKB
10.174 0.072 tSu 1 BSRAM_R56[7][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_3_s

Path Statistics:

Clock Skew 0.009
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 3.091, 38.574%; route: 4.555, 56.840%; tC2Q: 0.368, 4.586%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path12

Path Summary:

Slack 0.087
Data Arrival Time 10.097
Data Required Time 10.184
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/reset_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.111 2.111 tNET RR 1 R49C60[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/reset_2_s0/CLK
2.494 0.382 tC2Q RR 148 R49C60[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/reset_2_s0/Q
5.033 2.539 tNET RR 1 R48C68[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_10_s20/I1
5.268 0.235 tINS RF 49 R48C68[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_10_s20/F
5.718 0.450 tNET FF 1 R48C72[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_0_s4/I2
6.234 0.516 tINS FR 6 R48C72[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_0_s4/F
6.592 0.357 tNET RR 1 R50C71[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_0_s1/I2
7.118 0.526 tINS RR 3 R50C71[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_0_s1/F
7.682 0.564 tNET RR 1 R49C75[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_b_0_s0/I2
8.198 0.516 tINS RR 5 R49C75[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_b_0_s0/F
10.097 1.899 tNET RR 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/ADB[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/CLKB
10.184 0.072 tSu 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 8.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%
Arrival Data Path Delay cell: 1.794, 22.462%; route: 5.809, 72.748%; tC2Q: 0.382, 4.790%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Path13

Path Summary:

Slack 0.107
Data Arrival Time 9.931
Data Required Time 10.038
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_9_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/CLK
2.460 0.368 tC2Q RF 21 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q
4.040 1.580 tNET FF 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/I1
4.556 0.516 tINS FR 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/F
4.714 0.157 tNET RR 1 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/I0
5.129 0.415 tINS RR 8 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/F
5.556 0.427 tNET RR 1 R9C91[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s5/I0
5.819 0.262 tINS RR 6 R9C91[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s5/F
6.411 0.593 tNET RR 1 R8C84[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_0_s4/I0
6.932 0.521 tINS RR 19 R8C84[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b6_0_s4/F
7.116 0.184 tNET RR 1 R8C83[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s35/I3
7.614 0.498 tINS RR 1 R8C83[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s35/F
7.751 0.137 tNET RR 1 R8C83[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s34/I0
8.273 0.521 tINS RR 1 R8C83[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s34/F
8.430 0.157 tNET RR 1 R7C83[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s33/I0
8.891 0.461 tINS RR 2 R7C83[0][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/b4_3_s33/F
9.931 1.040 tNET RR 1 R7C98[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R7C98[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_9_s0/CLK
10.038 -0.064 tSu 1 R7C98[1][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc3/dout_9_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 8.000
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 3.195, 40.759%; route: 4.276, 54.553%; tC2Q: 0.368, 4.688%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path14

Path Summary:

Slack 0.111
Data Arrival Time 10.072
Data Required Time 10.184
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/CLK
2.460 0.368 tC2Q RF 43 R45C66[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_pt_0_s0/Q
3.004 0.544 tNET FF 4 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/RAD[0]
3.530 0.526 tINS FR 3 R51C72 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_0_s/DO[0]
3.690 0.160 tNET RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/I1
4.211 0.521 tINS RR 1 R51C71[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s29/F
4.459 0.248 tNET RR 1 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/I0
4.724 0.265 tINS RR 2 R51C73[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s26/F
5.054 0.330 tNET RR 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/I0
5.344 0.290 tINS RF 1 R51C71[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s23/F
5.670 0.326 tNET FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/I1
5.960 0.290 tINS FF 1 R51C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s17/F
6.102 0.142 tNET FF 1 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/I0
6.517 0.415 tINS FR 12 R51C73[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15198_s14/F
7.081 0.564 tNET RR 1 R50C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15194_s12/I1
7.344 0.262 tINS RR 4 R50C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n15194_s12/F
7.734 0.390 tNET RR 1 R48C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_b_6_s0/I0
8.149 0.415 tINS RR 5 R48C72[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_rd_addr_c_b_b_6_s0/F
10.073 1.924 tNET RR 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/ADB[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s/CLKB
10.184 0.072 tSu 1 BSRAM_R56[7][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_2_s

Path Statistics:

Clock Skew 0.019
Setup Relationship 8.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 2.985, 37.406%; route: 4.628, 57.989%; tC2Q: 0.368, 4.605%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Path15

Path Summary:

Slack 0.135
Data Arrival Time 9.912
Data Required Time 10.047
From SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1
To SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_9_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.092 2.092 tNET RR 1 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/CLK
2.460 0.368 tC2Q RF 21 R22C75[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb_pipe_interface/RxData_0_s1/Q
4.040 1.580 tNET FF 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/I1
4.556 0.516 tINS FR 1 R9C96[2][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s6/F
4.714 0.157 tNET RR 1 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/I0
5.129 0.415 tINS RR 8 R9C95[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc0/b6_0_s3/F
5.990 0.861 tNET RR 1 R12C85[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s13/I0
6.405 0.415 tINS RR 23 R12C85[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b6_0_s13/F
7.187 0.782 tNET RR 1 R8C82[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_2_s52/I2
7.477 0.290 tINS RF 4 R8C82[3][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_2_s52/F
7.630 0.152 tNET FF 1 R7C82[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_3_s35/I3
8.091 0.461 tINS FR 1 R7C82[0][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_3_s35/F
8.229 0.137 tNET RR 1 R7C82[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_3_s33/I3
8.690 0.461 tINS RR 2 R7C82[1][B] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/b4_3_s33/F
9.912 1.222 tNET RR 1 R8C97[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 R8C97[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_9_s0/CLK
10.047 -0.064 tSu 1 R8C97[3][A] SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_encode_8b10b_4ch/enc2/dout_9_s0

Path Statistics:

Clock Skew 0.019
Setup Relationship 8.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%
Arrival Data Path Delay cell: 2.559, 32.721%; route: 4.894, 62.580%; tC2Q: 0.368, 4.699%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Path16

Path Summary:

Slack 0.141
Data Arrival Time 9.641
Data Required Time 9.781
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.641 0.357 tNET RR 1 R54C95[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R54C95[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_1_s0/CLK
9.781 -0.311 tSu 1 R54C95[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_1_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.896%; route: 5.674, 80.666%; tC2Q: 0.382, 5.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path17

Path Summary:

Slack 0.141
Data Arrival Time 9.641
Data Required Time 9.781
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.641 0.357 tNET RR 1 R54C95[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R54C95[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_2_s0/CLK
9.781 -0.311 tSu 1 R54C95[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_2_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.896%; route: 5.674, 80.666%; tC2Q: 0.382, 5.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path18

Path Summary:

Slack 0.141
Data Arrival Time 9.641
Data Required Time 9.781
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_3_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.641 0.357 tNET RR 1 R54C95[1][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R54C95[1][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_3_s0/CLK
9.781 -0.311 tSu 1 R54C95[1][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_3_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.896%; route: 5.674, 80.666%; tC2Q: 0.382, 5.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path19

Path Summary:

Slack 0.141
Data Arrival Time 9.641
Data Required Time 9.781
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.641 0.357 tNET RR 1 R54C95[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R54C95[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_4_s0/CLK
9.781 -0.311 tSu 1 R54C95[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_4_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.896%; route: 5.674, 80.666%; tC2Q: 0.382, 5.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path20

Path Summary:

Slack 0.143
Data Arrival Time 9.638
Data Required Time 9.781
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_7_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.638 0.355 tNET RR 1 R53C95[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C95[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_7_s0/CLK
9.781 -0.311 tSu 1 R53C95[3][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_7_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.901%; route: 5.672, 80.660%; tC2Q: 0.382, 5.440%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path21

Path Summary:

Slack 0.148
Data Arrival Time 9.643
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.643 0.360 tNET RR 1 R53C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_0_s0/CLK
9.791 -0.311 tSu 1 R53C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_0_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.891%; route: 5.677, 80.673%; tC2Q: 0.382, 5.436%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path22

Path Summary:

Slack 0.148
Data Arrival Time 9.643
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.643 0.360 tNET RR 1 R54C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R54C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_6_s0/CLK
9.791 -0.311 tSu 1 R54C96[2][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_6_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.891%; route: 5.677, 80.673%; tC2Q: 0.382, 5.436%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path23

Path Summary:

Slack 0.148
Data Arrival Time 9.643
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_13_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.643 0.360 tNET RR 1 R54C96[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_13_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R54C96[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_13_s0/CLK
9.791 -0.311 tSu 1 R54C96[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_13_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.891%; route: 5.677, 80.673%; tC2Q: 0.382, 5.436%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path24

Path Summary:

Slack 0.148
Data Arrival Time 9.643
Data Required Time 9.791
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_14_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.643 0.360 tNET RR 1 R54C96[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_14_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R54C96[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_14_s0/CLK
9.791 -0.311 tSu 1 R54C96[0][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_14_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.891%; route: 5.677, 80.673%; tC2Q: 0.382, 5.436%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path25

Path Summary:

Slack 0.157
Data Arrival Time 9.643
Data Required Time 9.800
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
5.079 2.090 tNET RR 1 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/I1
5.595 0.516 tINS RR 686 R50C102[2][A] UserLayer_top_inst/ControlTransfer_inst/n2207_s1/F
8.822 3.227 tNET RR 1 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/I3
9.283 0.461 tINS RR 16 R55C96[1][B] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_15_s2/F
9.643 0.360 tNET RR 1 R53C97[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.111 2.111 tNET RR 1 R53C97[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_5_s0/CLK
9.800 -0.311 tSu 1 R53C97[0][A] UserLayer_top_inst/ControlTransfer_inst/wr_desc_len_latch_5_s0

Path Statistics:

Clock Skew -0.495
Setup Relationship 8.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.977, 13.891%; route: 5.677, 80.673%; tC2Q: 0.382, 5.436%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.111, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.186
Data Arrival Time 0.986
Data Required Time 0.800
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C66[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/CLK
0.816 0.144 tC2Q RR 37 R43C66[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/Q
0.986 0.170 tNET RR 1 R34C66[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.869 0.869 tNET RR 1 R34C66[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_6_s0/CLK
0.800 -0.069 tHld 1 R34C66[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_6_s0

Path Statistics:

Clock Skew 0.197
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.170, 54.140%; tC2Q: 0.144, 45.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path2

Path Summary:

Slack 0.186
Data Arrival Time 0.986
Data Required Time 0.800
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_22_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C66[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/CLK
0.816 0.144 tC2Q RR 37 R43C66[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_link_busy_d_s0/Q
0.986 0.170 tNET RR 1 R34C66[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_22_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.869 0.869 tNET RR 1 R34C66[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_22_s0/CLK
0.800 -0.069 tHld 1 R34C66[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/outp_data_22_s0

Path Statistics:

Clock Skew 0.197
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.170, 54.140%; tC2Q: 0.144, 45.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.869, 100.000%

Path3

Path Summary:

Slack 0.192
Data Arrival Time 0.918
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_0_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R49C62[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_0_s0/CLK
0.816 0.144 tC2Q RR 5 R49C62[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_0_s0/Q
0.918 0.102 tNET RR 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/CLK
0.726 0.050 tHld 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.102, 41.463%; tC2Q: 0.144, 58.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path4

Path Summary:

Slack 0.194
Data Arrival Time 0.916
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C63[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/CLK
0.820 0.144 tC2Q RR 3 R51C63[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/Q
0.916 0.096 tNET RR 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/CLK
0.722 0.050 tHld 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path5

Path Summary:

Slack 0.194
Data Arrival Time 0.916
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C63[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/CLK
0.820 0.144 tC2Q RR 4 R51C63[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/Q
0.916 0.096 tNET RR 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/CLK
0.722 0.050 tHld 1 R51C62 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.096, 40.000%; tC2Q: 0.144, 60.000%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path6

Path Summary:

Slack 0.197
Data Arrival Time 0.919
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C65[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/CLK
0.820 0.144 tC2Q RR 3 R51C65[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/Q
0.919 0.099 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/CLK
0.722 0.050 tHld 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path7

Path Summary:

Slack 0.197
Data Arrival Time 0.919
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s2
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C67[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s2/CLK
0.820 0.144 tC2Q RR 4 R51C67[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s2/Q
0.919 0.099 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/CLK
0.722 0.050 tHld 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path8

Path Summary:

Slack 0.197
Data Arrival Time 0.919
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_0_s2
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C67[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_0_s2/CLK
0.820 0.144 tC2Q RR 5 R51C67[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_0_s2/Q
0.919 0.099 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/CLK
0.722 0.050 tHld 1 R51C66 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path9

Path Summary:

Slack 0.197
Data Arrival Time 0.923
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_1_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R49C60[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_1_s0/CLK
0.824 0.144 tC2Q RR 4 R49C60[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_1_s0/Q
0.923 0.099 tNET RR 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/CLK
0.726 0.050 tHld 1 R49C61 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path10

Path Summary:

Slack 0.202
Data Arrival Time 0.928
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C78[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/CLK
0.820 0.144 tC2Q RR 9 R51C78[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/Q
0.928 0.108 tNET RR 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/CLK
0.726 0.050 tHld 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.108, 42.857%; tC2Q: 0.144, 57.143%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path11

Path Summary:

Slack 0.205
Data Arrival Time 0.931
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C78[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/CLK
0.820 0.144 tC2Q RR 10 R51C78[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/Q
0.931 0.111 tNET RR 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/WAD[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s/CLK
0.726 0.050 tHld 1 R50C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path12

Path Summary:

Slack 0.206
Data Arrival Time 0.932
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R49C63[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_2_s0/CLK
0.820 0.144 tC2Q RR 3 R49C63[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_2_s0/Q
0.932 0.112 tNET RR 1 R49C65 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R49C65 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/CLK
0.726 0.050 tHld 1 R49C65 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.112, 43.750%; tC2Q: 0.144, 56.250%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path13

Path Summary:

Slack 0.206
Data Arrival Time 0.932
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/CLK
0.816 0.144 tC2Q RR 24 R40C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/Q
0.932 0.116 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/CLK
0.726 0.050 tHld 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.116, 44.615%; tC2Q: 0.144, 55.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path14

Path Summary:

Slack 0.206
Data Arrival Time 0.932
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/CLK
0.816 0.144 tC2Q RR 38 R40C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/Q
0.932 0.116 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/CLK
0.726 0.050 tHld 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.116, 44.615%; tC2Q: 0.144, 55.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path15

Path Summary:

Slack 0.208
Data Arrival Time 0.930
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/CLK
0.816 0.144 tC2Q RR 24 R40C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_2_s0/Q
0.930 0.114 tNET RR 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/CLK
0.722 0.050 tHld 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.114, 44.186%; tC2Q: 0.144, 55.814%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path16

Path Summary:

Slack 0.208
Data Arrival Time 0.934
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_1_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R51C78[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/CLK
0.820 0.144 tC2Q RR 9 R51C78[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_2_s0/Q
0.934 0.114 tNET RR 1 R49C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_1_s/WAD[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R49C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_1_s/CLK
0.726 0.050 tHld 1 R49C78 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.114, 44.186%; tC2Q: 0.144, 55.814%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path17

Path Summary:

Slack 0.210
Data Arrival Time 0.932
Data Required Time 0.722
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R40C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/CLK
0.816 0.144 tC2Q RR 38 R40C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_0_s2/Q
0.932 0.116 tNET RR 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/WAD[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s/CLK
0.722 0.050 tHld 1 R39C87 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.116, 44.615%; tC2Q: 0.144, 55.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path18

Path Summary:

Slack 0.214
Data Arrival Time 0.940
Data Required Time 0.726
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_3_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_3_s0/CLK
0.820 0.144 tC2Q RR 21 R40C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_in_pt_3_s0/Q
0.940 0.120 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/WAD[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s/CLK
0.726 0.050 tHld 1 R40C86 USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_out_len_mem_buf_out_len_mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 45.455%; tC2Q: 0.144, 54.545%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path19

Path Summary:

Slack 0.230
Data Arrival Time 1.128
Data Required Time 0.898
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3p/phy_power_down_1_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/port_tx_elecidle_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R44C55[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3p/phy_power_down_1_s1/CLK
0.820 0.144 tC2Q RR 19 R44C55[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3p/phy_power_down_1_s1/Q
0.975 0.155 tNET RR 1 R36C55[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/n2739_s11/I1
1.128 0.153 tINS RF 1 R36C55[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/n2739_s11/F
1.128 0.000 tNET FF 1 R36C55[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/port_tx_elecidle_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.873 0.873 tNET RR 1 R36C55[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/port_tx_elecidle_s0/CLK
0.898 0.025 tHld 1 R36C55[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3lt/port_tx_elecidle_s0

Path Statistics:

Clock Skew 0.197
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.153, 33.850%; route: 0.155, 34.292%; tC2Q: 0.144, 31.858%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.873, 100.000%

Path20

Path Summary:

Slack 0.232
Data Arrival Time 0.945
Data Required Time 0.713
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R34C98[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/CLK
0.820 0.144 tC2Q RR 40 R34C98[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/Q
0.945 0.125 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKA
0.713 0.037 tHld 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.125, 46.468%; tC2Q: 0.144, 53.532%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path21

Path Summary:

Slack 0.237
Data Arrival Time 0.950
Data Required Time 0.713
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R34C97[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/CLK
0.824 0.144 tC2Q RR 39 R34C97[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/Q
0.950 0.126 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKA
0.713 0.037 tHld 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 46.667%; tC2Q: 0.144, 53.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path22

Path Summary:

Slack 0.238
Data Arrival Time 0.947
Data Required Time 0.709
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R34C98[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/CLK
0.820 0.144 tC2Q RR 40 R34C98[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_9_s0/Q
0.947 0.127 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/CLKA
0.709 0.037 tHld 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 46.863%; tC2Q: 0.144, 53.137%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path23

Path Summary:

Slack 0.239
Data Arrival Time 0.948
Data Required Time 0.709
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R34C98[2][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/CLK
0.820 0.144 tC2Q RR 45 R34C98[2][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/Q
0.948 0.128 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/CLKA
0.709 0.037 tHld 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 47.059%; tC2Q: 0.144, 52.941%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path24

Path Summary:

Slack 0.239
Data Arrival Time 0.952
Data Required Time 0.713
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R34C98[2][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/CLK
0.820 0.144 tC2Q RR 45 R34C98[2][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_6_s0/Q
0.952 0.132 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s/CLKA
0.713 0.037 tHld 1 BSRAM_R38[20][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_15_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.132, 47.826%; tC2Q: 0.144, 52.174%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path25

Path Summary:

Slack 0.241
Data Arrival Time 0.950
Data Required Time 0.709
From UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0
To UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R34C97[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/CLK
0.824 0.144 tC2Q RR 39 R34C97[2][A] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.wbin_7_s0/Q
0.950 0.126 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s/CLKA
0.709 0.037 tHld 1 BSRAM_R38[20][B] UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_18_s

Path Statistics:

Clock Skew -0.008
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 46.667%; tC2Q: 0.144, 53.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.459
Data Arrival Time 9.295
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_0_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.295 4.451 tNET FF 1 R53C86[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C86[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_0_s1/CLK
9.754 -0.347 tSu 1 R53C86[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_0_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.298%; route: 5.885, 87.984%; tC2Q: 0.382, 5.719%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path2

Path Summary:

Slack 0.459
Data Arrival Time 9.295
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_3_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.295 4.451 tNET FF 1 R53C86[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C86[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_3_s1/CLK
9.754 -0.347 tSu 1 R53C86[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_3_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.298%; route: 5.885, 87.984%; tC2Q: 0.382, 5.719%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path3

Path Summary:

Slack 0.459
Data Arrival Time 9.295
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_5_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.295 4.451 tNET FF 1 R53C86[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C86[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_5_s1/CLK
9.754 -0.347 tSu 1 R53C86[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_5_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.298%; route: 5.885, 87.984%; tC2Q: 0.382, 5.719%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path4

Path Summary:

Slack 0.459
Data Arrival Time 9.295
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_6_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.295 4.451 tNET FF 1 R53C86[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C86[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_6_s1/CLK
9.754 -0.347 tSu 1 R53C86[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_out_addr_6_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.298%; route: 5.885, 87.984%; tC2Q: 0.382, 5.719%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path5

Path Summary:

Slack 0.459
Data Arrival Time 9.295
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_6_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.295 4.451 tNET FF 1 R53C86[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C86[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_6_s1/CLK
9.754 -0.347 tSu 1 R53C86[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_6_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.298%; route: 5.885, 87.984%; tC2Q: 0.382, 5.719%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path6

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_2_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_2_s1/CLK
9.745 -0.347 tSu 1 R53C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_2_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path7

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_3_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_3_s1/CLK
9.745 -0.347 tSu 1 R53C87[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_3_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path8

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_4_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_4_s1/CLK
9.745 -0.347 tSu 1 R53C87[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_4_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path9

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_5_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_5_s1/CLK
9.745 -0.347 tSu 1 R53C87[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_5_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path10

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_7_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_7_s1/CLK
9.745 -0.347 tSu 1 R53C87[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_7_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path11

Path Summary:

Slack 0.634
Data Arrival Time 9.111
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_8_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R53C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_8_s1/CLK
9.745 -0.347 tSu 1 R53C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_8_s1

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path12

Path Summary:

Slack 0.639
Data Arrival Time 9.115
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_2_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.115 4.271 tNET FF 1 R66C90[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R66C90[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_2_s1/CLK
9.754 -0.347 tSu 1 R66C90[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_2_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.472%; route: 5.705, 87.651%; tC2Q: 0.382, 5.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path13

Path Summary:

Slack 0.639
Data Arrival Time 9.115
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_3_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.115 4.271 tNET FF 1 R66C90[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R66C90[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_3_s1/CLK
9.754 -0.347 tSu 1 R66C90[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_3_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.472%; route: 5.705, 87.651%; tC2Q: 0.382, 5.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path14

Path Summary:

Slack 0.639
Data Arrival Time 9.115
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_5_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.115 4.271 tNET FF 1 R66C90[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R66C90[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_5_s1/CLK
9.754 -0.347 tSu 1 R66C90[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_5_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.472%; route: 5.705, 87.651%; tC2Q: 0.382, 5.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path15

Path Summary:

Slack 0.639
Data Arrival Time 9.115
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_6_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.115 4.271 tNET FF 1 R66C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R66C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_6_s1/CLK
9.754 -0.347 tSu 1 R66C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_6_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.472%; route: 5.705, 87.651%; tC2Q: 0.382, 5.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path16

Path Summary:

Slack 0.639
Data Arrival Time 9.115
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_7_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.115 4.271 tNET FF 1 R66C90[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R66C90[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_7_s1/CLK
9.754 -0.347 tSu 1 R66C90[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_7_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.472%; route: 5.705, 87.651%; tC2Q: 0.382, 5.877%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path17

Path Summary:

Slack 0.643
Data Arrival Time 9.111
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_ready_s3
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C88[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_ready_s3/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C88[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_ready_s3/CLK
9.754 -0.347 tSu 1 R53C88[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_ready_s3

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path18

Path Summary:

Slack 0.643
Data Arrival Time 9.111
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_0_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C88[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C88[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_0_s1/CLK
9.754 -0.347 tSu 1 R53C88[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_0_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path19

Path Summary:

Slack 0.643
Data Arrival Time 9.111
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_hasdata_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.111 4.268 tNET FF 1 R53C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_hasdata_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_hasdata_s1/CLK
9.754 -0.347 tSu 1 R53C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_a_hasdata_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.476%; route: 5.701, 87.644%; tC2Q: 0.382, 5.880%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path20

Path Summary:

Slack 0.662
Data Arrival Time 9.093
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_4_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.093 4.249 tNET FF 1 R67C90[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R67C90[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_4_s1/CLK
9.754 -0.347 tSu 1 R67C90[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_4_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.495%; route: 5.683, 87.608%; tC2Q: 0.382, 5.897%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path21

Path Summary:

Slack 0.662
Data Arrival Time 9.093
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_1_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.093 4.249 tNET FF 1 R67C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R67C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_1_s1/CLK
9.754 -0.347 tSu 1 R67C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_OUT/buf_out_addr_1_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.495%; route: 5.683, 87.608%; tC2Q: 0.382, 5.897%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path22

Path Summary:

Slack 0.670
Data Arrival Time 9.075
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/rd_setup_pkt_dval_d_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.075 4.231 tNET FF 1 R55C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/rd_setup_pkt_dval_d_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R55C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/rd_setup_pkt_dval_d_s0/CLK
9.745 -0.347 tSu 1 R55C87[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/rd_setup_pkt_dval_d_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.512%; route: 5.665, 87.575%; tC2Q: 0.382, 5.913%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path23

Path Summary:

Slack 0.670
Data Arrival Time 9.075
Data Required Time 9.745
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/packet_setup_latch_act_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.075 4.231 tNET FF 1 R55C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/packet_setup_latch_act_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.092 2.092 tNET RR 1 R55C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/packet_setup_latch_act_s0/CLK
9.745 -0.347 tSu 1 R55C87[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/packet_setup_latch_act_s0

Path Statistics:

Clock Skew -0.514
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.512%; route: 5.665, 87.575%; tC2Q: 0.382, 5.913%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.092, 100.000%

Path24

Path Summary:

Slack 0.671
Data Arrival Time 9.084
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_1_s1
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.084 4.240 tNET FF 1 R53C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R53C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_1_s1/CLK
9.754 -0.347 tSu 1 R53C90[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/usb3_ep0_IN/buf_in_addr_1_s1

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.503%; route: 5.674, 87.592%; tC2Q: 0.382, 5.905%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Path25

Path Summary:

Slack 0.671
Data Arrival Time 9.083
Data Required Time 9.754
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/dev_address_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR 1 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/CLK
2.989 0.382 tC2Q RR 76 R33C52[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/attached_s0/Q
4.423 1.434 tNET RR 1 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/I1
4.844 0.421 tINS RF 75 R46C86[3][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/n6_s1/F
9.083 4.239 tNET FF 1 R59C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/dev_address_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
8.000 8.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
10.102 2.102 tNET RR 1 R59C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/dev_address_4_s0/CLK
9.754 -0.347 tSu 1 R59C88[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/dev_address_4_s0

Path Statistics:

Clock Skew -0.504
Setup Relationship 8.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.606, 100.000%
Arrival Data Path Delay cell: 0.421, 6.504%; route: 5.673, 87.590%; tC2Q: 0.382, 5.906%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.102, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.406
Data Arrival Time 1.029
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.029 0.213 tNET RR 1 R57C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R57C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_1_s0/CLK
0.623 -0.053 tHld 1 R57C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_1_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.213, 59.664%; tC2Q: 0.144, 40.336%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path2

Path Summary:

Slack 0.467
Data Arrival Time 1.086
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.086 0.270 tNET RR 1 R60C70[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_4_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R60C70[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_4_s0/CLK
0.619 -0.053 tHld 1 R60C70[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.270, 65.217%; tC2Q: 0.144, 34.783%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path3

Path Summary:

Slack 0.467
Data Arrival Time 1.086
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_10_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.086 0.270 tNET RR 1 R54C70[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_10_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R54C70[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_10_s0/CLK
0.619 -0.053 tHld 1 R54C70[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.270, 65.217%; tC2Q: 0.144, 34.783%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path4

Path Summary:

Slack 0.467
Data Arrival Time 1.086
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.086 0.270 tNET RR 1 R54C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R54C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/CLK
0.619 -0.053 tHld 1 R54C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.270, 65.217%; tC2Q: 0.144, 34.783%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path5

Path Summary:

Slack 0.468
Data Arrival Time 1.087
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.087 0.271 tNET RR 1 R53C70[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R53C70[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/CLK
0.619 -0.053 tHld 1 R53C70[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.271, 65.301%; tC2Q: 0.144, 34.699%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path6

Path Summary:

Slack 0.468
Data Arrival Time 1.087
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_8_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.087 0.271 tNET RR 1 R53C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_8_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R53C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_8_s0/CLK
0.619 -0.053 tHld 1 R53C70[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.271, 65.301%; tC2Q: 0.144, 34.699%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path7

Path Summary:

Slack 0.500
Data Arrival Time 1.123
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.123 0.307 tNET RR 1 R59C71[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R59C71[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_0_s0/CLK
0.623 -0.053 tHld 1 R59C71[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_0_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path8

Path Summary:

Slack 0.500
Data Arrival Time 1.123
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.123 0.307 tNET RR 1 R59C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_5_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R59C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_5_s0/CLK
0.623 -0.053 tHld 1 R59C71[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_5_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.307, 68.071%; tC2Q: 0.144, 31.929%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path9

Path Summary:

Slack 0.502
Data Arrival Time 1.125
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_3_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.125 0.309 tNET RR 1 R57C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_3_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R57C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_3_s0/CLK
0.623 -0.053 tHld 1 R57C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_3_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.309, 68.212%; tC2Q: 0.144, 31.788%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path10

Path Summary:

Slack 0.512
Data Arrival Time 1.135
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_1_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.135 0.315 tNET RR 1 R43C82[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_1_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R43C82[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_1_s0/CLK
0.623 -0.053 tHld 1 R43C82[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path11

Path Summary:

Slack 0.512
Data Arrival Time 1.135
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_3_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.135 0.315 tNET RR 1 R43C82[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_3_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R43C82[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_3_s0/CLK
0.623 -0.053 tHld 1 R43C82[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path12

Path Summary:

Slack 0.512
Data Arrival Time 1.135
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_7_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.135 0.315 tNET RR 1 R43C82[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_7_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R43C82[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_7_s0/CLK
0.623 -0.053 tHld 1 R43C82[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.315, 68.627%; tC2Q: 0.144, 31.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path13

Path Summary:

Slack 0.551
Data Arrival Time 1.174
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_5_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.174 0.354 tNET RR 1 R44C78[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_5_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R44C78[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_5_s0/CLK
0.623 -0.053 tHld 1 R44C78[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.354, 71.084%; tC2Q: 0.144, 28.916%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path14

Path Summary:

Slack 0.551
Data Arrival Time 1.174
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_9_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.174 0.354 tNET RR 1 R44C78[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_9_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R44C78[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_9_s0/CLK
0.623 -0.053 tHld 1 R44C78[2][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.354, 71.084%; tC2Q: 0.144, 28.916%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path15

Path Summary:

Slack 0.555
Data Arrival Time 1.178
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_7_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.178 0.362 tNET RR 1 R59C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_7_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R59C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_7_s0/CLK
0.623 -0.053 tHld 1 R59C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_7_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path16

Path Summary:

Slack 0.555
Data Arrival Time 1.178
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.178 0.362 tNET RR 1 R59C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R59C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/CLK
0.623 -0.053 tHld 1 R59C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path17

Path Summary:

Slack 0.597
Data Arrival Time 1.216
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_0_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.216 0.396 tNET RR 1 R43C83[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_0_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C83[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_0_s0/CLK
0.619 -0.053 tHld 1 R43C83[2][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_0_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.396, 73.333%; tC2Q: 0.144, 26.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path18

Path Summary:

Slack 0.597
Data Arrival Time 1.216
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.216 0.396 tNET RR 1 R43C83[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C83[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_2_s0/CLK
0.619 -0.053 tHld 1 R43C83[1][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_2_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.396, 73.333%; tC2Q: 0.144, 26.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path19

Path Summary:

Slack 0.597
Data Arrival Time 1.216
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_4_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.216 0.396 tNET RR 1 R43C83[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_4_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C83[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_4_s0/CLK
0.619 -0.053 tHld 1 R43C83[3][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_4_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.396, 73.333%; tC2Q: 0.144, 26.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path20

Path Summary:

Slack 0.597
Data Arrival Time 1.216
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_10_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.216 0.396 tNET RR 1 R43C83[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_10_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C83[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_10_s0/CLK
0.619 -0.053 tHld 1 R43C83[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_10_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.396, 73.333%; tC2Q: 0.144, 26.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path21

Path Summary:

Slack 0.597
Data Arrival Time 1.216
Data Required Time 0.619
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_11_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.216 0.396 tNET RR 1 R43C83[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_11_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R43C83[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_11_s0/CLK
0.619 -0.053 tHld 1 R43C83[1][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_11_s0

Path Statistics:

Clock Skew -0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.396, 73.333%; tC2Q: 0.144, 26.667%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%

Path22

Path Summary:

Slack 0.602
Data Arrival Time 1.229
Data Required Time 0.627
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_15_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.229 0.409 tNET RR 1 R43C81[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_15_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R43C81[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_15_s0/CLK
0.627 -0.053 tHld 1 R43C81[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_15_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 73.960%; tC2Q: 0.144, 26.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%

Path23

Path Summary:

Slack 0.602
Data Arrival Time 1.229
Data Required Time 0.627
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_8_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/CLK
0.820 0.144 tC2Q RR 18 R40C84[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/crc_hptx_rst_s0/Q
1.229 0.409 tNET RR 1 R43C81[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_8_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.680 0.680 tNET RR 1 R43C81[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_8_s0/CLK
0.627 -0.053 tHld 1 R43C81[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chptx/q_8_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 73.960%; tC2Q: 0.144, 26.040%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.680, 100.000%

Path24

Path Summary:

Slack 0.611
Data Arrival Time 1.234
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_14_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.234 0.418 tNET RR 1 R55C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_14_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R55C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_14_s0/CLK
0.623 -0.053 tHld 1 R55C69[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_14_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.418, 74.377%; tC2Q: 0.144, 25.623%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Path25

Path Summary:

Slack 0.626
Data Arrival Time 1.249
Data Required Time 0.623
From USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_2_s0
Launch Clk pclk:[R]
Latch Clk pclk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.672 0.672 tNET RR 1 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.816 0.144 tC2Q RR 23 R57C75[0][A] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
1.249 0.433 tNET RR 1 R58C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_2_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR 5681 R2C2 SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.676 0.676 tNET RR 1 R58C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_2_s0/CLK
0.623 -0.053 tHld 1 R58C69[0][B] USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_2_s0

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.672, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.433, 75.043%; tC2Q: 0.144, 24.957%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.676, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s/CLKA

MPW2

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s/CLKB

MPW3

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_1_s/CLKA

MPW4

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: UserLayer_top_inst/DataTransfer_inst/payload_fifo_a/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF UserLayer_top_inst/DataTransfer_inst/payload_fifo_a/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR UserLayer_top_inst/DataTransfer_inst/payload_fifo_a/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW5

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

MPW6

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR UserLayer_top_inst/yuv_data_fifo_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

MPW7

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR UserLayer_top_inst/DataTransfer_inst/payload_fifo_b/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB

MPW8

MPW Summary:

Slack: 1.272
Actual Width: 2.272
Required Width: 1.000
Type: Low Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
6.605 2.605 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_2_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
8.000 0.000 active clock edge time
8.000 0.000 pclk
8.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.877 0.877 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/usb3_ep2_IN/buf_a_buf_a_0_2_s/CLKB

MPW9

MPW Summary:

Slack: 1.276
Actual Width: 2.276
Required Width: 1.000
Type: High Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.882 0.882 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_0_s/CLKA

MPW10

MPW Summary:

Slack: 1.276
Actual Width: 2.276
Required Width: 1.000
Type: High Pulse Width
Clock: pclk
Objects: USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 pclk
0.000 0.000 tCL RR SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
2.606 2.606 tNET RR USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s/CLKB

Early clock Path:

AT DELAY TYPE RF NODE
4.000 0.000 active clock edge time
4.000 0.000 pclk
4.000 0.000 tCL FF SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
4.882 0.882 tNET FF USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_3_res_mem_3_0_1_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
5681 pclk 0.003 2.616
686 n2207_5 0.003 3.236
437 n2492_7 2.167 2.156
260 upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1] 1.695 4.106
240 n5171_3 3.962 2.730
191 cam_active_Z 0.182 3.190
148 reset_2 0.087 2.802
137 ltssm_state[1] 2.133 1.432
134 resp_rd_addr[0] 3.345 1.152
133 rx_cred_idx_latch[1] 4.583 1.360

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R21C81 91.67%
R34C98 88.89%
R23C82 86.11%
R17C84 84.72%
R13C89 83.33%
R23C83 83.33%
R16C85 83.33%
R41C77 83.33%
R18C85 81.94%
R40C72 81.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name pclk -period 8 -waveform {0 4} [get_nets {pclk}]
TC_CLOCK Actived create_clock -name sys_clk_p -period 5 -waveform {0 2.5} [get_ports {sys_clk_p}]
TC_CLOCK Actived create_clock -name drp_clk_o -period 10 -waveform {0 5} [get_nets {SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {drp_clk_o}]