Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\dp_data_fifo_top\dp_data_fifo_top.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\payload_fifo\payload_fifo.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\serdes\serdes.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\serdes\upar_arbiter\upar_arbiter.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\serdes\usb3_0_phy\static_macro_define.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\serdes\usb3_0_phy\usb3_0_phy.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\serdes\usb3_0_phy\usb3_0_phy_top_define.vh E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\top.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\USB30_Device_Controller_Top.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb30_device_controller.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_TxHp.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_TxLcmd.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_const.vh E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_crc.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_descramble.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_ep.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_ep0.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_ep0in_ram.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_lfsr.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_link.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_ltssm_device.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_macro_define.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_pipe.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_protocol.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_device_controller\usb3_scramble.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\ControlTransfer.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\DataTransfer.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\PixelGen.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\UVCDefine.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\UserEndpt_define.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\UserLayer_top.v E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\usb30_user_layer\usb_descrip.vh E:\myWork\IP\releaseVerify\version\1.9.11.01\Gowin_USB30_UVC_RefDeign\prj\src\yuv_data_fifo\yuv_data_fifo.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5AT-LV60UG225C1/I0 |
| Device | GW5AT-60 |
| Device Version | B |
| Created Time | Fri Feb 28 10:38:17 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 307.105MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 307.105MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 307.105MB Optimizing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 307.105MB Running inference: Inferring Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 307.105MB Inferring Phase 1: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.743s, Peak memory usage = 307.105MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 307.105MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 307.105MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 307.105MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.505s, Peak memory usage = 307.105MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.602s, Peak memory usage = 307.105MB Tech-Mapping Phase 3: CPU time = 0h 2m 34s, Elapsed time = 0h 2m 34s, Peak memory usage = 309.941MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 309.941MB Generate output files: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.764s, Peak memory usage = 325.059MB |
| Total Time and Memory Usage | CPU time = 0h 2m 47s, Elapsed time = 0h 2m 47s, Peak memory usage = 325.059MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 5 |
| I/O Buf | 3 |
| OBUF | 1 |
| TLVDS_IBUF | 1 |
| TLVDS_OBUF | 1 |
| Register | 5712 |
| DFFSE | 93 |
| DFFRE | 2295 |
| DFFPE | 135 |
| DFFCE | 3189 |
| LUT | 9397 |
| LUT2 | 1194 |
| LUT3 | 2888 |
| LUT4 | 5315 |
| ALU | 448 |
| ALU | 448 |
| SSRAM | 36 |
| RAM16SDP1 | 1 |
| RAM16SDP2 | 1 |
| RAM16SDP4 | 34 |
| INV | 92 |
| INV | 92 |
| DSP | |
| MULTALU27X18 | 1 |
| BSRAM | 92 |
| SDPB | 74 |
| SDPX9B | 17 |
| pROM | 1 |
| CLOCK | 1 |
| PLLA | 1 |
| GTR12_QUADA | 1 |
| GTR12_UPARA | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 10153(9489 LUT, 448 ALU, 36 RAM16) / 59904 | 17% |
| Register | 5712 / 60231 | 10% |
| --Register as Latch | 0 / 60231 | 0% |
| --Register as FF | 5712 / 60231 | 10% |
| BSRAM | 92 / 118 | 78% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | sys_clk_p | Base | 5.000 | 200.000 | 0.000 | 2.500 | Inst_sys_clk_in/I | ||
| 2 | Inst_Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 8.000 | 125.000 | 0.000 | 4.000 | Inst_sys_clk_in/I | sys_clk_p | Inst_Gowin_PLL/PLLA_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|