Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\gowin_pll\gowin_pll.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\gowin_pll\gowin_pll_mod.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\i2c_master\i2c_master.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\iic\gw_i2c_master.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\iic\iic_controller.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\iic\master_sram_iic.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\pll_init.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\serdes\serdes.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\serdes\upar_arbiter\upar_arbiter.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\ControlTransfer.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\EP1_loopback.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\EP2_INT.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\EP2_speed.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\UserLayer_top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_user_layer\usb_descrip_define.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\serdes\usb3_1_phy\usb3_1_phy.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\transfer_in_mem.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\transfer_in_mem_ping_pong.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\transfer_out_mem.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\transfer_out_mem_ping_pong.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_2_device_controller.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\USB3_2_Device_Controller_Top.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_const.vh E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_ep.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_ep0.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_ep0in_ram.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_macro_define.v E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_protocol.sv E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_link.vg E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_ltssm_device.vg E:\Gowin_haogang\project\Gowin_USB3_2_Ref\Gowin_USB3_2_CDC_BULK_BW_Test_Ref\release\Gowin_USB3_2_CDC_BULK_BW_Test_Ref_DK_USB_5AT60UG225\prj\src\usb3_2_device_controller\usb3_pipe.vg
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Wed Jul 8 16:05:42 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	top
Synthesis Process	Running parser: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 8s, Peak memory usage = 458.125MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 4s, Peak memory usage = 458.125MB Optimizing Phase 1: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 458.125MB Optimizing Phase 2: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 458.125MB Running inference: Inferring Phase 0: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 458.125MB Inferring Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 458.125MB Inferring Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.408s, Peak memory usage = 458.125MB Inferring Phase 3: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 458.125MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 458.125MB Tech-Mapping Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 458.125MB Tech-Mapping Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 458.125MB Tech-Mapping Phase 3: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 458.125MB Tech-Mapping Phase 4: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 458.125MB Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 550.539MB
Total Time and Memory Usage	CPU time = 0h 1m 7s, Elapsed time = 0h 1m 4s, Peak memory usage = 550.539MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	20
I/O Buf	1211
IBUF	816
OBUF	391
IOBUF	2
TLVDS_IBUF	1
ELVDS_OBUF	1
Register	14212
DFFSE	351
DFFRE	3180
DFFPE	481
DFFCE	10200
LUT	24067
LUT2	2987
LUT3	6690
LUT4	14390
ALU	598
ALU	598
SSRAM	82
RAM16SDP1	2
RAM16SDP2	1
RAM16SDP4	79
INV	635
INV	635
DSP
MULTALU27X18	1
BSRAM	35
SDPB	28
SDPX9B	7

Resource Utilization Summary

Resource	Usage	Utilization
Logic	25792(24702 LUT, 598 ALU, 82 RAM16) / 59904	44%
Register	14212 / 60228	24%
--Register as Latch	0 / 60228	0%
--Register as FF	14212 / 60228	24%
BSRAM	35 / 118	30%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Object
1	fclk	Base	10.000	100.000	5.000	fclk_ibuf/I
2	pclk	Base	10.000	100.000	5.000	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
3	pclk_gowin	Base	10.000	100.000	5.000	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
4	pclk_gowin_gowin	Base	10.000	100.000	5.000	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/local_clk_ibuf/I
5	sys_clk_p	Base	10.000	100.000	5.000	Inst_sys_clk_in/I
6	cnt4_clr	Base	10.000	100.000	5.000	cnt4_clr_s0/Q

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	fclk	100.000(MHz)	206.373(MHz)	7	TOP
2	pclk	100.000(MHz)	186.930(MHz)	9	TOP
3	pclk_gowin	100.000(MHz)	191.077(MHz)	8	TOP
4	pclk_gowin_gowin	100.000(MHz)	141.834(MHz)	8	TOP
5	sys_clk_p	100.000(MHz)	483.723(MHz)	3	TOP
6	cnt4_clr	100.000(MHz)	806.322(MHz)	2	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	1.287
Data Arrival Time	9.430
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/I
4.572	0.528	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/I2
5.174	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/F
5.444	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/I1
5.816	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/F
6.086	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/I0
6.465	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s2/I2
7.067	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s2/F
7.337	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s144/I3
7.526	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s144/F
7.796	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s138/I1
7.894	0.098	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s138/O
8.164	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s135/I1
8.226	0.062	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s135/O
8.496	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s92/I0
8.558	0.062	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s92/O
8.828	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6198_s1/I2
9.160	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6198_s1/F
9.430	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	10
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.116, 59.273%; route: 3.240, 37.536%; tC2Q: 0.275, 3.191%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 2

Path Summary:

Slack	1.912
Data Arrival Time	8.627
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
8.357	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
8.627	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_0_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.124, 65.444%; route: 2.430, 31.038%; tC2Q: 0.275, 3.518%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 3

Path Summary:

Slack	1.912
Data Arrival Time	8.627
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
8.357	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
8.627	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_1_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.124, 65.444%; route: 2.430, 31.038%; tC2Q: 0.275, 3.518%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 4

Path Summary:

Slack	1.912
Data Arrival Time	8.627
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
8.357	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
8.627	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_2_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.124, 65.444%; route: 2.430, 31.038%; tC2Q: 0.275, 3.518%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 5

Path Summary:

Slack	1.912
Data Arrival Time	8.627
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/I2
8.357	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s4/F
8.627	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_loopback_latch_3_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.124, 65.444%; route: 2.430, 31.038%; tC2Q: 0.275, 3.518%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 6

Path Summary:

Slack	2.029
Data Arrival Time	8.688
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_active_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_active_s2/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_active_s2/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_active_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_active_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_active_ibuf/I
4.572	0.528	tINS	RR	8	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_active_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/set_ts_s9/I0
5.221	0.379	tINS	RR	7	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/set_ts_s9/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s11/I0
5.870	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s11/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s5/I0
6.519	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s5/F
6.789	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s30/I0
7.167	0.379	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s30/F
7.437	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s31/I0
7.816	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s31/F
8.086	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s28/I2
8.418	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3848_s28/F
8.688	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_5_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.185, 65.712%; route: 2.430, 30.798%; tC2Q: 0.275, 3.490%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 7

Path Summary:

Slack	2.036
Data Arrival Time	8.681
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_3_s0
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/I0
6.519	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/F
6.789	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s40/I0
7.167	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s40/F
7.437	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3693_s41/I1
7.809	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3693_s41/F
8.079	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3693_s39/I2
8.411	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3693_s39/F
8.681	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_3_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_3_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_3_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.178, 65.680%; route: 2.430, 30.826%; tC2Q: 0.275, 3.494%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 8

Path Summary:

Slack	2.083
Data Arrival Time	8.634
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/I
4.572	0.528	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/I2
5.174	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/F
5.444	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/I1
5.816	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/F
6.086	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/I0
6.465	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s95/I0
7.113	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s95/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s90/I2
7.716	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s90/F
7.986	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s89/I0
8.364	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s89/F
8.634	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.131, 65.476%; route: 2.430, 31.010%; tC2Q: 0.275, 3.514%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 9

Path Summary:

Slack	2.104
Data Arrival Time	8.613
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_power_ack_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_power_ack_s2/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_power_ack_s2/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_power_ack_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_power_ack_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/port_power_ack_ibuf/I
4.572	0.528	tINS	RR	12	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/port_power_ack_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s121/I1
5.214	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s121/F
5.484	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s29/I1
5.855	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s29/F
6.125	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s24/I2
6.457	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s24/F
6.727	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s11/I2
7.059	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s11/F
7.329	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s31/I1
7.701	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s31/F
7.971	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s1/I1
8.343	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6190_s1/F
8.613	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.109, 65.380%; route: 2.430, 31.096%; tC2Q: 0.275, 3.524%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 10

Path Summary:

Slack	2.186
Data Arrival Time	8.531
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/I0
6.519	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/F
6.789	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s52/I1
7.160	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s52/F
7.430	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/I1
7.802	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/F
8.072	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/I3
8.261	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/F
8.531	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 5.027, 65.014%; route: 2.430, 31.425%; tC2Q: 0.275, 3.561%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 11

Path Summary:

Slack	2.219
Data Arrival Time	8.499
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/I3
6.329	0.189	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/F
6.599	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/I2
6.931	0.332	tINS	RR	9	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/F
7.201	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s29/I0
7.580	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s29/F
7.850	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s28/I0
8.229	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3846_s28/F
8.499	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s2
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.995, 64.867%; route: 2.430, 31.557%; tC2Q: 0.275, 3.576%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 12

Path Summary:

Slack	2.226
Data Arrival Time	8.491
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_2_s0
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/I1
5.862	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/F
6.132	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s41/I0
6.511	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s41/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s55/I3
6.970	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s55/F
7.240	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s51/I0
7.619	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s51/F
7.889	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s48/I2
8.221	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3695_s48/F
8.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_2_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_2_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.988, 64.833%; route: 2.430, 31.587%; tC2Q: 0.275, 3.580%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 13

Path Summary:

Slack	2.226
Data Arrival Time	8.491
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1760_s31/I2
6.472	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1760_s31/F
6.742	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s34/I3
6.931	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s34/F
7.201	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s31/I0
7.580	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s31/F
7.850	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s29/I1
8.221	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1765_s29/F
8.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/state_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.988, 64.833%; route: 2.430, 31.587%; tC2Q: 0.275, 3.580%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 14

Path Summary:

Slack	2.233
Data Arrival Time	8.484
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/partner_looking_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/partner_looking_s2/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/partner_looking_s2/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/partner_looking_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/partner_looking_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_looking_ibuf/I
4.572	0.528	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_looking_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s122/I0
5.221	0.379	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s122/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s137/I0
5.870	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s137/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s134/I1
6.511	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s134/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s128/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s128/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s123/I3
7.572	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s123/F
7.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s121/I1
8.214	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2516_s121/F
8.484	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.981, 64.801%; route: 2.430, 31.616%; tC2Q: 0.275, 3.583%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 15

Path Summary:

Slack	2.233
Data Arrival Time	8.484
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_idle_pass_s2
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_idle_pass_s2/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_idle_pass_s2/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_idle_pass_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_train_idle_pass_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_idle_pass_ibuf/I
4.572	0.528	tINS	RR	9	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/train_idle_pass_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s125/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2517_s125/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s18/I0
5.870	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s18/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s13/I1
6.511	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s13/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s7/I3
6.970	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s7/F
7.240	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s3/I2
7.572	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s3/F
7.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s1/I1
8.214	0.372	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s1/F
8.484	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.981, 64.801%; route: 2.430, 31.616%; tC2Q: 0.275, 3.583%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 16

Path Summary:

Slack	2.312
Data Arrival Time	8.405
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/I3
6.329	0.189	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/F
6.599	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/I2
6.931	0.332	tINS	RR	9	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/F
7.201	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s35/I2
7.533	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s35/F
7.803	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s33/I2
8.135	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3844_s33/F
8.405	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.901, 64.435%; route: 2.430, 31.945%; tC2Q: 0.275, 3.620%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 17

Path Summary:

Slack	2.455
Data Arrival Time	8.262
Data Required Time	10.717
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
5.870	0.379	tINS	RR	13	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/I3
6.329	0.189	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_2_s18/F
6.599	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/I2
6.931	0.332	tINS	RR	9	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3852_s29/F
7.201	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s29/I2
7.533	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s29/F
7.803	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s28/I3
7.992	0.189	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3850_s28/F
8.262	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2
10.717	-0.046	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.758, 63.752%; route: 2.430, 32.558%; tC2Q: 0.275, 3.690%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 18

Path Summary:

Slack	2.514
Data Arrival Time	8.025
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_0_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_0_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_0_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_0_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_0_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.792, 66.301%; route: 2.160, 29.888%; tC2Q: 0.275, 3.811%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 19

Path Summary:

Slack	2.514
Data Arrival Time	8.025
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_1_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_1_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_1_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_1_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.792, 66.301%; route: 2.160, 29.888%; tC2Q: 0.275, 3.811%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 20

Path Summary:

Slack	2.514
Data Arrival Time	8.025
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_2_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_2_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_2_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_2_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.792, 66.301%; route: 2.160, 29.888%; tC2Q: 0.275, 3.811%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 21

Path Summary:

Slack	2.514
Data Arrival Time	8.025
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/I0
5.221	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s8/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/I0
5.870	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s7/F
6.140	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/I1
6.511	0.372	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/ts_hot_reset_latch_3_s5/F
6.781	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/I2
7.113	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s6/F
7.383	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/I1
7.755	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s4/F
8.025	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ts_hot_reset_latch_3_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.792, 66.301%; route: 2.160, 29.888%; tC2Q: 0.275, 3.811%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 22

Path Summary:

Slack	2.554
Data Arrival Time	7.986
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
Launch Clk	pclk[R]
Latch Clk	pclk_gowin[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
0.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/CLK
1.074	0.275	tC2Q	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/ltssm_rate_changed_s0/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/I
3.774	2.430	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_rate_changed_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/I
4.572	0.528	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_changed_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/I2
5.174	0.332	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s70/F
5.444	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/I1
5.816	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2603_s68/F
6.086	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/I0
6.465	0.379	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s6/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s2/I2
7.067	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s2/F
7.337	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s3/I0
7.716	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s3/F
7.986	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk_gowin
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
10.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.752, 66.115%; route: 2.160, 30.053%; tC2Q: 0.275, 3.832%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 23

Path Summary:

Slack	2.554
Data Arrival Time	7.986
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/I1
5.862	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/F
6.132	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/I2
6.465	0.332	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/I2
7.067	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/F
7.337	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s4/I0
7.716	0.379	tINS	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s4/F
7.986	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.752, 66.115%; route: 2.160, 30.053%; tC2Q: 0.275, 3.832%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 24

Path Summary:

Slack	2.600
Data Arrival Time	7.939
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_3_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/I1
5.862	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/F
6.132	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/I2
6.465	0.332	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/I2
7.067	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/F
7.337	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s4/I2
7.669	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s4/F
7.939	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_3_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_3_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_3_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.705, 65.893%; route: 2.160, 30.250%; tC2Q: 0.275, 3.857%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%

Path 25

Path Summary:

Slack	2.600
Data Arrival Time	7.939
Data Required Time	10.539
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2
Launch Clk	pclk_gowin[R]
Latch Clk	pclk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				pclk_gowin
0.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/I
0.528	0.528	tINS	RR	348	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/local_clk_ibuf/O
0.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/CLK
1.074	0.275	tC2Q	RR	77	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_3_s1/Q
1.344	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/I
3.774	2.430	tINS	RR	6	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/ltssm_state_3_obuf/O
4.044	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/I
4.572	0.528	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/ltssm_state_3_ibuf/O
4.842	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I0
5.221	0.379	tINS	RR	3	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
5.491	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/I1
5.862	0.372	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s45/F
6.132	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/I2
6.465	0.332	tINS	RR	5	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3898_s14/F
6.735	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/I2
7.067	0.332	tINS	RR	2	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_7_s5/F
7.337	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s4/I2
7.669	0.332	tINS	RR	4	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s4/F
7.939	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	10.000				active clock edge time
10.000	0.000				pclk
10.000	0.000	tCL	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/I
10.528	0.528	tINS	RR	1467	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/local_clk_ibuf/O
10.798	0.270	tNET	RR	1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2/CLK
10.763	-0.035	tUnc			USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2
10.539	-0.224	tSu		1	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_4_s2

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	8
Arrival Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%
Arrival Data Path Delay:	cell: 4.705, 65.893%; route: 2.160, 30.250%; tC2Q: 0.275, 3.857%
Required Clock Path Delay:	cell: 0.528, 66.176%; route: 0.270, 33.824%