Timing Messages

Report Title	Timing Analysis Report
Design File	D:\MXY\project_202607\USB3.x ref design\Gowin_USB3_2_GEN2_BULK_Bandwidth_Test_DK_USB_GW5AT_LV60UG225_V1.0\prj\impl\gwsynthesis\prj.vg
Physical Constraints File	D:\MXY\project_202607\USB3.x ref design\Gowin_USB3_2_GEN2_BULK_Bandwidth_Test_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.cst
Timing Constraint File	D:\MXY\project_202607\USB3.x ref design\Gowin_USB3_2_GEN2_BULK_Bandwidth_Test_DK_USB_GW5AT_LV60UG225_V1.0\prj\src\top.sdc
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5AT-LV60UG225C2/I1
Device	GW5AT-60
Device Version	B
Created Time	Mon Aug 10 16:58:34 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.93V 0C C2/I1
Hold Delay Model	Fast 0.975V 85C C2/I1
Numbers of Paths Analyzed	33018
Numbers of Endpoints Analyzed	47043
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	pclk	Base	6.400	156.250	0.000	3.200			pclk
2	q0_lane1_fabric_rx_clk	Base	6.400	156.250	0.000	3.200			SerDes_Top_inst/q0_lane1_fabric_rx_clk
3	drp_clk	Base	10.000	100.000	0.000	5.000			SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]
4	fclk	Base	41.667	24.000	0.000	20.834			fclk
5	sys_clk_p	Base	10.000	100.000	0.000	5.000			Inst_sys_clk_in/I
6	cnt4_clr	Base	10.000	100.000	0.000	5.000			cnt4_clr_s0/Q

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	pclk	156.250(MHz)	156.274(MHz)	6	TOP
2	q0_lane1_fabric_rx_clk	156.250(MHz)	185.416(MHz)	8	TOP
3	drp_clk	100.000(MHz)	156.120(MHz)	9	TOP
4	fclk	24.000(MHz)	216.022(MHz)	7	TOP
5	sys_clk_p	100.000(MHz)	281.116(MHz)	1	TOP
6	cnt4_clr	100.000(MHz)	1435.542(MHz)	2	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
pclk	Setup	0.000	0
pclk	Hold	0.000	0
q0_lane1_fabric_rx_clk	Setup	0.000	0
q0_lane1_fabric_rx_clk	Hold	0.000	0
drp_clk	Setup	0.000	0
drp_clk	Hold	0.000	0
fclk	Setup	0.000	0
fclk	Hold	0.000	0
sys_clk_p	Setup	0.000	0
sys_clk_p	Hold	0.000	0
cnt4_clr	Setup	0.000	0
cnt4_clr	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.001	UserLayer_top_inst/ControlTransfer_inst/bRequest_latch_2_s0/Q	UserLayer_top_inst/ControlTransfer_inst/request_commit_s1/D	pclk:[R]	pclk:[R]	6.400	0.370	5.865
2	0.243	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_1_s2/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.926
3	0.243	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_2_s2/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.926
4	0.243	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s2/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.926
5	0.284	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.939
6	0.284	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s0/D	pclk:[R]	pclk:[R]	6.400	0.014	5.939
7	0.357	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_0_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.826
8	0.357	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_1_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.826
9	0.357	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_2_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.826
10	0.357	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_3_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.826
11	0.382	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.965
12	0.396	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/CE	pclk:[R]	pclk:[R]	6.400	0.014	5.766
13	0.396	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s1/CE	pclk:[R]	pclk:[R]	6.400	0.014	5.766
14	0.448	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s2/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.735
15	0.454	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0/D	pclk:[R]	pclk:[R]	6.400	-0.014	5.914
16	0.481	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.866
17	0.490	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_2_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.871
18	0.493	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s4/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.676
19	0.507	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[7]_12_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.736
20	0.511	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s4/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.658
21	0.540	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.808
22	0.566	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/D	pclk:[R]	pclk:[R]	6.400	0.000	5.788
23	0.566	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/D	pclk:[R]	pclk:[R]	6.400	0.000	5.788
24	0.623	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.731
25	0.623	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/D	pclk:[R]	pclk:[R]	6.400	0.000	5.731
26	0.633	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s1/CE	pclk:[R]	pclk:[R]	6.400	0.014	5.530
27	0.643	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.711
28	0.643	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/D	pclk:[R]	pclk:[R]	6.400	0.000	5.711
29	0.648	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.700
30	0.648	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.700
31	0.653	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_2_s0/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.523
32	0.654	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_2_s0/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.515
33	0.654	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s0/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.515
34	0.670	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/lfps_send_state_0_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.691
35	0.678	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s0/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.498
36	0.685	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[1]_12_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.663
37	0.689	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_3_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.672
38	0.703	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D	pclk:[R]	pclk:[R]	6.400	0.007	5.644
39	0.719	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_0_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.457
40	0.719	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_1_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.457
41	0.719	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_2_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.457
42	0.721	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.502
43	0.730	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s2/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.453
44	0.731	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.610
45	0.735	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D	pclk:[R]	pclk:[R]	6.400	0.014	5.487
46	0.740	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.442
47	0.746	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D	pclk:[R]	pclk:[R]	6.400	0.014	5.594
48	0.746	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.594
49	0.748	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_3_s4/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.434
50	0.749	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_0_s2/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.611
51	0.753	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s1/D	pclk:[R]	pclk:[R]	6.400	0.000	5.601
52	0.753	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s0/D	pclk:[R]	pclk:[R]	6.400	0.000	5.601
53	0.757	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.479
54	0.770	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_1_s0/CE	pclk:[R]	pclk:[R]	6.400	-0.007	5.413
55	0.780	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.575
56	0.782	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s1/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.461
57	0.782	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.461
58	0.791	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_0_s0/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.378
59	0.791	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_1_s0/CE	pclk:[R]	pclk:[R]	6.400	0.007	5.378
60	0.801	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.560
61	0.837	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D	pclk:[R]	pclk:[R]	6.400	0.007	5.347
62	0.859	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/D	pclk:[R]	pclk:[R]	6.400	0.007	5.371
63	0.863	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[0]_0_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.491
64	0.866	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s0/D	pclk:[R]	pclk:[R]	6.400	0.014	5.475
65	0.872	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_0_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.304
66	0.872	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_1_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.304
67	0.872	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_2_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.304
68	0.877	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.306
69	0.877	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.306
70	0.880	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_3_s4/D	pclk:[R]	pclk:[R]	6.400	0.007	5.467
71	0.883	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/D	pclk:[R]	pclk:[R]	6.400	0.014	5.458
72	0.883	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.458
73	0.884	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_18_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_2_s1/D	pclk:[R]	pclk:[R]	6.400	0.000	5.470
74	0.886	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_15_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_10_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.461
75	0.890	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.471
76	0.890	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/D	pclk:[R]	pclk:[R]	6.400	-0.007	5.471
77	0.892	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[5]_12_s0/D	pclk:[R]	pclk:[R]	6.400	0.000	5.462
78	0.901	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/D	pclk:[R]	pclk:[R]	6.400	-0.363	5.817
79	0.905	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/CE	pclk:[R]	pclk:[R]	6.400	-0.014	5.285
80	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_0_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
81	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_1_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
82	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_2_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
83	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_3_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
84	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_4_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
85	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_5_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
86	0.907	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_6_s0/RESET	pclk:[R]	pclk:[R]	6.400	-0.007	5.232
87	0.908	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/D	pclk:[R]	pclk:[R]	6.400	-0.014	5.296
88	0.909	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/valid_bits_3_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/Empty_s0/D	pclk:[R]	pclk:[R]	6.400	0.007	5.439
89	0.916	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_3_s4/CE	pclk:[R]	pclk:[R]	6.400	0.000	5.260
90	0.937	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s1/D	pclk:[R]	pclk:[R]	6.400	0.014	5.286
91	0.937	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s0/D	pclk:[R]	pclk:[R]	6.400	0.014	5.286
92	0.944	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.286
93	0.946	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/D	pclk:[R]	pclk:[R]	6.400	0.007	5.402
94	0.946	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.402
95	0.955	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_link_busy_s0/D	pclk:[R]	pclk:[R]	6.400	0.014	5.386
96	0.955	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_51_s2/D	pclk:[R]	pclk:[R]	6.400	0.000	5.281
97	0.965	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_0_s2/D	pclk:[R]	pclk:[R]	6.400	0.007	5.382
98	0.966	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/warm_or_hot_reset_s0/D	pclk:[R]	pclk:[R]	6.400	0.000	5.388
99	0.969	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.215
100	0.970	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D	pclk:[R]	pclk:[R]	6.400	0.007	5.260

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.041	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_45_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[14]	pclk:[R]	pclk:[R]	0.000	-0.181	0.256
2	0.043	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_55_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[7]	pclk:[R]	pclk:[R]	0.000	-0.177	0.254
3	0.043	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_58_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[9]	pclk:[R]	pclk:[R]	0.000	-0.177	0.254
4	0.043	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_50_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[1]	pclk:[R]	pclk:[R]	0.000	-0.177	0.254
5	0.043	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_40_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[9]	pclk:[R]	pclk:[R]	0.000	-0.177	0.254
6	0.047	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_59_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[10]	pclk:[R]	pclk:[R]	0.000	-0.174	0.254
7	0.052	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_62_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[13]	pclk:[R]	pclk:[R]	0.000	-0.170	0.256
8	0.058	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_42_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[11]	pclk:[R]	pclk:[R]	0.000	-0.174	0.265
9	0.082	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0]	pclk:[R]	pclk:[R]	0.000	0.000	0.127
10	0.095	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_2_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/ADA[7]	pclk:[R]	pclk:[R]	0.000	-0.177	0.305
11	0.098	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_43_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[12]	pclk:[R]	pclk:[R]	0.000	-0.181	0.312
12	0.102	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_0_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/ADA[5]	pclk:[R]	pclk:[R]	0.000	-0.174	0.309
13	0.107	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_26_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[10]	pclk:[R]	pclk:[R]	0.000	-0.181	0.321
14	0.107	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_48_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[17]	pclk:[R]	pclk:[R]	0.000	-0.181	0.321
15	0.107	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_46_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[15]	pclk:[R]	pclk:[R]	0.000	-0.181	0.321
16	0.109	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_32_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[1]	pclk:[R]	pclk:[R]	0.000	-0.181	0.323
17	0.111	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_53_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[5]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
18	0.111	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_50_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[2]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
19	0.111	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_18_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[2]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
20	0.111	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_16_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[0]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
21	0.111	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_53_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[4]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
22	0.111	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_51_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[2]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
23	0.111	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_49_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[0]	pclk:[R]	pclk:[R]	0.000	-0.177	0.321
24	0.121	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_31_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[15]	pclk:[R]	pclk:[R]	0.000	-0.181	0.335
25	0.121	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_30_s1/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[14]	pclk:[R]	pclk:[R]	0.000	-0.181	0.335

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.668	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/PRESET	pclk:[R]	pclk:[R]	6.400	0.007	4.475
2	1.686	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.007	4.457
3	2.097	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s1/PRESET	pclk:[R]	pclk:[R]	6.400	0.014	4.039
4	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_33_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
5	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_35_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
6	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_97_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
7	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_99_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
8	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_9_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
9	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_13_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
10	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_15_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
11	2.239	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_63_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.897
12	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_5_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
13	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_40_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
14	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_42_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
15	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_18_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
16	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_42_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
17	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_56_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
18	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_82_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
19	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_106_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
20	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_15_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
21	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_30_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
22	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_27_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
23	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_30_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
24	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_31_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896
25	2.241	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_32_s0/CLEAR	pclk:[R]	pclk:[R]	6.400	0.014	3.896

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.307	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_15_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.177	0.436
2	0.307	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_4_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.177	0.436
3	0.307	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_5_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.177	0.436
4	0.307	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_6_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.177	0.436
5	0.307	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_7_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.177	0.436
6	0.350	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt0_10_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.007	0.310
7	0.356	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_1_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.308
8	0.356	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_8_s1/PRESET	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.308
9	0.358	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_rden_o_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.310
10	0.358	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/cur_state_0_s0/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.310
11	0.360	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_11_s0/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.312
12	0.360	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_12_s0/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	0.000	0.312
13	0.385	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_3_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.522
14	0.385	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_value_0_s1/PRESET	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.522
15	0.393	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_2_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.530
16	0.393	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_3_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.530
17	0.393	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_13_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.530
18	0.393	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_14_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.530
19	0.393	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_15_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.185	0.530
20	0.397	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_8_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.181	0.530
21	0.397	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_9_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.181	0.530
22	0.397	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_10_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.181	0.530
23	0.397	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_11_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.181	0.530
24	0.397	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_12_s1/CLEAR	drp_clk:[R]	drp_clk:[R]	0.000	-0.181	0.530
25	0.417	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/Q	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLEAR	pclk:[R]	pclk:[R]	0.000	0.000	0.369

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	1.216	1.992	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
2	1.220	1.995	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s
3	1.220	1.995	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s
4	1.220	1.995	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
5	1.220	1.996	0.776	High Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
6	1.223	1.999	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_1_s
7	1.223	1.999	0.776	Low Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
8	1.223	1.999	0.776	High Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s
9	1.223	1.999	0.776	High Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s
10	1.223	1.999	0.776	High Pulse Width	q0_lane1_fabric_rx_clk	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 100 -max_common_paths 1

Path1

Path Summary:

Slack	0.001
Data Arrival Time	7.742
Data Required Time	7.743
From	UserLayer_top_inst/ControlTransfer_inst/bRequest_latch_2_s0
To	UserLayer_top_inst/ControlTransfer_inst/request_commit_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.876	1.876	tNET	RR	1	R31C9[0][A]	UserLayer_top_inst/ControlTransfer_inst/bRequest_latch_2_s0/CLK
2.152	0.275	tC2Q	RR	8	R31C9[0][A]	UserLayer_top_inst/ControlTransfer_inst/bRequest_latch_2_s0/Q
2.523	0.371	tNET	RR	1	R31C10[3][B]	UserLayer_top_inst/ControlTransfer_inst/n4866_s1/I2
2.881	0.358	tINS	RR	6	R31C10[3][B]	UserLayer_top_inst/ControlTransfer_inst/n4866_s1/F
3.334	0.454	tNET	RR	1	R33C5[1][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s34/I2
3.713	0.379	tINS	RR	2	R33C5[1][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s34/F
3.829	0.115	tNET	RR	1	R33C6[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s31/I1
4.207	0.379	tINS	RR	1	R33C6[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s31/F
4.458	0.250	tNET	RR	1	R32C7[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s26/I3
4.790	0.332	tINS	RR	1	R32C7[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s26/F
5.177	0.387	tNET	RR	1	R30C10[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s23/I2
5.366	0.189	tINS	RR	1	R30C10[0][B]	UserLayer_top_inst/ControlTransfer_inst/n605_s23/F
7.742	2.376	tNET	RR	1	R24C76[0][A]	UserLayer_top_inst/ControlTransfer_inst/request_commit_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R24C76[0][A]	UserLayer_top_inst/ControlTransfer_inst/request_commit_s1/CLK
7.743	-0.164	tSu		1	R24C76[0][A]	UserLayer_top_inst/ControlTransfer_inst/request_commit_s1

Path Statistics:

Clock Skew	-0.370
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.876, 100.000%
Arrival Data Path Delay	cell: 1.637, 27.912%; route: 3.953, 67.393%; tC2Q: 0.275, 4.695%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path2

Path Summary:

Slack	0.243
Data Arrival Time	7.440
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/I2
6.256	0.358	tINS	FR	3	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/F
6.672	0.416	tNET	RR	1	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/I0
7.051	0.379	tINS	RR	3	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/F
7.440	0.389	tNET	RR	1	R18C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R18C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_1_s2/CLK
7.682	-0.224	tSu		1	R18C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_1_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.470, 24.799%; route: 4.192, 70.737%; tC2Q: 0.265, 4.465%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path3

Path Summary:

Slack	0.243
Data Arrival Time	7.440
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_2_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/I2
6.256	0.358	tINS	FR	3	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/F
6.672	0.416	tNET	RR	1	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/I0
7.051	0.379	tINS	RR	3	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/F
7.440	0.389	tNET	RR	1	R18C104[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R18C104[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_2_s2/CLK
7.682	-0.224	tSu		1	R18C104[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_2_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.470, 24.799%; route: 4.192, 70.737%; tC2Q: 0.265, 4.465%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path4

Path Summary:

Slack	0.243
Data Arrival Time	7.440
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/I2
6.256	0.358	tINS	FR	3	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/F
6.672	0.416	tNET	RR	1	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/I0
7.051	0.379	tINS	RR	3	R13C104[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s4/F
7.440	0.389	tNET	RR	1	R18C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R18C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s2/CLK
7.682	-0.224	tSu		1	R18C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_3_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.470, 24.799%; route: 4.192, 70.737%; tC2Q: 0.265, 4.465%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path5

Path Summary:

Slack	0.284
Data Arrival Time	7.459
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.623	0.611	tNET	RR	1	R49C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s31/I2
5.981	0.358	tINS	RR	1	R49C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s31/F
6.080	0.099	tNET	RR	1	R49C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s25/I2
6.459	0.379	tINS	RR	1	R49C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s25/F
6.735	0.275	tNET	RR	1	R49C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s23/I2
7.110	0.375	tINS	RR	2	R49C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s23/F
7.459	0.349	tNET	RR	1	R48C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R48C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s1/CLK
7.743	-0.164	tSu		1	R48C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.863, 31.368%; route: 3.801, 63.995%; tC2Q: 0.275, 4.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path6

Path Summary:

Slack	0.284
Data Arrival Time	7.459
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.623	0.611	tNET	RR	1	R49C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s31/I2
5.981	0.358	tINS	RR	1	R49C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s31/F
6.080	0.099	tNET	RR	1	R49C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s25/I2
6.459	0.379	tINS	RR	1	R49C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s25/F
6.735	0.275	tNET	RR	1	R49C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s23/I2
7.110	0.375	tINS	RR	2	R49C69[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s23/F
7.459	0.349	tNET	RR	1	R48C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R48C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s0/CLK
7.743	-0.164	tSu		1	R48C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.863, 31.368%; route: 3.801, 63.995%; tC2Q: 0.275, 4.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path7

Path Summary:

Slack	0.357
Data Arrival Time	7.339
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_0_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
7.339	0.591	tNET	RR	1	R21C102[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_0_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R21C102[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_0_s4/CLK
7.696	-0.224	tSu		1	R21C102[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_0_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.483, 25.460%; route: 4.078, 69.998%; tC2Q: 0.265, 4.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path8

Path Summary:

Slack	0.357
Data Arrival Time	7.339
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_1_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
7.339	0.591	tNET	RR	1	R22C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_1_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R22C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_1_s4/CLK
7.696	-0.224	tSu		1	R22C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_1_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.483, 25.460%; route: 4.078, 69.998%; tC2Q: 0.265, 4.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path9

Path Summary:

Slack	0.357
Data Arrival Time	7.339
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_2_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
7.339	0.591	tNET	RR	1	R21C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_2_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R21C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_2_s4/CLK
7.696	-0.224	tSu		1	R21C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_2_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.483, 25.460%; route: 4.078, 69.998%; tC2Q: 0.265, 4.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path10

Path Summary:

Slack	0.357
Data Arrival Time	7.339
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_3_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
7.339	0.591	tNET	RR	1	R22C102[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_3_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R22C102[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_3_s4/CLK
7.696	-0.224	tSu		1	R22C102[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_3_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.483, 25.460%; route: 4.078, 69.998%; tC2Q: 0.265, 4.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path11

Path Summary:

Slack	0.382
Data Arrival Time	7.485
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.112	2.317	tNET	RR	1	R44C61[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s8/I2
4.444	0.332	tINS	RR	2	R44C61[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s8/F
4.448	0.004	tNET	RR	1	R44C61[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24965_s2/I2
4.657	0.209	tINS	RF	4	R44C61[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24965_s2/F
5.116	0.460	tNET	FF	1	R45C68[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s34/I0
5.305	0.189	tINS	FR	1	R45C68[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s34/F
5.419	0.113	tNET	RR	1	R46C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s29/I3
5.777	0.358	tINS	RR	1	R46C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s29/F
5.779	0.002	tNET	RR	1	R46C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s24/I1
6.158	0.379	tINS	RR	1	R46C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s24/F
6.548	0.391	tNET	RR	1	R46C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/I1
6.920	0.372	tINS	RR	2	R46C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/F
7.485	0.565	tNET	RR	1	R44C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R44C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1/CLK
7.867	-0.046	tSu		1	R44C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.839, 30.824%; route: 3.851, 64.559%; tC2Q: 0.275, 4.617%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path12

Path Summary:

Slack	0.396
Data Arrival Time	7.286
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/CLK
1.795	0.275	tC2Q	RR	207	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q
4.428	2.632	tNET	RR	1	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/I0
4.807	0.379	tINS	RR	5	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/F
6.079	1.273	tNET	RR	1	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/I0
6.412	0.332	tINS	RR	2	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/F
6.527	0.115	tNET	RR	1	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/I3
6.826	0.299	tINS	RR	2	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/F
6.829	0.004	tNET	RR	1	R63C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s4/I2
7.187	0.358	tINS	RR	2	R63C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s4/F
7.286	0.099	tNET	RR	1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/CLK
7.682	-0.224	tSu		1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.368, 23.724%; route: 4.123, 71.500%; tC2Q: 0.275, 4.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path13

Path Summary:

Slack	0.396
Data Arrival Time	7.286
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/CLK
1.795	0.275	tC2Q	RR	207	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q
4.428	2.632	tNET	RR	1	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/I0
4.807	0.379	tINS	RR	5	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/F
6.079	1.273	tNET	RR	1	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/I0
6.412	0.332	tINS	RR	2	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/F
6.527	0.115	tNET	RR	1	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/I3
6.826	0.299	tINS	RR	2	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/F
6.829	0.004	tNET	RR	1	R63C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s4/I2
7.187	0.358	tINS	RR	2	R63C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s4/F
7.286	0.099	tNET	RR	1	R63C76[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R63C76[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s1/CLK
7.682	-0.224	tSu		1	R63C76[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_1_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.368, 23.724%; route: 4.123, 71.500%; tC2Q: 0.275, 4.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path14

Path Summary:

Slack	0.448
Data Arrival Time	7.241
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/CLK
1.782	0.275	tC2Q	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q
2.076	0.294	tNET	RR	1	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/I0
2.452	0.375	tINS	RR	18	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/F
4.262	1.811	tNET	RR	1	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/I0
4.638	0.375	tINS	RR	13	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/F
4.931	0.293	tNET	RR	1	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/I2
5.140	0.209	tINS	RF	2	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/F
5.147	0.007	tNET	FF	1	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/I2
5.505	0.358	tINS	FR	13	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/F
5.764	0.259	tNET	RR	1	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/I0
6.136	0.372	tINS	RR	4	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/F
6.527	0.391	tNET	RR	1	R13C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s4/I0
6.718	0.191	tINS	RR	1	R13C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s4/F
7.241	0.524	tNET	RR	1	R13C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R13C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s2/CLK
7.689	-0.224	tSu		1	R13C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_0_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.880, 32.784%; route: 3.579, 62.414%; tC2Q: 0.275, 4.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path15

Path Summary:

Slack	0.454
Data Arrival Time	7.420
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
3.784	2.012	tNET	FF	1	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/I1
4.162	0.379	tINS	FR	10	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/F
4.616	0.454	tNET	RR	1	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/I3
4.948	0.332	tINS	RR	9	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/F
5.196	0.248	tNET	RR	1	R11C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s99/I1
5.554	0.358	tINS	RR	1	R11C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s99/F
6.078	0.524	tNET	RR	1	R8C93[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s92/I3
6.453	0.375	tINS	RR	1	R8C93[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s92/F
7.049	0.596	tNET	RR	1	R6C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s89/I3
7.420	0.372	tINS	RR	1	R6C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2522_s89/F
7.420	0.000	tNET	RR	1	R6C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R6C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0/CLK
7.874	-0.046	tSu		1	R6C90[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/dc_rst_n_s0

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.816, 30.711%; route: 3.833, 64.815%; tC2Q: 0.265, 4.474%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path16

Path Summary:

Slack	0.481
Data Arrival Time	7.386
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.112	2.317	tNET	RR	1	R44C61[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s8/I2
4.444	0.332	tINS	RR	2	R44C61[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s8/F
4.448	0.004	tNET	RR	1	R44C61[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24965_s2/I2
4.657	0.209	tINS	RF	4	R44C61[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24965_s2/F
5.116	0.460	tNET	FF	1	R45C68[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s34/I0
5.305	0.189	tINS	FR	1	R45C68[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s34/F
5.419	0.113	tNET	RR	1	R46C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s29/I3
5.777	0.358	tINS	RR	1	R46C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s29/F
5.779	0.002	tNET	RR	1	R46C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s24/I1
6.158	0.379	tINS	RR	1	R46C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s24/F
6.548	0.391	tNET	RR	1	R46C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/I1
6.920	0.372	tINS	RR	2	R46C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3754_s22/F
7.386	0.466	tNET	RR	1	R44C62[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R44C62[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0/CLK
7.867	-0.046	tSu		1	R44C62[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_9_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.839, 31.344%; route: 3.752, 63.961%; tC2Q: 0.275, 4.695%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path17

Path Summary:

Slack	0.490
Data Arrival Time	7.377
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_2_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
3.784	2.012	tNET	FF	1	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/I1
4.162	0.379	tINS	FR	10	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/F
4.616	0.454	tNET	RR	1	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/I3
4.948	0.332	tINS	RR	9	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/F
5.384	0.436	tNET	RR	1	R4C99[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s75/I0
5.716	0.332	tINS	RR	1	R4C99[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s75/F
6.299	0.583	tNET	RR	1	R9C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s72/I3
6.631	0.332	tINS	RR	1	R9C96[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s72/F
7.045	0.414	tNET	RR	1	R9C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s70/I2
7.377	0.332	tINS	RR	1	R9C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2538_s70/F
7.377	0.000	tNET	RR	1	R9C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R9C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_2_s0/CLK
7.867	-0.046	tSu		1	R9C91[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_2_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.707, 29.082%; route: 3.899, 66.411%; tC2Q: 0.265, 4.507%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path18

Path Summary:

Slack	0.493
Data Arrival Time	7.190
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
7.190	0.634	tNET	RR	1	R24C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R24C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s4/CLK
7.682	-0.224	tSu		1	R24C96[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s4

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.403, 24.719%; route: 4.009, 70.620%; tC2Q: 0.265, 4.661%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path19

Path Summary:

Slack	0.507
Data Arrival Time	7.249
Data Required Time	7.756
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[7]_12_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/CLK
1.789	0.275	tC2Q	RR	5	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q
3.085	1.296	tNET	RR	1	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/I2
3.464	0.379	tINS	RR	3	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/F
3.717	0.254	tNET	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/I3
4.093	0.375	tINS	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/F
4.343	0.250	tNET	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/I2
4.722	0.379	tINS	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/F
5.573	0.851	tNET	RR	1	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/I0
5.949	0.375	tINS	RR	9	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/F
7.249	1.301	tNET	RR	1	R42C106[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[7]_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R42C106[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[7]_12_s0/CLK
7.756	-0.164	tSu		1	R42C106[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[7]_12_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.508, 26.298%; route: 3.952, 68.900%; tC2Q: 0.275, 4.802%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path20

Path Summary:

Slack	0.511
Data Arrival Time	7.172
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
7.172	0.424	tNET	RR	1	R24C100[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R24C100[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s4/CLK
7.682	-0.224	tSu		1	R24C100[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s4

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.483, 26.213%; route: 3.911, 69.111%; tC2Q: 0.265, 4.676%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path21

Path Summary:

Slack	0.540
Data Arrival Time	7.321
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R16C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/CLK
1.778	0.265	tC2Q	RF	137	R16C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/Q
3.375	1.597	tNET	FF	1	R2C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s1/I0
3.751	0.375	tINS	FR	12	R2C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s1/F
4.238	0.487	tNET	RR	1	R11C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s16/I2
4.617	0.379	tINS	RR	1	R11C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s16/F
4.716	0.099	tNET	RR	1	R11C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s12/I3
5.048	0.332	tINS	RR	1	R11C88[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s12/F
5.409	0.362	tNET	RR	1	R12C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s7/I2
5.788	0.379	tINS	RR	1	R12C92[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s7/F
5.927	0.139	tNET	RR	1	R11C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s3/I2
6.306	0.379	tINS	RR	1	R11C92[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s3/F
6.308	0.002	tNET	RR	1	R11C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s1/I1
6.497	0.189	tINS	RR	1	R11C92[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6199_s1/F
7.321	0.824	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
7.861	-0.046	tSu		1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.033, 35.007%; route: 3.510, 60.437%; tC2Q: 0.265, 4.556%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path22

Path Summary:

Slack	0.566
Data Arrival Time	7.301
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R51C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/CLK
1.789	0.275	tC2Q	RR	7	R51C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/Q
2.502	0.714	tNET	RR	1	R50C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s45/I1
2.874	0.372	tINS	RR	3	R50C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s45/F
3.223	0.349	tNET	RR	1	R51C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s33/I3
3.412	0.189	tINS	RR	2	R51C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s33/F
4.618	1.206	tNET	RR	1	R52C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s31/I2
4.807	0.189	tINS	RR	1	R52C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s31/F
4.809	0.002	tNET	RR	1	R52C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/I3
5.141	0.332	tINS	RR	2	R52C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/F
6.016	0.875	tNET	RR	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/I0
6.205	0.189	tINS	RR	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/F
6.499	0.294	tNET	RR	1	R46C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/I2
6.875	0.375	tINS	RR	2	R46C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/F
7.301	0.427	tNET	RR	1	R44C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R44C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1/CLK
7.867	-0.046	tSu		1	R44C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.646, 28.440%; route: 3.866, 66.801%; tC2Q: 0.275, 4.758%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path23

Path Summary:

Slack	0.566
Data Arrival Time	7.301
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R51C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/CLK
1.789	0.275	tC2Q	RR	7	R51C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_12_s0/Q
2.502	0.714	tNET	RR	1	R50C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s45/I1
2.874	0.372	tINS	RR	3	R50C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s45/F
3.223	0.349	tNET	RR	1	R51C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s33/I3
3.412	0.189	tINS	RR	2	R51C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3757_s33/F
4.618	1.206	tNET	RR	1	R52C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s31/I2
4.807	0.189	tINS	RR	1	R52C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s31/F
4.809	0.002	tNET	RR	1	R52C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/I3
5.141	0.332	tINS	RR	2	R52C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s26/F
6.016	0.875	tNET	RR	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/I0
6.205	0.189	tINS	RR	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s24/F
6.499	0.294	tNET	RR	1	R46C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/I2
6.875	0.375	tINS	RR	2	R46C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3760_s22/F
7.301	0.427	tNET	RR	1	R44C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R44C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0/CLK
7.867	-0.046	tSu		1	R44C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.646, 28.440%; route: 3.866, 66.801%; tC2Q: 0.275, 4.758%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path24

Path Summary:

Slack	0.623
Data Arrival Time	7.244
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.407	1.619	tNET	RR	1	R59C73[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
3.739	0.332	tINS	RR	1	R59C73[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
3.840	0.101	tNET	RR	1	R59C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.172	0.332	tINS	RR	3	R59C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.079	0.906	tNET	RR	1	R40C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/I2
5.411	0.332	tINS	RR	1	R40C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/F
6.037	0.626	tNET	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/I1
6.369	0.332	tINS	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/F
6.622	0.253	tNET	RR	1	R54C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/I0
6.954	0.332	tINS	RR	2	R54C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/F
7.244	0.290	tNET	RR	1	R54C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R54C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2/CLK
7.867	-0.046	tSu		1	R54C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.660, 28.975%; route: 3.795, 66.219%; tC2Q: 0.275, 4.806%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path25

Path Summary:

Slack	0.623
Data Arrival Time	7.244
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.407	1.619	tNET	RR	1	R59C73[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/I2
3.739	0.332	tINS	RR	1	R59C73[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_22_s8/F
3.840	0.101	tNET	RR	1	R59C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/I2
4.172	0.332	tINS	RR	3	R59C73[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3097_s18/F
5.079	0.906	tNET	RR	1	R40C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/I2
5.411	0.332	tINS	RR	1	R40C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s4/F
6.037	0.626	tNET	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/I1
6.369	0.332	tINS	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s2/F
6.622	0.253	tNET	RR	1	R54C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/I0
6.954	0.332	tINS	RR	2	R54C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5556_s1/F
7.244	0.290	tNET	RR	1	R54C66[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R54C66[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1/CLK
7.867	-0.046	tSu		1	R54C66[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_46_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.660, 28.975%; route: 3.795, 66.219%; tC2Q: 0.275, 4.806%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path26

Path Summary:

Slack	0.633
Data Arrival Time	7.050
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/CLK
1.795	0.275	tC2Q	RR	207	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q
4.428	2.632	tNET	RR	1	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/I0
4.807	0.379	tINS	RR	5	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/F
6.079	1.273	tNET	RR	1	R64C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s4/I1
6.378	0.299	tINS	RR	1	R64C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s4/F
6.575	0.197	tNET	RR	1	R66C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s3/I1
6.951	0.375	tINS	RR	1	R66C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s3/F
7.050	0.099	tNET	RR	1	R66C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R66C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s1/CLK
7.682	-0.224	tSu		1	R66C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_hp_req_ack_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.053, 19.043%; route: 4.201, 75.977%; tC2Q: 0.275, 4.980%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path27

Path Summary:

Slack	0.643
Data Arrival Time	7.224
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.409	1.620	tNET	RR	1	R59C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.767	0.358	tINS	RR	1	R59C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
3.771	0.004	tNET	RR	1	R59C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.070	0.299	tINS	RR	3	R59C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
4.877	0.807	tNET	RR	1	R39C67[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/I2
5.209	0.332	tINS	RR	1	R39C67[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/F
5.681	0.472	tNET	RR	1	R45C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/I1
5.980	0.299	tINS	RR	1	R45C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/F
6.289	0.310	tNET	RR	1	R53C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/I0
6.668	0.379	tINS	RR	2	R53C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/F
7.224	0.556	tNET	RR	1	R54C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R54C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2/CLK
7.867	-0.046	tSu		1	R54C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.667, 29.186%; route: 3.769, 65.992%; tC2Q: 0.275, 4.822%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path28

Path Summary:

Slack	0.643
Data Arrival Time	7.224
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.409	1.620	tNET	RR	1	R59C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/I2
3.767	0.358	tINS	RR	1	R59C76[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_25_s8/F
3.771	0.004	tNET	RR	1	R59C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/I2
4.070	0.299	tINS	RR	3	R59C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3094_s18/F
4.877	0.807	tNET	RR	1	R39C67[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/I2
5.209	0.332	tINS	RR	1	R39C67[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s4/F
5.681	0.472	tNET	RR	1	R45C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/I1
5.980	0.299	tINS	RR	1	R45C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s2/F
6.289	0.310	tNET	RR	1	R53C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/I0
6.668	0.379	tINS	RR	2	R53C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5569_s1/F
7.224	0.556	tNET	RR	1	R54C64[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R54C64[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1/CLK
7.867	-0.046	tSu		1	R54C64[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_33_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.667, 29.186%; route: 3.769, 65.992%; tC2Q: 0.275, 4.822%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path29

Path Summary:

Slack	0.648
Data Arrival Time	7.220
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s8/I2
4.628	0.372	tINS	RR	3	R43C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s8/F
4.633	0.005	tNET	RR	1	R43C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n25025_s3/I2
5.008	0.375	tINS	RR	2	R43C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n25025_s3/F
5.260	0.252	tNET	RR	1	R44C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s23/I1
5.639	0.379	tINS	RR	1	R44C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s23/F
5.875	0.236	tNET	RR	1	R46C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s22/I3
6.064	0.189	tINS	RR	1	R46C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s22/F
6.066	0.002	tNET	RR	1	R46C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s20/I3
6.445	0.379	tINS	RR	1	R46C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s20/F
6.695	0.250	tNET	RR	1	R45C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s18/I2
7.027	0.332	tINS	RR	2	R45C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s18/F
7.220	0.193	tNET	RR	1	R45C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R45C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s1/CLK
7.867	-0.046	tSu		1	R45C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.026, 35.544%; route: 3.398, 59.624%; tC2Q: 0.275, 4.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path30

Path Summary:

Slack	0.648
Data Arrival Time	7.220
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s8/I2
4.628	0.372	tINS	RR	3	R43C62[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s8/F
4.633	0.005	tNET	RR	1	R43C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n25025_s3/I2
5.008	0.375	tINS	RR	2	R43C62[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n25025_s3/F
5.260	0.252	tNET	RR	1	R44C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s23/I1
5.639	0.379	tINS	RR	1	R44C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s23/F
5.875	0.236	tNET	RR	1	R46C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s22/I3
6.064	0.189	tINS	RR	1	R46C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s22/F
6.066	0.002	tNET	RR	1	R46C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s20/I3
6.445	0.379	tINS	RR	1	R46C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s20/F
6.695	0.250	tNET	RR	1	R45C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s18/I2
7.027	0.332	tINS	RR	2	R45C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3704_s18/F
7.220	0.193	tNET	RR	1	R45C62[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R45C62[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s0/CLK
7.867	-0.046	tSu		1	R45C62[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_59_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.026, 35.544%; route: 3.398, 59.624%; tC2Q: 0.275, 4.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path31

Path Summary:

Slack	0.653
Data Arrival Time	7.037
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_2_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.789	0.275	tC2Q	RR	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
3.171	1.382	tNET	RR	1	R52C94[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_d_s/I2
3.503	0.332	tINS	RR	7	R52C94[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_d_s/F
5.031	1.528	tNET	RR	1	R15C101[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s0/I0
5.403	0.372	tINS	RR	3	R15C101[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s0/F
7.037	1.634	tNET	RR	1	R58C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R58C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_2_s0/CLK
7.689	-0.224	tSu		1	R58C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 0.704, 12.742%; route: 4.544, 82.271%; tC2Q: 0.275, 4.986%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path32

Path Summary:

Slack	0.654
Data Arrival Time	7.029
Data Required Time	7.682
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_2_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	18	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB
2.961	1.447	tC2Q	RR	7	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]
3.686	0.725	tNET	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/I0
4.065	0.379	tINS	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/F
4.529	0.464	tNET	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/I3
4.887	0.358	tINS	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/F
4.986	0.099	tNET	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/I3
5.319	0.332	tINS	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/F
5.666	0.347	tNET	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/I2
6.045	0.379	tINS	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/F
6.158	0.113	tNET	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/I3
6.457	0.299	tINS	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/F
6.459	0.002	tNET	RR	1	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/I1
6.791	0.332	tINS	RR	4	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/F
7.029	0.238	tNET	RR	1	R49C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R49C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_2_s0/CLK
7.682	-0.224	tSu		1	R49C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_2_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.079, 37.696%; route: 1.989, 36.064%; tC2Q: 1.447, 26.240%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path33

Path Summary:

Slack	0.654
Data Arrival Time	7.029
Data Required Time	7.682
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	18	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB
2.961	1.447	tC2Q	RR	7	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]
3.686	0.725	tNET	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/I0
4.065	0.379	tINS	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/F
4.529	0.464	tNET	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/I3
4.887	0.358	tINS	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/F
4.986	0.099	tNET	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/I3
5.319	0.332	tINS	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/F
5.666	0.347	tNET	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/I2
6.045	0.379	tINS	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/F
6.158	0.113	tNET	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/I3
6.457	0.299	tINS	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/F
6.459	0.002	tNET	RR	1	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/I1
6.791	0.332	tINS	RR	4	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/F
7.029	0.238	tNET	RR	1	R49C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R49C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s0/CLK
7.682	-0.224	tSu		1	R49C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.079, 37.696%; route: 1.989, 36.064%; tC2Q: 1.447, 26.240%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path34

Path Summary:

Slack	0.670
Data Arrival Time	7.197
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/lfps_send_state_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
3.825	2.054	tNET	FF	1	R7C98[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6192_s3/I0
4.197	0.372	tINS	FR	5	R7C98[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n6192_s3/F
4.459	0.262	tNET	RR	1	R8C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n4995_s40/I0
4.757	0.299	tINS	RR	4	R8C96[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n4995_s40/F
4.999	0.241	tNET	RR	1	R8C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s40/I0
5.331	0.332	tINS	RR	1	R8C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s40/F
5.736	0.405	tNET	RR	1	R8C101[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s37/I3
6.115	0.379	tINS	RR	1	R8C101[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s37/F
6.383	0.268	tNET	RR	1	R9C100[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s31/I3
6.572	0.189	tINS	RR	1	R9C100[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s31/F
6.822	0.250	tNET	RR	1	R11C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s28/I3
7.197	0.375	tINS	RR	1	R11C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n5000_s28/F
7.197	0.000	tNET	RR	1	R11C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/lfps_send_state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R11C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/lfps_send_state_0_s0/CLK
7.867	-0.046	tSu		1	R11C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/lfps_send_state_0_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.946, 34.193%; route: 3.480, 61.158%; tC2Q: 0.265, 4.650%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path35

Path Summary:

Slack	0.678
Data Arrival Time	7.005
Data Required Time	7.682
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.675	2.903	tNET	FF	1	R8C105[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_rate_s6/I1
4.864	0.189	tINS	FR	1	R8C105[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_rate_s6/F
4.963	0.099	tNET	RR	1	R8C105[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_rate_s7/I1
5.152	0.189	tINS	RR	2	R8C105[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/partner_rate_s7/F
5.507	0.355	tNET	RR	1	R8C95[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s6/I3
5.879	0.372	tINS	RR	1	R8C95[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s6/F
6.278	0.400	tNET	RR	1	R8C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s10/I3
6.657	0.379	tINS	RR	1	R8C91[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s10/F
7.005	0.347	tNET	RR	1	R8C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R8C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s0/CLK
7.682	-0.224	tSu		1	R8C88[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_r_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.129, 20.527%; route: 4.105, 74.660%; tC2Q: 0.265, 4.813%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path36

Path Summary:

Slack	0.685
Data Arrival Time	7.176
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[1]_12_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/CLK
1.789	0.275	tC2Q	RR	5	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q
3.085	1.296	tNET	RR	1	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/I2
3.464	0.379	tINS	RR	3	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/F
3.717	0.254	tNET	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/I3
4.093	0.375	tINS	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/F
4.343	0.250	tNET	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/I2
4.722	0.379	tINS	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/F
5.573	0.851	tNET	RR	1	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/I0
5.949	0.375	tINS	RR	9	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/F
7.176	1.228	tNET	RR	1	R45C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[1]_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[1]_12_s0/CLK
7.861	-0.046	tSu		1	R45C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[1]_12_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.508, 26.637%; route: 3.879, 68.500%; tC2Q: 0.275, 4.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path37

Path Summary:

Slack	0.689
Data Arrival Time	7.178
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
3.784	2.012	tNET	FF	1	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/I1
4.162	0.379	tINS	FR	10	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/F
4.515	0.353	tNET	RR	1	R4C98[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s79/I3
4.887	0.372	tINS	RR	6	R4C98[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s79/F
5.238	0.351	tNET	RR	1	R4C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s81/I3
5.596	0.358	tINS	RR	1	R4C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s81/F
6.120	0.524	tNET	RR	1	R7C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s74/I2
6.499	0.379	tINS	RR	1	R7C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s74/F
6.846	0.347	tNET	RR	1	R9C95[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s70/I3
7.178	0.332	tINS	RR	1	R9C95[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2537_s70/F
7.178	0.000	tNET	RR	1	R9C95[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R9C95[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_3_s0/CLK
7.867	-0.046	tSu		1	R9C95[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_3_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.820, 32.085%; route: 3.587, 63.250%; tC2Q: 0.265, 4.665%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path38

Path Summary:

Slack	0.703
Data Arrival Time	7.164
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/I2
4.146	0.189	tINS	RR	2	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/F
4.249	0.103	tNET	RR	1	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/I2
4.548	0.299	tINS	RR	4	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/F
5.162	0.615	tNET	RR	1	R48C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s6/I0
5.541	0.379	tINS	RR	1	R48C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s6/F
5.875	0.334	tNET	RR	1	R45C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s3/I1
6.064	0.189	tINS	RR	1	R45C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s3/F
6.163	0.099	tNET	RR	1	R45C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I3
6.542	0.379	tINS	RR	2	R45C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F
7.164	0.622	tNET	RR	1	R49C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R49C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2/CLK
7.867	-0.046	tSu		1	R49C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.435, 25.419%; route: 3.934, 69.702%; tC2Q: 0.275, 4.880%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path39

Path Summary:

Slack	0.719
Data Arrival Time	6.970
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_0_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
6.970	0.415	tNET	RR	1	R22C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_0_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R22C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_0_s4/CLK
7.689	-0.224	tSu		1	R22C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_0_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.403, 25.713%; route: 3.789, 69.438%; tC2Q: 0.265, 4.849%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path40

Path Summary:

Slack	0.719
Data Arrival Time	6.970
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_1_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
6.970	0.415	tNET	RR	1	R22C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_1_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R22C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_1_s4/CLK
7.689	-0.224	tSu		1	R22C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_1_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.403, 25.713%; route: 3.789, 69.438%; tC2Q: 0.265, 4.849%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path41

Path Summary:

Slack	0.719
Data Arrival Time	6.970
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_2_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
6.970	0.415	tNET	RR	1	R22C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_2_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R22C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_2_s4/CLK
7.689	-0.224	tSu		1	R22C101[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_2_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.403, 25.713%; route: 3.789, 69.438%; tC2Q: 0.265, 4.849%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path42

Path Summary:

Slack	0.721
Data Arrival Time	7.022
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.209	2.414	tNET	RR	1	R44C61[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_14_s8/I2
4.585	0.375	tINS	RR	2	R44C61[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_14_s8/F
4.588	0.004	tNET	RR	1	R44C61[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24960_s3/I2
4.967	0.379	tINS	RR	4	R44C61[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24960_s3/F
5.435	0.468	tNET	RR	1	R45C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s6/I0
5.767	0.332	tINS	RR	1	R45C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s6/F
6.017	0.250	tNET	RR	1	R42C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/I1
6.396	0.379	tINS	RR	1	R42C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/F
6.398	0.002	tNET	RR	1	R42C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I3
6.770	0.372	tINS	RR	2	R42C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F
7.022	0.252	tNET	RR	1	R41C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R41C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1/CLK
7.743	-0.164	tSu		1	R41C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.837, 33.388%; route: 3.389, 61.606%; tC2Q: 0.275, 5.006%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path43

Path Summary:

Slack	0.730
Data Arrival Time	6.960
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/CLK
1.782	0.275	tC2Q	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q
2.076	0.294	tNET	RR	1	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/I0
2.452	0.375	tINS	RR	18	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/F
4.262	1.811	tNET	RR	1	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/I0
4.638	0.375	tINS	RR	13	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/F
4.931	0.293	tNET	RR	1	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/I2
5.140	0.209	tINS	RF	2	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/F
5.147	0.007	tNET	FF	1	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/I2
5.505	0.358	tINS	FR	13	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/F
5.764	0.259	tNET	RR	1	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/I0
6.136	0.372	tINS	RR	4	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/F
6.392	0.256	tNET	RR	1	R14C103[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s4/I0
6.724	0.332	tINS	RR	1	R14C103[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s4/F
6.960	0.236	tNET	RR	1	R15C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R15C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s2/CLK
7.689	-0.224	tSu		1	R15C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_2_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 2.021, 37.069%; route: 3.156, 57.881%; tC2Q: 0.275, 5.050%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path44

Path Summary:

Slack	0.731
Data Arrival Time	7.130
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/CLK
1.795	0.275	tC2Q	RR	207	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q
4.428	2.632	tNET	RR	1	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/I0
4.807	0.379	tINS	RR	5	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/F
6.079	1.273	tNET	RR	1	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/I0
6.412	0.332	tINS	RR	2	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/F
6.527	0.115	tNET	RR	1	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/I3
6.826	0.299	tINS	RR	2	R63C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5082_s5/F
7.130	0.304	tNET	RR	1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1/CLK
7.861	-0.046	tSu		1	R63C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_sel_0_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.010, 18.001%; route: 4.325, 77.090%; tC2Q: 0.275, 4.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path45

Path Summary:

Slack	0.735
Data Arrival Time	7.007
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.209	2.414	tNET	RR	1	R44C61[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_14_s8/I2
4.585	0.375	tINS	RR	2	R44C61[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_14_s8/F
4.588	0.004	tNET	RR	1	R44C61[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24960_s3/I2
4.967	0.379	tINS	RR	4	R44C61[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24960_s3/F
5.435	0.468	tNET	RR	1	R45C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s6/I0
5.767	0.332	tINS	RR	1	R45C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s6/F
6.017	0.250	tNET	RR	1	R42C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/I1
6.396	0.379	tINS	RR	1	R42C68[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s3/F
6.398	0.002	tNET	RR	1	R42C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/I3
6.770	0.372	tINS	RR	2	R42C68[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5580_s0/F
7.007	0.238	tNET	RR	1	R42C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R42C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2/CLK
7.743	-0.164	tSu		1	R42C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_22_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.837, 33.475%; route: 3.375, 61.506%; tC2Q: 0.275, 5.019%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path46

Path Summary:

Slack	0.740
Data Arrival Time	6.956
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/I0
5.175	0.400	tINS	RF	4	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/COUT
5.647	0.472	tNET	FF	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/I0
6.005	0.358	tINS	FR	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/F
6.007	0.002	tNET	RR	1	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/I2
6.365	0.358	tINS	RR	6	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/F
6.956	0.590	tNET	RR	1	R23C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R23C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s4/CLK
7.696	-0.224	tSu		1	R23C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.449, 26.625%; route: 3.729, 68.513%; tC2Q: 0.265, 4.862%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path47

Path Summary:

Slack	0.746
Data Arrival Time	7.114
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.583	0.571	tNET	RR	1	R41C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s6/I0
5.915	0.332	tINS	RR	1	R41C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s6/F
6.028	0.113	tNET	RR	1	R40C69[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/I1
6.217	0.189	tINS	RR	1	R40C69[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/F
6.316	0.099	tNET	RR	1	R40C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I3
6.648	0.332	tINS	RR	2	R40C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F
7.114	0.466	tNET	RR	1	R39C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R39C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2/CLK
7.861	-0.046	tSu		1	R39C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.604, 28.668%; route: 3.715, 66.409%; tC2Q: 0.275, 4.923%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path48

Path Summary:

Slack	0.746
Data Arrival Time	7.114
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.583	0.571	tNET	RR	1	R41C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s6/I0
5.915	0.332	tINS	RR	1	R41C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s6/F
6.028	0.113	tNET	RR	1	R40C69[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/I1
6.217	0.189	tINS	RR	1	R40C69[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s3/F
6.316	0.099	tNET	RR	1	R40C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/I3
6.648	0.332	tINS	RR	2	R40C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5572_s0/F
7.114	0.466	tNET	RR	1	R39C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R39C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1/CLK
7.861	-0.046	tSu		1	R39C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_30_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.604, 28.668%; route: 3.715, 66.409%; tC2Q: 0.275, 4.923%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path49

Path Summary:

Slack	0.748
Data Arrival Time	6.948
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_3_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
6.948	0.392	tNET	RR	1	R23C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_3_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R23C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_3_s4/CLK
7.696	-0.224	tSu		1	R23C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_3_s4

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.403, 25.820%; route: 3.766, 69.311%; tC2Q: 0.265, 4.869%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path50

Path Summary:

Slack	0.749
Data Arrival Time	7.125
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/I0
6.277	0.379	tINS	FR	1	R16C102[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s6/F
6.376	0.099	tNET	RR	1	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/I2
6.748	0.372	tINS	RR	6	R16C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[2]_4_s5/F
6.753	0.005	tNET	RR	1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2322_s23/I2
7.125	0.372	tINS	RR	1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2322_s23/F
7.125	0.000	tNET	RR	1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_0_s2/CLK
7.874	-0.046	tSu		1	R16C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_0_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.855, 33.055%; route: 3.492, 62.229%; tC2Q: 0.265, 4.715%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path51

Path Summary:

Slack	0.753
Data Arrival Time	7.121
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R42C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s8/I2
4.146	0.189	tINS	RR	2	R42C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s8/F
4.263	0.117	tNET	RR	1	R42C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s28/I2
4.635	0.372	tINS	RR	4	R42C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s28/F
5.335	0.700	tNET	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s37/I1
5.667	0.332	tINS	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s37/F
5.667	0.000	tNET	RR	1	R48C72[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s33/I1
5.765	0.098	tINS	RR	1	R48C72[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s33/O
5.765	0.000	tNET	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s24/I1
5.827	0.062	tINS	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s24/O
6.505	0.678	tNET	RR	1	R45C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s27/I0
6.694	0.189	tINS	RR	2	R45C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s27/F
7.121	0.427	tNET	RR	1	R43C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R43C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s1/CLK
7.874	-0.046	tSu		1	R43C65[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.242, 22.176%; route: 4.083, 72.907%; tC2Q: 0.275, 4.917%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path52

Path Summary:

Slack	0.753
Data Arrival Time	7.121
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R42C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s8/I2
4.146	0.189	tINS	RR	2	R42C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s8/F
4.263	0.117	tNET	RR	1	R42C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s28/I2
4.635	0.372	tINS	RR	4	R42C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s28/F
5.335	0.700	tNET	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s37/I1
5.667	0.332	tINS	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s37/F
5.667	0.000	tNET	RR	1	R48C72[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s33/I1
5.765	0.098	tINS	RR	1	R48C72[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s33/O
5.765	0.000	tNET	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s24/I1
5.827	0.062	tINS	RR	1	R48C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s24/O
6.505	0.678	tNET	RR	1	R45C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s27/I0
6.694	0.189	tINS	RR	2	R45C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3746_s27/F
7.121	0.427	tNET	RR	1	R43C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R43C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s0/CLK
7.874	-0.046	tSu		1	R43C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.242, 22.176%; route: 4.083, 72.907%; tC2Q: 0.275, 4.917%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path53

Path Summary:

Slack	0.757
Data Arrival Time	6.992
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.407	1.619	tNET	RR	1	R58C73[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/I2
3.706	0.299	tINS	RR	1	R58C73[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_17_s8/F
3.710	0.004	tNET	RR	1	R58C73[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/I2
4.068	0.358	tINS	RR	3	R58C73[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3102_s18/F
4.864	0.796	tNET	RR	1	R40C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/I2
5.072	0.209	tINS	RF	1	R40C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s4/F
5.175	0.103	tNET	FF	1	R41C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/I1
5.364	0.189	tINS	FR	1	R41C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s2/F
5.821	0.457	tNET	RR	1	R49C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/I0
6.200	0.379	tINS	RR	2	R49C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5561_s1/F
6.992	0.792	tNET	RR	1	R51C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R51C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2/CLK
7.750	-0.164	tSu		1	R51C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_41_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.434, 26.168%; route: 3.770, 68.805%; tC2Q: 0.275, 5.027%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path54

Path Summary:

Slack	0.770
Data Arrival Time	6.926
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.083	0.305	tNET	FF	1	R64C84[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_3_s/I2
2.415	0.332	tINS	FR	6	R64C84[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_3_s/F
4.409	1.993	tNET	RR	1	R18C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s1/I2
4.788	0.379	tINS	RR	15	R18C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s1/F
5.058	0.271	tNET	RR	1	R16C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1767_s0/I2
5.437	0.379	tINS	RR	7	R16C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1767_s0/F
6.926	1.489	tNET	RR	1	R52C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R52C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_1_s0/CLK
7.696	-0.224	tSu		1	R52C86[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/transfer_out_lpf_1_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.090, 20.136%; route: 4.058, 74.975%; tC2Q: 0.265, 4.889%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path55

Path Summary:

Slack	0.780
Data Arrival Time	7.088
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R16C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/CLK
1.778	0.265	tC2Q	RF	137	R16C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_0_s0/Q
3.375	1.597	tNET	FF	1	R2C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s1/I0
3.751	0.375	tINS	FR	12	R2C86[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n1360_s1/F
4.779	1.028	tNET	RR	1	R7C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s85/I2
5.154	0.375	tINS	RR	1	R7C99[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s85/F
5.267	0.113	tNET	RR	1	R8C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s83/I3
5.456	0.189	tINS	RR	1	R8C99[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s83/F
5.861	0.405	tNET	RR	1	R11C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s81/I2
6.193	0.332	tINS	RR	1	R11C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2520_s81/F
7.088	0.895	tNET	RR	1	R13C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R13C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2/CLK
7.867	-0.046	tSu		1	R13C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/training_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.272, 22.812%; route: 4.038, 72.441%; tC2Q: 0.265, 4.747%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path56

Path Summary:

Slack	0.782
Data Arrival Time	6.968
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/CLK
1.782	0.275	tC2Q	RR	7	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/Q
2.354	0.572	tNET	RR	1	R52C67[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s33/I2
2.686	0.332	tINS	RR	2	R52C67[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s33/F
3.036	0.349	tNET	RR	1	R52C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s35/I2
3.415	0.379	tINS	RR	1	R52C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s35/F
3.514	0.099	tNET	RR	1	R52C65[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s32/I0
3.889	0.375	tINS	RR	1	R52C65[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s32/F
4.747	0.859	tNET	RR	1	R51C65[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s27/I3
4.956	0.209	tINS	RF	2	R51C65[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s27/F
5.862	0.905	tNET	FF	1	R48C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s24/I0
6.233	0.372	tINS	FR	1	R48C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s24/F
6.347	0.113	tNET	RR	1	R48C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s22/I1
6.536	0.189	tINS	RR	2	R48C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s22/F
6.968	0.432	tNET	RR	1	R46C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s1/CLK
7.750	-0.164	tSu		1	R46C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.856, 33.982%; route: 3.330, 60.976%; tC2Q: 0.275, 5.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path57

Path Summary:

Slack	0.782
Data Arrival Time	6.968
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/CLK
1.782	0.275	tC2Q	RR	7	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_41_s0/Q
2.354	0.572	tNET	RR	1	R52C67[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s33/I2
2.686	0.332	tINS	RR	2	R52C67[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s33/F
3.036	0.349	tNET	RR	1	R52C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s35/I2
3.415	0.379	tINS	RR	1	R52C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s35/F
3.514	0.099	tNET	RR	1	R52C65[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s32/I0
3.889	0.375	tINS	RR	1	R52C65[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s32/F
4.747	0.859	tNET	RR	1	R51C65[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s27/I3
4.956	0.209	tINS	RF	2	R51C65[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s27/F
5.862	0.905	tNET	FF	1	R48C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s24/I0
6.233	0.372	tINS	FR	1	R48C69[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s24/F
6.347	0.113	tNET	RR	1	R48C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s22/I1
6.536	0.189	tINS	RR	2	R48C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3751_s22/F
6.968	0.432	tNET	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s0/CLK
7.750	-0.164	tSu		1	R46C66[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.856, 33.982%; route: 3.330, 60.976%; tC2Q: 0.275, 5.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path58

Path Summary:

Slack	0.791
Data Arrival Time	6.892
Data Required Time	7.682
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	18	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB
2.961	1.447	tC2Q	RR	7	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]
3.686	0.725	tNET	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/I0
4.065	0.379	tINS	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/F
4.529	0.464	tNET	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/I3
4.887	0.358	tINS	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/F
4.986	0.099	tNET	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/I3
5.319	0.332	tINS	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/F
5.666	0.347	tNET	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/I2
6.045	0.379	tINS	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/F
6.158	0.113	tNET	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/I3
6.457	0.299	tINS	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/F
6.459	0.002	tNET	RR	1	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/I1
6.791	0.332	tINS	RR	4	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/F
6.892	0.101	tNET	RR	1	R50C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R50C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_0_s0/CLK
7.682	-0.224	tSu		1	R50C3[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_0_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.079, 38.655%; route: 1.852, 34.438%; tC2Q: 1.447, 26.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path59

Path Summary:

Slack	0.791
Data Arrival Time	6.892
Data Required Time	7.682
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	18	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB
2.961	1.447	tC2Q	RR	7	BSRAM_R56[2]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DO[4]
3.686	0.725	tNET	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/I0
4.065	0.379	tINS	RR	1	R51C16[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s9/F
4.529	0.464	tNET	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/I3
4.887	0.358	tINS	RR	1	R51C6[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s7/F
4.986	0.099	tNET	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/I3
5.319	0.332	tINS	RR	1	R51C6[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s10/F
5.666	0.347	tNET	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/I2
6.045	0.379	tINS	RR	1	R50C4[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s4/F
6.158	0.113	tNET	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/I3
6.457	0.299	tINS	RR	1	R50C3[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s3/F
6.459	0.002	tNET	RR	1	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/I1
6.791	0.332	tINS	RR	4	R50C3[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_3_s2/F
6.892	0.101	tNET	RR	1	R50C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R50C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_1_s0/CLK
7.682	-0.224	tSu		1	R50C3[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_descramble/rx_polarity_cnt_1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.079, 38.655%; route: 1.852, 34.438%; tC2Q: 1.447, 26.908%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path60

Path Summary:

Slack	0.801
Data Arrival Time	7.067
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
3.784	2.012	tNET	FF	1	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/I1
4.162	0.379	tINS	FR	10	R4C96[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2523_s84/F
4.616	0.454	tNET	RR	1	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/I3
4.948	0.332	tINS	RR	9	R11C98[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2533_s80/F
5.427	0.479	tNET	RR	1	R3C100[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s81/I2
5.636	0.209	tINS	RF	1	R3C100[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s81/F
5.639	0.004	tNET	FF	1	R3C100[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s73/I0
6.018	0.379	tINS	FR	1	R3C100[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s73/F
6.688	0.670	tNET	RR	1	R9C95[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s70/I3
7.067	0.379	tINS	RR	1	R9C95[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2539_s70/F
7.067	0.000	tNET	RR	1	R9C95[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R9C95[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0/CLK
7.867	-0.046	tSu		1	R9C95[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/tsc_1_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.678, 30.172%; route: 3.618, 65.070%; tC2Q: 0.265, 4.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path61

Path Summary:

Slack	0.837
Data Arrival Time	6.867
Data Required Time	7.704
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.112	2.317	tNET	RR	1	R44C62[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s8/I2
4.411	0.299	tINS	RR	1	R44C62[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s8/F
4.414	0.004	tNET	RR	1	R44C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24962_s4/I2
4.793	0.379	tINS	RR	5	R44C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24962_s4/F
5.350	0.557	tNET	RR	1	R48C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/I0
5.722	0.372	tINS	RR	1	R48C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/F
6.290	0.568	tNET	RR	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s3/I0
6.479	0.189	tINS	RR	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s3/F
6.481	0.002	tNET	RR	1	R43C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I3
6.650	0.169	tINS	RF	2	R43C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F
6.867	0.217	tNET	FF	1	R45C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R45C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2/CLK
7.704	-0.210	tSu		1	R45C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.408, 26.326%; route: 3.664, 68.524%; tC2Q: 0.275, 5.151%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path62

Path Summary:

Slack	0.859
Data Arrival Time	6.884
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.468	1.679	tNET	RR	1	R57C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/I2
3.826	0.358	tINS	RR	1	R57C71[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_20_s8/F
3.927	0.101	tNET	RR	1	R57C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/I2
4.116	0.189	tINS	RR	3	R57C71[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3099_s20/F
4.765	0.649	tNET	RR	1	R40C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/I2
4.973	0.209	tINS	RF	1	R40C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s4/F
4.977	0.004	tNET	FF	1	R40C67[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/I1
5.309	0.332	tINS	FR	1	R40C67[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s2/F
5.668	0.359	tNET	RR	1	R50C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/I0
6.047	0.379	tINS	RR	2	R50C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5558_s1/F
6.884	0.837	tNET	RR	1	R51C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R51C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2/CLK
7.743	-0.164	tSu		1	R51C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_44_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.467, 27.315%; route: 3.628, 67.558%; tC2Q: 0.275, 5.128%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path63

Path Summary:

Slack	0.863
Data Arrival Time	7.004
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[0]_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/I0
5.175	0.400	tINS	RF	3	R24C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1464_s0/COUT
5.786	0.611	tNET	FF	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/I0
6.084	0.299	tINS	FR	1	R17C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s6/F
6.183	0.099	tNET	RR	1	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/I0
6.555	0.372	tINS	RR	6	R17C102[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[0]_4_s7/F
6.672	0.117	tNET	RR	1	R17C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1524_s23/I0
7.004	0.332	tINS	RR	1	R17C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1524_s23/F
7.004	0.000	tNET	RR	1	R17C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[0]_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R17C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[0]_0_s2/CLK
7.867	-0.046	tSu		1	R17C103[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[0]_0_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.735, 31.601%; route: 3.491, 63.580%; tC2Q: 0.265, 4.819%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path64

Path Summary:

Slack	0.866
Data Arrival Time	6.995
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/I2
4.146	0.189	tINS	RR	2	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/F
4.249	0.103	tNET	RR	1	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/I2
4.548	0.299	tINS	RR	4	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/F
5.054	0.506	tNET	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s37/I1
5.432	0.379	tINS	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s37/F
5.432	0.000	tNET	RR	1	R50C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s33/I1
5.531	0.098	tINS	RR	1	R50C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s33/O
5.531	0.000	tNET	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s24/I1
5.593	0.062	tINS	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s24/O
6.175	0.582	tNET	RR	1	R45C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s27/I0
6.554	0.379	tINS	RR	2	R45C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s27/F
6.995	0.441	tNET	RR	1	R44C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R44C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s0/CLK
7.861	-0.046	tSu		1	R44C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.406, 25.678%; route: 3.793, 69.291%; tC2Q: 0.275, 5.030%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path65

Path Summary:

Slack	0.872
Data Arrival Time	6.817
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_0_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/I0
5.175	0.400	tINS	RF	4	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/COUT
5.647	0.472	tNET	FF	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/I0
6.005	0.358	tINS	FR	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/F
6.007	0.002	tNET	RR	1	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/I2
6.365	0.358	tINS	RR	6	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/F
6.817	0.452	tNET	RR	1	R21C101[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_0_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R21C101[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_0_s4/CLK
7.689	-0.224	tSu		1	R21C101[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_0_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.449, 27.321%; route: 3.590, 67.690%; tC2Q: 0.265, 4.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path66

Path Summary:

Slack	0.872
Data Arrival Time	6.817
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_1_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/I0
5.175	0.400	tINS	RF	4	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/COUT
5.647	0.472	tNET	FF	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/I0
6.005	0.358	tINS	FR	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/F
6.007	0.002	tNET	RR	1	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/I2
6.365	0.358	tINS	RR	6	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/F
6.817	0.452	tNET	RR	1	R21C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_1_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R21C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_1_s4/CLK
7.689	-0.224	tSu		1	R21C101[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_1_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.449, 27.321%; route: 3.590, 67.690%; tC2Q: 0.265, 4.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path67

Path Summary:

Slack	0.872
Data Arrival Time	6.817
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_2_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/I0
5.175	0.400	tINS	RF	4	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/COUT
5.647	0.472	tNET	FF	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/I0
6.005	0.358	tINS	FR	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/F
6.007	0.002	tNET	RR	1	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/I2
6.365	0.358	tINS	RR	6	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/F
6.817	0.452	tNET	RR	1	R21C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_2_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R21C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_2_s4/CLK
7.689	-0.224	tSu		1	R21C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_2_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.449, 27.321%; route: 3.590, 67.690%; tC2Q: 0.265, 4.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path68

Path Summary:

Slack	0.877
Data Arrival Time	6.826
Data Required Time	7.704
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.114	2.318	tNET	RR	1	R43C64[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s8/I2
4.303	0.189	tINS	RR	2	R43C64[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s8/F
4.308	0.005	tNET	RR	1	R43C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24973_s2/I2
4.687	0.379	tINS	RR	3	R43C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24973_s2/F
5.244	0.557	tNET	RR	1	R49C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s33/I3
5.576	0.332	tINS	RR	1	R49C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s33/F
5.578	0.002	tNET	RR	1	R49C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s27/I1
5.910	0.332	tINS	RR	1	R49C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s27/F
6.009	0.099	tNET	RR	1	R49C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s23/I1
6.308	0.299	tINS	RR	1	R49C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s23/F
6.310	0.002	tNET	RR	1	R49C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s42/I0
6.585	0.275	tINS	RF	2	R49C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s42/F
6.826	0.241	tNET	FF	1	R48C66[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R48C66[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s1/CLK
7.704	-0.210	tSu		1	R48C66[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.806, 34.040%; route: 3.225, 60.770%; tC2Q: 0.275, 5.190%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path69

Path Summary:

Slack	0.877
Data Arrival Time	6.826
Data Required Time	7.704
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.114	2.318	tNET	RR	1	R43C64[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s8/I2
4.303	0.189	tINS	RR	2	R43C64[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s8/F
4.308	0.005	tNET	RR	1	R43C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24973_s2/I2
4.687	0.379	tINS	RR	3	R43C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24973_s2/F
5.244	0.557	tNET	RR	1	R49C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s33/I3
5.576	0.332	tINS	RR	1	R49C68[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s33/F
5.578	0.002	tNET	RR	1	R49C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s27/I1
5.910	0.332	tINS	RR	1	R49C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s27/F
6.009	0.099	tNET	RR	1	R49C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s23/I1
6.308	0.299	tINS	RR	1	R49C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s23/F
6.310	0.002	tNET	RR	1	R49C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s42/I0
6.585	0.275	tINS	RF	2	R49C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3762_s42/F
6.826	0.241	tNET	FF	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s0/CLK
7.704	-0.210	tSu		1	R48C66[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.806, 34.040%; route: 3.225, 60.770%; tC2Q: 0.275, 5.190%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path70

Path Summary:

Slack	0.880
Data Arrival Time	6.981
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_3_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/I2
6.256	0.358	tINS	FR	3	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/F
6.649	0.392	tNET	RR	1	R16C108[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s23/I1
6.981	0.332	tINS	RR	1	R16C108[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s23/F
6.981	0.000	tNET	RR	1	R16C108[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_3_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R16C108[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_3_s4/CLK
7.861	-0.046	tSu		1	R16C108[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/out_state[2]_3_s4

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.423, 26.025%; route: 3.780, 69.136%; tC2Q: 0.265, 4.840%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path71

Path Summary:

Slack	0.883
Data Arrival Time	6.978
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.559	0.547	tNET	RR	1	R42C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/I0
5.748	0.189	tINS	RR	1	R42C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/F
6.179	0.430	tNET	RR	1	R53C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/I0
6.537	0.358	tINS	RR	2	R53C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/F
6.978	0.441	tNET	RR	1	R54C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R54C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2/CLK
7.861	-0.046	tSu		1	R54C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s2

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.298, 23.780%; route: 3.884, 71.174%; tC2Q: 0.275, 5.046%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path72

Path Summary:

Slack	0.883
Data Arrival Time	6.978
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.256	2.461	tNET	RR	1	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/I2
4.628	0.372	tINS	RR	2	R43C63[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_6_s8/F
4.633	0.005	tNET	RR	1	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/I2
5.012	0.379	tINS	RR	4	R43C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24968_s3/F
5.559	0.547	tNET	RR	1	R42C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/I0
5.748	0.189	tINS	RR	1	R42C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s2/F
6.179	0.430	tNET	RR	1	R53C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/I0
6.537	0.358	tINS	RR	2	R53C68[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5540_s1/F
6.978	0.441	tNET	RR	1	R54C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R54C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1/CLK
7.861	-0.046	tSu		1	R54C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_62_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.298, 23.780%; route: 3.884, 71.174%; tC2Q: 0.275, 5.046%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path73

Path Summary:

Slack	0.884
Data Arrival Time	6.984
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_18_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_2_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R50C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_18_s0/CLK
1.789	0.275	tC2Q	RR	7	R50C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_18_s0/Q
2.404	0.616	tNET	RR	1	R50C67[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3750_s47/I3
2.613	0.209	tINS	RF	2	R50C67[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3750_s47/F
3.188	0.575	tNET	FF	1	R53C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s36/I1
3.560	0.372	tINS	FR	1	R53C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s36/F
3.810	0.250	tNET	RR	1	R52C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s31/I0
4.168	0.358	tINS	RR	2	R52C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3759_s31/F
4.919	0.751	tNET	RR	1	R51C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s31/I1
5.218	0.299	tINS	RR	2	R51C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s31/F
6.120	0.902	tNET	RR	1	R49C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s30/I0
6.491	0.372	tINS	RR	1	R49C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s30/F
6.605	0.113	tNET	RR	1	R48C60[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s27/I2
6.984	0.379	tINS	RR	1	R48C60[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3761_s27/F
6.984	0.000	tNET	RR	1	R48C60[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R48C60[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_2_s1/CLK
7.867	-0.046	tSu		1	R48C60[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.988, 36.344%; route: 3.207, 58.621%; tC2Q: 0.275, 5.035%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path74

Path Summary:

Slack	0.886
Data Arrival Time	6.975
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_15_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_10_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R52C64[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_15_s0/CLK
1.789	0.275	tC2Q	RR	6	R52C64[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_15_s0/Q
2.068	0.279	tNET	RR	1	R51C62[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s43/I2
2.439	0.372	tINS	RR	3	R51C62[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3748_s43/F
3.629	1.190	tNET	RR	1	R51C64[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s35/I1
4.008	0.379	tINS	RR	2	R51C64[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s35/F
4.357	0.349	tNET	RR	1	R52C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s40/I3
4.546	0.189	tINS	RR	1	R52C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s40/F
4.685	0.139	tNET	RR	1	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s33/I3
5.017	0.332	tINS	RR	2	R52C63[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s33/F
6.111	1.093	tNET	RR	1	R49C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s31/I2
6.482	0.372	tINS	RR	1	R49C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s31/F
6.596	0.113	tNET	RR	1	R48C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s27/I3
6.975	0.379	tINS	RR	1	R48C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3753_s27/F
6.975	0.000	tNET	RR	1	R48C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R48C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_10_s1/CLK
7.861	-0.046	tSu		1	R48C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_10_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.022, 37.030%; route: 3.163, 57.927%; tC2Q: 0.275, 5.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path75

Path Summary:

Slack	0.890
Data Arrival Time	6.984
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.401	1.612	tNET	RR	1	R57C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.733	0.332	tINS	RR	1	R57C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
3.834	0.101	tNET	RR	1	R57C72[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.212	0.379	tINS	RR	3	R57C72[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
4.861	0.649	tNET	RR	1	R41C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/I2
5.193	0.332	tINS	RR	1	R41C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/F
5.444	0.250	tNET	RR	1	R42C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/I1
5.776	0.332	tINS	RR	1	R42C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/F
6.245	0.469	tNET	RR	1	R53C66[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/I0
6.543	0.299	tINS	RR	2	R53C66[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/F
6.984	0.441	tNET	RR	1	R54C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R54C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2/CLK
7.874	-0.046	tSu		1	R54C65[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s2

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.674, 30.597%; route: 3.522, 64.369%; tC2Q: 0.275, 5.034%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path76

Path Summary:

Slack	0.890
Data Arrival Time	6.984
Data Required Time	7.874
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.401	1.612	tNET	RR	1	R57C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/I2
3.733	0.332	tINS	RR	1	R57C72[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_3_s8/F
3.834	0.101	tNET	RR	1	R57C72[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/I2
4.212	0.379	tINS	RR	3	R57C72[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3116_s17/F
4.861	0.649	tNET	RR	1	R41C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/I2
5.193	0.332	tINS	RR	1	R41C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s4/F
5.444	0.250	tNET	RR	1	R42C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/I1
5.776	0.332	tINS	RR	1	R42C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s2/F
6.245	0.469	tNET	RR	1	R53C66[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/I0
6.543	0.299	tINS	RR	2	R53C66[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5543_s1/F
6.984	0.441	tNET	RR	1	R54C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R54C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1/CLK
7.874	-0.046	tSu		1	R54C65[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_59_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.674, 30.597%; route: 3.522, 64.369%; tC2Q: 0.275, 5.034%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path77

Path Summary:

Slack	0.892
Data Arrival Time	6.975
Data Required Time	7.867
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[5]_12_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/CLK
1.789	0.275	tC2Q	RR	5	R43C77[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/aligned_dpp_data_d0[0]_17_s0/Q
3.085	1.296	tNET	RR	1	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/I2
3.464	0.379	tINS	RR	3	R44C76[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_1_s15/F
3.717	0.254	tNET	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/I3
4.093	0.375	tINS	RR	1	R43C75[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s7/F
4.343	0.250	tNET	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/I2
4.722	0.379	tINS	RR	1	R44C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s2/F
5.573	0.851	tNET	RR	1	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/I0
5.949	0.375	tINS	RR	9	R44C81[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/iu3cdprx64/crcOut_12_s1/F
6.975	1.027	tNET	RR	1	R46C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[5]_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[5]_12_s0/CLK
7.867	-0.046	tSu		1	R46C97[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/crc64_in[5]_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.508, 27.616%; route: 3.678, 67.342%; tC2Q: 0.275, 5.042%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path78

Path Summary:

Slack	0.901
Data Arrival Time	7.330
Data Required Time	8.231
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R11C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/CLK
1.789	0.275	tC2Q	RR	63	R11C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_4_s1/Q
2.188	0.400	tNET	RR	1	R13C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/I2
2.564	0.375	tINS	RR	3	R13C83[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_5g/n1753_s33/F
3.015	0.452	tNET	RR	1	R15C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/I0
3.387	0.372	tINS	RR	13	R15C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/train_sym_skp_6_s12/F
5.395	2.008	tNET	RR	1	R32C47[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/I0
5.767	0.372	tINS	RR	3	R32C47[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3690_s43/F
6.006	0.239	tNET	RR	1	R32C48[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s52/I1
6.381	0.375	tINS	RR	1	R32C48[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s52/F
6.520	0.139	tNET	RR	1	R32C49[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/I1
6.852	0.332	tINS	RR	1	R32C49[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s48/F
6.951	0.099	tNET	RR	1	R32C49[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/I3
7.330	0.379	tINS	RR	1	R32C49[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/n3700_s44/F
7.330	0.000	tNET	RR	1	R32C49[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
8.276	1.876	tNET	RR	1	R32C49[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0/CLK
8.231	-0.046	tSu		1	R32C49[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3p/iu3p_10g/state_0_s0

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.205, 37.908%; route: 3.336, 57.357%; tC2Q: 0.275, 4.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.876, 100.000%

Path79

Path Summary:

Slack	0.905
Data Arrival Time	6.791
Data Required Time	7.696
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/CLK
1.782	0.275	tC2Q	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q
2.076	0.294	tNET	RR	1	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/I0
2.452	0.375	tINS	RR	18	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/F
4.262	1.811	tNET	RR	1	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/I0
4.638	0.375	tINS	RR	13	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/F
4.931	0.293	tNET	RR	1	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/I2
5.140	0.209	tINS	RF	2	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/F
5.147	0.007	tNET	FF	1	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/I2
5.505	0.358	tINS	FR	13	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/F
5.764	0.259	tNET	RR	1	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/I0
6.136	0.372	tINS	RR	4	R16C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1520_s32/F
6.255	0.119	tNET	RR	1	R16C103[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s4/I0
6.444	0.189	tINS	RR	1	R16C103[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s4/F
6.791	0.347	tNET	RR	1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/CLK
7.696	-0.224	tSu		1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.878, 35.542%; route: 3.131, 59.247%; tC2Q: 0.275, 5.211%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path80

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_0_s0/CLK
7.645	-0.268	tSu		1	R3C85[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_0_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path81

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_1_s0/CLK
7.645	-0.268	tSu		1	R3C85[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_1_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path82

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_2_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_2_s0/CLK
7.645	-0.268	tSu		1	R3C85[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_2_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path83

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_3_s0/CLK
7.645	-0.268	tSu		1	R3C85[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_3_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path84

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_4_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_4_s0/CLK
7.645	-0.268	tSu		1	R3C85[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_4_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path85

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_5_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_5_s0/CLK
7.645	-0.268	tSu		1	R3C85[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_5_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path86

Path Summary:

Slack	0.907
Data Arrival Time	6.738
Data Required Time	7.645
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_6_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
4.397	2.626	tNET	FF	1	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/I1
4.586	0.189	tINS	FR	3	R7C103[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n2609_s79/F
5.054	0.468	tNET	RR	1	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/I0
5.426	0.372	tINS	RR	2	R8C93[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s3/F
5.842	0.416	tNET	RR	1	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/I1
6.141	0.299	tINS	RR	26	R7C90[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/n10256_s1/F
6.738	0.598	tNET	RR	1	R3C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R3C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_6_s0/CLK
7.645	-0.268	tSu		1	R3C85[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rc_6_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.859, 16.429%; route: 4.108, 78.514%; tC2Q: 0.265, 5.058%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path87

Path Summary:

Slack	0.908
Data Arrival Time	6.802
Data Required Time	7.710
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/CLK
1.782	0.275	tC2Q	RR	1	R66C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_endp_d[10]_0_s0/Q
2.076	0.294	tNET	RR	1	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/I0
2.452	0.375	tINS	RR	18	R64C84[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_endp_d_0_s/F
4.262	1.811	tNET	RR	1	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/I0
4.638	0.375	tINS	RR	13	R17C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2166_s1/F
4.931	0.293	tNET	RR	1	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/I2
5.140	0.209	tINS	RF	2	R15C103[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s2/F
5.147	0.007	tNET	FF	1	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/I2
5.505	0.358	tINS	FR	13	R15C103[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/prot_buf_in_ready_s/F
5.901	0.396	tNET	RR	1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1919_s26/I0
6.090	0.189	tINS	RR	2	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1919_s26/F
6.094	0.004	tNET	RR	1	R18C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1905_s12/I1
6.303	0.209	tINS	RF	1	R18C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1905_s12/F
6.802	0.500	tNET	FF	1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.920	1.520	tNET	RR	1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2/CLK
7.710	-0.210	tSu		1	R18C102[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_rdy_mask_1_s2

Path Statistics:

Clock Skew	0.014
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 1.715, 32.393%; route: 3.305, 62.407%; tC2Q: 0.275, 5.201%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%

Path88

Path Summary:

Slack	0.909
Data Arrival Time	6.952
Data Required Time	7.861
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/valid_bits_3_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/Empty_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R43C18[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/valid_bits_3_s0/CLK
1.778	0.265	tC2Q	RF	89	R43C18[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/valid_bits_3_s0/Q
2.386	0.608	tNET	FF	1	R45C19[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/tx_ready_s1/I2
2.718	0.332	tINS	FR	6	R45C19[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/tx_ready_s1/F
3.003	0.284	tNET	RR	1	R46C20[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/tx_ready_s/I0
3.302	0.299	tINS	RR	85	R46C20[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/tx_ready_s/F
3.900	0.599	tNET	RR	1	R45C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rbinnext_1_s5/I3
4.258	0.358	tINS	RR	8	R45C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rbinnext_1_s5/F
4.658	0.400	tNET	RR	1	R46C24[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rbinnext_1_s3/I1
5.030	0.372	tINS	RR	3	R46C24[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rbinnext_1_s3/F
5.147	0.117	tNET	RR	1	R46C25[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rgraynext_1_s1/I0
5.336	0.189	tINS	RR	2	R46C25[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rgraynext_1_s1/F
5.783	0.447	tNET	RR	2	R48C26[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n208_s0/I0
6.183	0.400	tINS	RF	1	R48C26[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n208_s0/COUT
6.183	0.000	tNET	FF	2	R48C26[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n209_s0/CIN
6.219	0.036	tINS	FR	1	R48C26[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n209_s0/COUT
6.219	0.000	tNET	RR	2	R48C26[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n210_s0/CIN
6.255	0.036	tINS	RR	1	R48C26[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n210_s0/COUT
6.255	0.000	tNET	RR	2	R48C26[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n211_s0/CIN
6.291	0.036	tINS	RR	1	R48C26[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/n211_s0/COUT
6.580	0.289	tNET	RR	1	R48C27[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rempty_val_s1/I0
6.952	0.372	tINS	RR	1	R48C27[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/rempty_val_s1/F
6.952	0.000	tNET	RR	1	R48C27[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/Empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R48C27[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/Empty_s0/CLK
7.861	-0.046	tSu		1	R48C27[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/Empty_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 2.430, 44.680%; route: 2.744, 50.455%; tC2Q: 0.265, 4.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path89

Path Summary:

Slack	0.916
Data Arrival Time	6.773
Data Required Time	7.689
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_3_s4
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.774	1.568	tNET	RR	2	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/I0
5.175	0.400	tINS	RF	4	R23C101[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n1863_s0/COUT
5.647	0.472	tNET	FF	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/I0
6.005	0.358	tINS	FR	1	R16C101[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s6/F
6.007	0.002	tNET	RR	1	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/I2
6.365	0.358	tINS	RR	6	R16C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_4_s5/F
6.773	0.408	tNET	RR	1	R23C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_3_s4/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R23C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_3_s4/CLK
7.689	-0.224	tSu		1	R23C101[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_ack_current_seq[1]_3_s4

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.449, 27.550%; route: 3.546, 67.420%; tC2Q: 0.265, 5.031%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path90

Path Summary:

Slack	0.937
Data Arrival Time	6.806
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/CLK
1.795	0.275	tC2Q	RR	7	R51C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/Q
2.391	0.596	tNET	RR	1	R51C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s42/I3
2.770	0.379	tINS	RR	2	R51C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s42/F
2.911	0.140	tNET	RR	1	R51C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s39/I3
3.243	0.332	tINS	RR	2	R51C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s39/F
4.017	0.774	tNET	RR	1	R52C64[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s34/I3
4.375	0.358	tINS	RR	1	R52C64[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s34/F
4.377	0.002	tNET	RR	1	R52C64[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s27/I0
4.735	0.358	tINS	RR	1	R52C64[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s27/F
5.552	0.817	tNET	RR	1	R50C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s23/I2
5.884	0.332	tINS	RR	1	R50C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s23/F
6.134	0.250	tNET	RR	1	R48C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s22/I0
6.510	0.375	tINS	RR	2	R48C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s22/F
6.806	0.296	tNET	RR	1	R46C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s1/CLK
7.743	-0.164	tSu		1	R46C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.135, 40.388%; route: 2.876, 54.402%; tC2Q: 0.275, 5.210%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path91

Path Summary:

Slack	0.937
Data Arrival Time	6.806
Data Required Time	7.743
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/CLK
1.795	0.275	tC2Q	RR	7	R51C65[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_header_pkt_81_s0/Q
2.391	0.596	tNET	RR	1	R51C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s42/I3
2.770	0.379	tINS	RR	2	R51C60[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s42/F
2.911	0.140	tNET	RR	1	R51C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s39/I3
3.243	0.332	tINS	RR	2	R51C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3755_s39/F
4.017	0.774	tNET	RR	1	R52C64[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s34/I3
4.375	0.358	tINS	RR	1	R52C64[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s34/F
4.377	0.002	tNET	RR	1	R52C64[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s27/I0
4.735	0.358	tINS	RR	1	R52C64[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s27/F
5.552	0.817	tNET	RR	1	R50C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s23/I2
5.884	0.332	tINS	RR	1	R50C64[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s23/F
6.134	0.250	tNET	RR	1	R48C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s22/I0
6.510	0.375	tINS	RR	2	R48C63[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3752_s22/F
6.806	0.296	tNET	RR	1	R46C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s0/CLK
7.743	-0.164	tSu		1	R46C63[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_11_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 2.135, 40.388%; route: 2.876, 54.402%; tC2Q: 0.275, 5.210%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path92

Path Summary:

Slack	0.944
Data Arrival Time	6.806
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/I2
4.146	0.189	tINS	RR	2	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/F
4.249	0.103	tNET	RR	1	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/I2
4.548	0.299	tINS	RR	4	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/F
5.054	0.506	tNET	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s37/I1
5.432	0.379	tINS	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s37/F
5.432	0.000	tNET	RR	1	R50C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s33/I1
5.531	0.098	tINS	RR	1	R50C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s33/O
5.531	0.000	tNET	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s24/I1
5.593	0.062	tINS	RR	1	R50C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s24/O
6.175	0.582	tNET	RR	1	R45C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s27/I0
6.554	0.379	tINS	RR	2	R45C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s27/F
6.806	0.252	tNET	RR	1	R44C68[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R44C68[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s1/CLK
7.750	-0.164	tSu		1	R44C68[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.406, 26.596%; route: 3.605, 68.193%; tC2Q: 0.275, 5.210%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path93

Path Summary:

Slack	0.946
Data Arrival Time	6.915
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.414	1.625	tNET	RR	1	R57C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/I2
3.746	0.332	tINS	RR	1	R57C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/F
3.887	0.140	tNET	RR	1	R57C71[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/I2
4.262	0.375	tINS	RR	3	R57C71[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/F
5.008	0.746	tNET	RR	1	R40C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/I2
5.380	0.372	tINS	RR	1	R40C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/F
5.655	0.275	tNET	RR	1	R44C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/I1
5.987	0.332	tINS	RR	1	R44C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/F
6.267	0.280	tNET	RR	1	R53C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/I0
6.625	0.358	tINS	RR	2	R53C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/F
6.915	0.290	tNET	RR	1	R53C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R53C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2/CLK
7.861	-0.046	tSu		1	R53C67[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.769, 32.756%; route: 3.357, 62.146%; tC2Q: 0.275, 5.098%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path94

Path Summary:

Slack	0.946
Data Arrival Time	6.915
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.414	1.625	tNET	RR	1	R57C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/I2
3.746	0.332	tINS	RR	1	R57C70[1][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_19_s8/F
3.887	0.140	tNET	RR	1	R57C71[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/I2
4.262	0.375	tINS	RR	3	R57C71[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3100_s18/F
5.008	0.746	tNET	RR	1	R40C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/I2
5.380	0.372	tINS	RR	1	R40C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s4/F
5.655	0.275	tNET	RR	1	R44C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/I1
5.987	0.332	tINS	RR	1	R44C67[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s2/F
6.267	0.280	tNET	RR	1	R53C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/I0
6.625	0.358	tINS	RR	2	R53C67[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5559_s1/F
6.915	0.290	tNET	RR	1	R53C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R53C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1/CLK
7.861	-0.046	tSu		1	R53C67[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_43_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.769, 32.756%; route: 3.357, 62.146%; tC2Q: 0.275, 5.098%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path95

Path Summary:

Slack	0.955
Data Arrival Time	6.906
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_link_busy_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/CLK
1.795	0.275	tC2Q	RR	207	R22C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/rate_d1_s0/Q
4.428	2.632	tNET	RR	1	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/I0
4.807	0.379	tINS	RR	5	R30C60[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/n438_s0/F
6.079	1.273	tNET	RR	1	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/I0
6.412	0.332	tINS	RR	2	R64C76[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_lcmd_req_ack_s5/F
6.527	0.115	tNET	RR	1	R63C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5079_s0/I1
6.906	0.379	tINS	RR	1	R63C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5079_s0/F
6.906	0.000	tNET	RR	1	R63C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_link_busy_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R63C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_link_busy_s0/CLK
7.861	-0.046	tSu		1	R63C76[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/tx_link_busy_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.090, 20.237%; route: 4.020, 74.649%; tC2Q: 0.275, 5.114%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path96

Path Summary:

Slack	0.955
Data Arrival Time	6.794
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_51_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/CLK
1.789	0.275	tC2Q	RR	2624	R60C75[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0_s0/Q
3.407	1.619	tNET	RR	1	R61C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/I2
3.706	0.299	tINS	RR	1	R61C76[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_lcmd_11_s8/F
3.807	0.101	tNET	RR	1	R61C76[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/I2
4.139	0.332	tINS	RR	3	R61C76[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3108_s19/F
5.230	1.091	tNET	RR	1	R40C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s4/I2
5.439	0.209	tINS	RF	1	R40C68[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s4/F
5.707	0.268	tNET	FF	1	R44C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s2/I1
6.039	0.332	tINS	FR	1	R44C68[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s2/F
6.041	0.002	tNET	RR	1	R44C68[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s1/I0
6.420	0.379	tINS	RR	2	R44C68[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5551_s1/F
6.794	0.374	tNET	RR	1	R46C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_51_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_51_s2/CLK
7.750	-0.164	tSu		1	R46C66[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_51_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.551, 29.365%; route: 3.455, 65.420%; tC2Q: 0.275, 5.215%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path97

Path Summary:

Slack	0.965
Data Arrival Time	6.895
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.513	1.513	tNET	RR	1	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/CLK
1.778	0.265	tC2Q	RF	49	R62C83[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/speed_13_s0/Q
2.874	1.096	tNET	FF	1	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/I2
3.206	0.332	tINS	FR	6	R66C83[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/prot_rx_dph_seq_d_4_s/F
4.884	1.678	tNET	RR	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/I0
5.284	0.400	tINS	RF	2	R24C102[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2262_s0/COUT
5.898	0.614	tNET	FF	1	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/I2
6.256	0.358	tINS	FR	3	R16C102[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2316_s26/F
6.706	0.450	tNET	RR	1	R13C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2312_s9/I1
6.895	0.189	tINS	RR	1	R13C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n2312_s9/F
6.895	0.000	tNET	RR	1	R13C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R13C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_0_s2/CLK
7.861	-0.046	tSu		1	R13C104[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/ep_out_wt_cnt[2]_0_s2

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%
Arrival Data Path Delay	cell: 1.280, 23.779%; route: 3.838, 71.304%; tC2Q: 0.265, 4.916%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path98

Path Summary:

Slack	0.966
Data Arrival Time	6.895
Data Required Time	7.861
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/warm_or_hot_reset_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.507	1.507	tNET	RR	1	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/CLK
1.771	0.265	tC2Q	RF	128	R16C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3lt/state_1_s0/Q
5.235	3.464	tNET	FF	1	R27C105[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n244_s1/I3
5.567	0.332	tINS	FR	1	R27C105[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n244_s1/F
5.666	0.099	tNET	RR	1	R27C105[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n244_s0/I0
6.045	0.379	tINS	RR	1	R27C105[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n244_s0/F
6.895	0.850	tNET	RR	1	R22C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/warm_or_hot_reset_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R22C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/warm_or_hot_reset_s0/CLK
7.861	-0.046	tSu		1	R22C100[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/warm_or_hot_reset_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.400
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%
Arrival Data Path Delay	cell: 0.711, 13.195%; route: 4.413, 81.894%; tC2Q: 0.265, 4.911%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path99

Path Summary:

Slack	0.969
Data Arrival Time	6.735
Data Required Time	7.704
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
4.112	2.317	tNET	RR	1	R44C62[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s8/I2
4.411	0.299	tINS	RR	1	R44C62[3][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_12_s8/F
4.414	0.004	tNET	RR	1	R44C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24962_s4/I2
4.793	0.379	tINS	RR	5	R44C62[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n24962_s4/F
5.350	0.557	tNET	RR	1	R48C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/I0
5.722	0.372	tINS	RR	1	R48C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s5/F
6.290	0.568	tNET	RR	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s3/I0
6.479	0.189	tINS	RR	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s3/F
6.481	0.002	tNET	RR	1	R43C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/I3
6.650	0.169	tINS	RF	2	R43C70[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5582_s0/F
6.735	0.085	tNET	FF	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1/CLK
7.704	-0.210	tSu		1	R43C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_20_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.408, 26.993%; route: 3.532, 67.725%; tC2Q: 0.275, 5.281%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path100

Path Summary:

Slack	0.970
Data Arrival Time	6.780
Data Required Time	7.750
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/CLK
1.795	0.275	tC2Q	RR	159	R49C69[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/reset_n_d_s0/Q
3.957	2.162	tNET	RR	1	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/I2
4.146	0.189	tINS	RR	2	R43C66[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/out_data_hp_19_s8/F
4.249	0.103	tNET	RR	1	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/I2
4.548	0.299	tINS	RR	4	R43C66[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n3744_s28/F
5.162	0.615	tNET	RR	1	R48C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s6/I0
5.541	0.379	tINS	RR	1	R48C70[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s6/F
5.875	0.334	tNET	RR	1	R45C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s3/I1
6.064	0.189	tINS	RR	1	R45C70[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s3/F
6.163	0.099	tNET	RR	1	R45C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/I3
6.542	0.379	tINS	RR	2	R45C70[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/n5591_s0/F
6.780	0.238	tNET	RR	1	R46C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1/CLK
7.750	-0.164	tSu		1	R46C70[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/outp_data_11_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 1.435, 27.276%; route: 3.550, 67.488%; tC2Q: 0.275, 5.236%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.041
Data Arrival Time	0.860
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_45_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R44C27[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_45_s0/CLK
0.734	0.130	tC2Q	RR	1	R44C27[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_45_s0/Q
0.860	0.126	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 49.296%; tC2Q: 0.130, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path2

Path Summary:

Slack	0.043
Data Arrival Time	0.859
Data Required Time	0.815
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_55_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C59[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_55_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C59[3][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_55_s0/Q
0.859	0.124	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path3

Path Summary:

Slack	0.043
Data Arrival Time	0.859
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_58_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R39C23[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_58_s0/CLK
0.734	0.130	tC2Q	RR	1	R39C23[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_58_s0/Q
0.859	0.124	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path4

Path Summary:

Slack	0.043
Data Arrival Time	0.859
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_50_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R39C23[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_50_s0/CLK
0.734	0.130	tC2Q	RR	1	R39C23[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_50_s0/Q
0.859	0.124	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path5

Path Summary:

Slack	0.043
Data Arrival Time	0.862
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_40_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R39C26[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_40_s0/CLK
0.738	0.130	tC2Q	RR	1	R39C26[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_40_s0/Q
0.862	0.124	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path6

Path Summary:

Slack	0.047
Data Arrival Time	0.862
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_59_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R39C24[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_59_s0/CLK
0.738	0.130	tC2Q	RR	1	R39C24[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_59_s0/Q
0.862	0.124	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path7

Path Summary:

Slack	0.052
Data Arrival Time	0.868
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_62_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.612	0.612	tNET	RR	1	R42C25[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_62_s0/CLK
0.742	0.130	tC2Q	RR	1	R42C25[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_62_s0/Q
0.868	0.126	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.170
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.612, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 49.296%; tC2Q: 0.130, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path8

Path Summary:

Slack	0.058
Data Arrival Time	0.877
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_42_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.612	0.612	tNET	RR	1	R42C29[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_42_s0/CLK
0.742	0.130	tC2Q	RR	1	R42C29[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_42_s0/Q
0.877	0.135	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.612, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 51.020%; tC2Q: 0.130, 48.980%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path9

Path Summary:

Slack	0.082
Data Arrival Time	0.732
Data Required Time	0.650
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R67C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/CLK
0.732	0.127	tC2Q	RF	1	R67C84[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[5]_8_s0/Q
0.732	0.000	tNET	FF	1	R68C84	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R68C84	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9/CLK
0.650	0.045	tHld		1	R68C84	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/rx_dph_len_d[6]_0_s9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.127, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%

Path10

Path Summary:

Slack	0.095
Data Arrival Time	0.913
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_2_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R50C26[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_2_s0/CLK
0.738	0.130	tC2Q	RR	7	R50C26[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_2_s0/Q
0.913	0.175	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/ADA[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 57.522%; tC2Q: 0.130, 42.478%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path11

Path Summary:

Slack	0.098
Data Arrival Time	0.917
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_43_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R45C27[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_43_s0/CLK
0.734	0.130	tC2Q	RR	1	R45C27[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_43_s0/Q
0.917	0.183	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path12

Path Summary:

Slack	0.102
Data Arrival Time	0.921
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_0_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.612	0.612	tNET	RR	1	R50C25[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_0_s0/CLK
0.742	0.130	tC2Q	RR	10	R50C25[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/wbin_0_s0/Q
0.921	0.179	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.174
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.612, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 58.017%; tC2Q: 0.130, 41.983%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path13

Path Summary:

Slack	0.107
Data Arrival Time	0.926
Data Required Time	0.819
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_26_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C63[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_26_s1/CLK
0.734	0.130	tC2Q	RR	1	R40C63[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_26_s1/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path14

Path Summary:

Slack	0.107
Data Arrival Time	0.926
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_48_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C27[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_48_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C27[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_48_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path15

Path Summary:

Slack	0.107
Data Arrival Time	0.926
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_46_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C27[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_46_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C27[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_46_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path16

Path Summary:

Slack	0.109
Data Arrival Time	0.928
Data Required Time	0.819
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_32_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R42C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_32_s0/CLK
0.734	0.130	tC2Q	RR	1	R42C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_32_s0/Q
0.928	0.193	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[4][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.193, 59.889%; tC2Q: 0.130, 40.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path17

Path Summary:

Slack	0.111
Data Arrival Time	0.926
Data Required Time	0.815
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_53_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C59[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_53_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C59[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_53_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path18

Path Summary:

Slack	0.111
Data Arrival Time	0.926
Data Required Time	0.815
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_50_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C59[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_50_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C59[0][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_50_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[12][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path19

Path Summary:

Slack	0.111
Data Arrival Time	0.930
Data Required Time	0.819
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_18_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R40C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_18_s1/CLK
0.738	0.130	tC2Q	RR	1	R40C62[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_18_s1/Q
0.930	0.192	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path20

Path Summary:

Slack	0.111
Data Arrival Time	0.930
Data Required Time	0.819
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_16_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.608	0.608	tNET	RR	1	R40C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_16_s1/CLK
0.738	0.130	tC2Q	RR	1	R40C62[2][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_16_s1/Q
0.930	0.192	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.608, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path21

Path Summary:

Slack	0.111
Data Arrival Time	0.926
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_53_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C23[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_53_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C23[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_53_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path22

Path Summary:

Slack	0.111
Data Arrival Time	0.926
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_51_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C23[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_51_s0/CLK
0.734	0.130	tC2Q	RR	1	R40C23[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_51_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path23

Path Summary:

Slack	0.111
Data Arrival Time	0.926
Data Required Time	0.815
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_49_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R39C23[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_49_s0/CLK
0.734	0.130	tC2Q	RR	1	R39C23[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_encode_10g_49_s0/Q
0.926	0.192	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.782	0.782	tNET	RR	1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA
0.815	0.033	tHld		1	BSRAM_R38[4][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_tx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.192, 59.664%; tC2Q: 0.130, 40.336%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.782, 100.000%

Path24

Path Summary:

Slack	0.121
Data Arrival Time	0.940
Data Required Time	0.819
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_31_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R41C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_31_s1/CLK
0.734	0.130	tC2Q	RR	1	R41C63[1][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_31_s1/Q
0.940	0.205	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Path25

Path Summary:

Slack	0.121
Data Arrival Time	0.940
Data Required Time	0.819
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_30_s1
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.605	0.605	tNET	RR	1	R40C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_30_s1/CLK
0.734	0.130	tC2Q	RR	1	R40C63[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/res_mem_wr_dat_30_s1/Q
0.940	0.205	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.786	0.786	tNET	RR	1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s/CLKA
0.819	0.033	tHld		1	BSRAM_R38[12][B]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/gowin_add_SDPB_res_mem_res_mem_0_0_s

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.605, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 61.290%; tC2Q: 0.130, 38.710%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.786, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.668
Data Arrival Time	5.995
Data Required Time	7.663
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/CLK
1.795	0.275	tC2Q	RR	598	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q
4.797	3.001	tNET	RR	1	R46C28[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/I3
5.172	0.375	tINS	RR	3	R46C28[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/F
5.179	0.007	tNET	RR	1	R46C28[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3233_s2/I3
5.460	0.281	tINS	RF	1	R46C28[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3233_s2/F
5.995	0.535	tNET	FF	1	R46C28[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C28[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1/CLK
7.663	-0.250	tSu		1	R46C28[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.656, 14.661%; route: 3.544, 79.186%; tC2Q: 0.275, 6.154%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path2

Path Summary:

Slack	1.686
Data Arrival Time	5.977
Data Required Time	7.663
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/CLK
1.795	0.275	tC2Q	RR	598	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q
4.797	3.001	tNET	RR	1	R46C28[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/I3
5.172	0.375	tINS	RR	3	R46C28[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s12/F
5.179	0.007	tNET	RR	1	R46C28[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3235_s2/I3
5.460	0.281	tINS	RF	1	R46C28[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3235_s2/F
5.977	0.517	tNET	FF	1	R46C28[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.913	1.513	tNET	RR	1	R46C28[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0/CLK
7.663	-0.250	tSu		1	R46C28[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_r1_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	6.400
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.656, 14.720%; route: 3.526, 79.101%; tC2Q: 0.275, 6.179%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.513, 100.000%

Path3

Path Summary:

Slack	2.097
Data Arrival Time	5.559
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/CLK
1.795	0.275	tC2Q	RR	598	R42C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn_s0/Q
4.786	2.991	tNET	RR	1	R46C27[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3227_s2/I0
5.060	0.274	tINS	RF	1	R46C27[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/n3227_s2/F
5.559	0.500	tNET	FF	1	R46C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s1/CLK
7.656	-0.250	tSu		1	R46C27[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/tx_data_en_encode_o_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.274, 6.774%; route: 3.490, 86.408%; tC2Q: 0.275, 6.818%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path4

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_33_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_33_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_33_s0/CLK
7.656	-0.250	tSu		1	R46C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_33_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path5

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_35_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_35_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_35_s0/CLK
7.656	-0.250	tSu		1	R46C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_35_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path6

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_97_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C19[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_97_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C19[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_97_s0/CLK
7.656	-0.250	tSu		1	R46C19[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_97_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path7

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_99_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_99_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_99_s0/CLK
7.656	-0.250	tSu		1	R46C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_99_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path8

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_9_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C7[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C7[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_9_s0/CLK
7.656	-0.250	tSu		1	R46C7[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_9_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path9

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_13_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C7[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C7[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_13_s0/CLK
7.656	-0.250	tSu		1	R46C7[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_13_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path10

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_15_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C7[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C7[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_15_s0/CLK
7.656	-0.250	tSu		1	R46C7[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_15_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path11

Path Summary:

Slack	2.239
Data Arrival Time	5.417
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_63_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.417	3.632	tNET	FF	1	R46C7[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_63_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R46C7[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_63_s0/CLK
7.656	-0.250	tSu		1	R46C7[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_c_r_63_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.632, 93.210%; tC2Q: 0.265, 6.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path12

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_5_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C15[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C15[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_5_s0/CLK
7.656	-0.250	tSu		1	R45C15[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_5_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path13

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_40_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C19[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_40_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C19[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_40_s0/CLK
7.656	-0.250	tSu		1	R45C19[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_40_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path14

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_42_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_42_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_42_s0/CLK
7.656	-0.250	tSu		1	R45C19[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/o_data_ff_42_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path15

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_18_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C15[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_18_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C15[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_18_s0/CLK
7.656	-0.250	tSu		1	R45C15[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_18_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path16

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_42_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C19[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_42_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C19[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_42_s0/CLK
7.656	-0.250	tSu		1	R45C19[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_42_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path17

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_56_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_56_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_56_s0/CLK
7.656	-0.250	tSu		1	R45C19[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_56_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path18

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_82_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C15[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_82_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C15[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_82_s0/CLK
7.656	-0.250	tSu		1	R45C15[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_82_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path19

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_106_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_106_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_106_s0/CLK
7.656	-0.250	tSu		1	R45C19[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_p132btxgears/buffer_106_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path20

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_15_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_15_s0/CLK
7.656	-0.250	tSu		1	R45C11[3][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_15_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path21

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_30_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_30_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_30_s0/CLK
7.656	-0.250	tSu		1	R45C11[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_30_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path22

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_27_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_27_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_27_s0/CLK
7.656	-0.250	tSu		1	R45C11[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_27_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path23

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_30_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_30_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_30_s0/CLK
7.656	-0.250	tSu		1	R45C11[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_30_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path24

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_31_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_31_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_31_s0/CLK
7.656	-0.250	tSu		1	R45C11[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_31_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Path25

Path Summary:

Slack	2.241
Data Arrival Time	5.416
Data Required Time	7.656
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_32_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
1.520	1.520	tNET	RR	1	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/CLK
1.785	0.265	tC2Q	RF	627	R51C13[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n_s0/Q
5.416	3.631	tNET	FF	1	R45C11[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_32_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					pclk
6.400	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
7.907	1.507	tNET	RR	1	R45C11[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_32_s0/CLK
7.656	-0.250	tSu		1	R45C11[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_usb3_1_scramble/data_out_r_32_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.520, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.631, 93.208%; tC2Q: 0.265, 6.792%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.507, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.307
Data Arrival Time	2.340
Data Required Time	2.033
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_15_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.340	0.307	tNET	RR	1	R37C33[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.081	2.081	tNET	RR	1	R37C33[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_15_s1/CLK
2.033	-0.048	tHld		1	R37C33[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_15_s1

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.307, 70.309%; tC2Q: 0.130, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.081, 100.000%

Path2

Path Summary:

Slack	0.307
Data Arrival Time	2.340
Data Required Time	2.033
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_4_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.340	0.307	tNET	RR	1	R37C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.081	2.081	tNET	RR	1	R37C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_4_s1/CLK
2.033	-0.048	tHld		1	R37C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_4_s1

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.307, 70.309%; tC2Q: 0.130, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.081, 100.000%

Path3

Path Summary:

Slack	0.307
Data Arrival Time	2.340
Data Required Time	2.033
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_5_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.340	0.307	tNET	RR	1	R37C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.081	2.081	tNET	RR	1	R37C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_5_s1/CLK
2.033	-0.048	tHld		1	R37C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_5_s1

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.307, 70.309%; tC2Q: 0.130, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.081, 100.000%

Path4

Path Summary:

Slack	0.307
Data Arrival Time	2.340
Data Required Time	2.033
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_6_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.340	0.307	tNET	RR	1	R37C33[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.081	2.081	tNET	RR	1	R37C33[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_6_s1/CLK
2.033	-0.048	tHld		1	R37C33[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_6_s1

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.307, 70.309%; tC2Q: 0.130, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.081, 100.000%

Path5

Path Summary:

Slack	0.307
Data Arrival Time	2.340
Data Required Time	2.033
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_7_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.340	0.307	tNET	RR	1	R37C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.081	2.081	tNET	RR	1	R37C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_7_s1/CLK
2.033	-0.048	tHld		1	R37C33[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_7_s1

Path Statistics:

Clock Skew	0.177
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.307, 70.309%; tC2Q: 0.130, 29.691%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.081, 100.000%

Path6

Path Summary:

Slack	0.350
Data Arrival Time	2.213
Data Required Time	1.863
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt0_10_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.213	0.180	tNET	RR	1	R41C35[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt0_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.911	1.911	tNET	RR	1	R41C35[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt0_10_s1/CLK
1.863	-0.048	tHld		1	R41C35[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt0_10_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.911, 100.000%

Path7

Path Summary:

Slack	0.356
Data Arrival Time	2.211
Data Required Time	1.856
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_1_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.211	0.178	tNET	RR	1	R39C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R39C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_1_s1/CLK
1.856	-0.048	tHld		1	R39C33[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%

Path8

Path Summary:

Slack	0.356
Data Arrival Time	2.211
Data Required Time	1.856
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_8_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.211	0.178	tNET	RR	1	R39C33[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_8_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R39C33[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_8_s1/CLK
1.856	-0.048	tHld		1	R39C33[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%

Path9

Path Summary:

Slack	0.358
Data Arrival Time	2.395
Data Required Time	2.037
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_rden_o_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
2.214	0.130	tC2Q	RR	144	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
2.395	0.181	tNET	RR	1	R33C34[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_rden_o_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R33C34[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_rden_o_s1/CLK
2.037	-0.048	tHld		1	R33C34[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/upar_rden_o_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.181, 58.261%; tC2Q: 0.130, 41.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path10

Path Summary:

Slack	0.358
Data Arrival Time	2.395
Data Required Time	2.037
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/cur_state_0_s0
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
2.214	0.130	tC2Q	RR	144	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
2.395	0.181	tNET	RR	1	R33C34[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/cur_state_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R33C34[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/cur_state_0_s0/CLK
2.037	-0.048	tHld		1	R33C34[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/cur_state_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.181, 58.261%; tC2Q: 0.130, 41.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path11

Path Summary:

Slack	0.360
Data Arrival Time	2.397
Data Required Time	2.037
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_11_s0
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
2.214	0.130	tC2Q	RR	144	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
2.397	0.183	tNET	RR	1	R35C32[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R35C32[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_11_s0/CLK
2.037	-0.048	tHld		1	R35C32[1][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path12

Path Summary:

Slack	0.360
Data Arrival Time	2.397
Data Required Time	2.037
From	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0
To	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_12_s0
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/CLK
2.214	0.130	tC2Q	RR	144	R32C32[2][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/rstn_s0/Q
2.397	0.183	tNET	RR	1	R35C32[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R35C32[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_12_s0/CLK
2.037	-0.048	tHld		1	R35C32[0][A]	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst/u_upar_arbiter/drp_addr_serdes_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.183, 58.501%; tC2Q: 0.130, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path13

Path Summary:

Slack	0.385
Data Arrival Time	2.425
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_3_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.425	0.392	tNET	RR	1	R37C31[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C31[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_3_s1/CLK
2.040	-0.048	tHld		1	R37C31[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_addr_3_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 75.172%; tC2Q: 0.130, 24.828%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path14

Path Summary:

Slack	0.385
Data Arrival Time	2.425
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_value_0_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.425	0.392	tNET	RR	1	R37C31[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_value_0_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C31[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_value_0_s1/CLK
2.040	-0.048	tHld		1	R37C31[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/csr_value_0_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 75.172%; tC2Q: 0.130, 24.828%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path15

Path Summary:

Slack	0.393
Data Arrival Time	2.434
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_2_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C35[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C35[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_2_s1/CLK
2.040	-0.048	tHld		1	R37C35[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_2_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path16

Path Summary:

Slack	0.393
Data Arrival Time	2.434
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_3_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C35[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C35[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_3_s1/CLK
2.040	-0.048	tHld		1	R37C35[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_3_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path17

Path Summary:

Slack	0.393
Data Arrival Time	2.434
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_13_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C35[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C35[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_13_s1/CLK
2.040	-0.048	tHld		1	R37C35[1][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_13_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path18

Path Summary:

Slack	0.393
Data Arrival Time	2.434
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_14_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C35[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C35[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_14_s1/CLK
2.040	-0.048	tHld		1	R37C35[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_14_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path19

Path Summary:

Slack	0.393
Data Arrival Time	2.434
Data Required Time	2.040
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_15_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C35[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.088	2.088	tNET	RR	1	R37C35[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_15_s1/CLK
2.040	-0.048	tHld		1	R37C35[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_15_s1

Path Statistics:

Clock Skew	0.185
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.088, 100.000%

Path20

Path Summary:

Slack	0.397
Data Arrival Time	2.434
Data Required Time	2.037
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_8_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C34[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R37C34[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_8_s1/CLK
2.037	-0.048	tHld		1	R37C34[0][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_8_s1

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path21

Path Summary:

Slack	0.397
Data Arrival Time	2.434
Data Required Time	2.037
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_9_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C34[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R37C34[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_9_s1/CLK
2.037	-0.048	tHld		1	R37C34[0][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_9_s1

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path22

Path Summary:

Slack	0.397
Data Arrival Time	2.434
Data Required Time	2.037
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_10_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C34[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R37C34[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_10_s1/CLK
2.037	-0.048	tHld		1	R37C34[2][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_10_s1

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path23

Path Summary:

Slack	0.397
Data Arrival Time	2.434
Data Required Time	2.037
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_11_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C34[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R37C34[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_11_s1/CLK
2.037	-0.048	tHld		1	R37C34[2][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_11_s1

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path24

Path Summary:

Slack	0.397
Data Arrival Time	2.434
Data Required Time	2.037
From	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_12_s1
Launch Clk	drp_clk:[R]
Latch Clk	drp_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.903	1.903	tNET	RR	1	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/CLK
2.033	0.130	tC2Q	RR	112	R42C33[1][B]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/upar_rstn_r1_s0/Q
2.434	0.400	tNET	RR	1	R37C34[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk
0.000	0.000	tCL	RR	272	R2C2	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
2.084	2.084	tNET	RR	1	R37C34[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_12_s1/CLK
2.037	-0.048	tHld		1	R37C34[3][A]	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_upar_csr/cnt1_12_s1

Path Statistics:

Clock Skew	0.181
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.903, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 75.552%; tC2Q: 0.130, 24.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.084, 100.000%

Path25

Path Summary:

Slack	0.417
Data Arrival Time	0.981
Data Required Time	0.564
From	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0
To	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.612	0.612	tNET	RR	1	R13C98[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/CLK
0.742	0.130	tC2Q	RR	5	R13C98[2][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_s0/Q
0.981	0.239	tNET	RR	1	R12C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	12308	R2C2	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_TX_O_FABRIC_CLK
0.612	0.612	tNET	RR	1	R12C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0/CLK
0.564	-0.048	tHld		1	R12C90[0][A]	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/ltssm_go_u_d0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.612, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.239, 64.878%; tC2Q: 0.130, 35.122%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.612, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	1.216
Actual Width:	1.992
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.337	2.137	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.330	0.930	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	1.220
Actual Width:	1.995
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.331	2.131	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.326	0.926	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	1.220
Actual Width:	1.995
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.331	2.131	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.326	0.926	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	1.220
Actual Width:	1.995
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.331	2.131	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.326	0.926	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack:	1.220
Actual Width:	1.996
Required Width:	0.776
Type:	High Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.138	2.138	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
4.134	0.934	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW6

MPW Summary:

Slack:	1.223
Actual Width:	1.999
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.324	2.124	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.323	0.922	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_1_s/CLKA

MPW7

MPW Summary:

Slack:	1.223
Actual Width:	1.999
Required Width:	0.776
Type:	Low Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
5.324	2.124	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			q0_lane1_fabric_rx_clk
6.400	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
7.323	0.922	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	1.223
Actual Width:	1.999
Required Width:	0.776
Type:	High Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
4.131	0.931	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/mem_mem_0_0_s/CLKA

MPW9

MPW Summary:

Slack:	1.223
Actual Width:	1.999
Required Width:	0.776
Type:	High Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
4.131	0.931	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_rx_async_fifo/mem_mem_0_0_s/CLKA

MPW10

MPW Summary:

Slack:	1.223
Actual Width:	1.999
Required Width:	0.776
Type:	High Pulse Width
Clock:	q0_lane1_fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			q0_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
2.132	2.132	tNET	RR	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.200	0.000			active clock edge time
3.200	0.000			q0_lane1_fabric_rx_clk
3.200	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE1_PCS_RX_O_FABRIC_CLK
4.131	0.931	tNET	FF	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/u_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
12308	pclk	0.001	1.876
2624	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/link_rst_n_d0	0.623	1.723
1625	SerDes_Top_inst/q0_lane1_fabric_rx_clk	1.007	2.488
868	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/rx_reset_n	2.145	2.772
733	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3r/n340_7	2.243	2.447
627	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/Inst_datapath/fast_reset_n	1.338	3.806
598	SerDes_Top_inst/USB3_1_PHY_Top_inst/Inst_usb3_1_phy/internel_resetn	1.033	3.191
520	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/prot_rst_n_d1	2.204	2.668
322	phy_resetn_o	6.443	3.051
294	USB3_2_Device_Controller_Top_inst/usb3_2_device_controller_inst/iu3l/buf_out_val_adv[8]	2.673	2.221

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R44C77	93.06%
R44C79	93.06%
R46C44	93.06%
R48C45	90.28%
R43C79	90.28%
R44C75	90.28%
R44C78	90.28%
R45C77	90.28%
R43C78	88.89%
R44C76	88.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name pclk -period 6.4 -waveform {0 3.2} [get_nets {pclk}]
TC_CLOCK	Actived	create_clock -name q0_lane1_fabric_rx_clk -period 6.4 -waveform {0 3.2} [get_nets {SerDes_Top_inst/q0_lane1_fabric_rx_clk}]
TC_CLOCK	Actived	create_clock -name drp_clk -period 10 -waveform {0 5} [get_nets {SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[1]}]
TC_CLOCK	Actived	create_clock -name fclk -period 41.667 -waveform {0 20.834} [get_nets {fclk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {pclk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {q0_lane1_fabric_rx_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {drp_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {fclk}]
TC_REPORT_TIMING	Actived	report_timing -setup -max_paths 100 -max_common_paths 1