Pin Messages

Report Title Pin Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_USB_Audio_Class_RefDesign\project\impl\gwsynthesis\Gowin_UAC_V1_0.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_USB_Audio_Class_RefDesign\project\src\Gowin_UAC_V1_0.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11\Gowin_USB_Audio_Class_RefDesign\project\src\Gowin_UAC_V1_0.sdc
Tool Version V1.9.11 (64-bit)
Part Number GW2AR-LV18QN88C8/I7
Device GW2AR-18
Device Version C
Created Time Tue Dec 24 15:49:06 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
CLK_12M - 10/6 Y in IOL29[A] GCLKT_6 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
CLK_IIS - 35/4 Y in IOB30[A] GCLKT_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
USB_RXDP_I - 77/1 Y in IOT30[A] GCLKT_1 LVDS25 NA NONE NA NA NA NA NA OFF 3.3
USB_RXDN_I - 71/1 Y in IOT44[A] - LVDS25 NA NONE NA NA NA NA NA OFF 3.3
USB_PULLUP_EN_O - 80/0 Y out IOT27[A] GCLKT_0 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
SPK_IIS_LRCK_O1 - 41/4 Y out IOB43[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_BCLK_O1 - 39/4 Y out IOB40[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_DATA_O1 - 37/4 Y out IOB34[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_LRCK_O2 - 32/5 Y out IOB18[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_BCLK_O2 - 30/5 Y out IOB14[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_DATA_O2 - 26/5 Y out IOB6[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_LRCK_O3 - 33/5 Y out IOB24[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_BCLK_O3 - 31/5 Y out IOB18[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
SPK_IIS_DATA_O3 - 29/5 Y out IOB14[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
USB_DXP_IO USB_DXN_IO 73,72/1 Y io IOT40 - LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
USB_TERM_DP_IO - 75/1 Y io IOT34[A] - LVCMOS33 12 NONE NA NONE OFF NA NA NA 3.3
USB_TERM_DN_IO - 74/1 Y io IOT34[B] - LVCMOS33 12 NONE NA NONE OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
86/0 - in IOT4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
85/0 - in IOT4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
84/0 - in IOT6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
83/0 - in IOT6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
82/0 - in IOT17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
81/0 - in IOT17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
80/0 USB_PULLUP_EN_O out IOT27[A] GCLKT_0 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
79/0 - in IOT27[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
77/1 USB_RXDP_I(p) in IOT30[A] GCLKT_1 LVDS25 NA NONE NA NA NA NA NA OFF 3.3
76/1 USB_RXDP_I(n) in IOT30[B] GCLKT_1 LVDS25 NA NONE NA NA NA NA NA OFF 3.3
75/1 USB_TERM_DP_IO io IOT34[A] - LVCMOS33 12 NONE NA NONE OFF NA NA NA 3.3
74/1 USB_TERM_DN_IO io IOT34[B] - LVCMOS33 12 NONE NA NONE OFF NA NA NA 3.3
73/1 USB_DXP_IO io IOT40[A] - LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
72/1 USB_DXN_IO io IOT40[B] - LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
71/1 USB_RXDN_I(p) in IOT44[A] - LVDS25 NA NONE NA NA NA NA NA OFF 3.3
70/1 USB_RXDN_I(n) in IOT44[B] - LVDS25 NA NONE NA NA NA NA NA OFF 3.3
69/1 - in IOT50[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
25/5 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
26/5 SPK_IIS_DATA_O2 out IOB6[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
27/5 - in IOB8[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
28/5 - in IOB8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
29/5 SPK_IIS_DATA_O3 out IOB14[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
30/5 SPK_IIS_BCLK_O2 out IOB14[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
31/5 SPK_IIS_BCLK_O3 out IOB18[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
32/5 SPK_IIS_LRCK_O2 out IOB18[B] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
33/5 SPK_IIS_LRCK_O3 out IOB24[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
34/5 - in IOB24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
35/4 CLK_IIS in IOB30[A] GCLKT_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
36/4 - in IOB30[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
37/4 SPK_IIS_DATA_O1 out IOB34[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
38/4 - in IOB34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
39/4 SPK_IIS_BCLK_O1 out IOB40[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
40/4 - in IOB40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
42/4 - in IOB42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
41/4 SPK_IIS_LRCK_O1 out IOB43[A] - LVCMOS33 8 DOWN NA NA OFF NA NA NA 3.3
4/7 - in IOL7[A] LPLL1_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
10/6 CLK_12M in IOL29[A] GCLKT_6 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
11/6 - in IOL29[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
13/6 - in IOL45[A] LPLL2_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
15/6 - in IOL47[A] LPLL2_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
16/6 - in IOL47[B] LPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
17/6 - in IOL49[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
18/6 - in IOL49[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
19/6 - in IOL51[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
20/6 - in IOL51[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
8/2 - out IOR25[A] TDO LVCMOS18 8 UP NA NA OFF NA NA NA 3.3
5/2 - in IOR25[B] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
6/2 - in IOR26[A] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
7/2 - in IOR26[B] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
63/3 - in IOR29[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
88/3 - in IOR30[A] MODE0 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
87/3 - in IOR30[B] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
9/3 - in IOR31[B] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/3 - in IOR33[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/3 - in IOR33[B] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/3 - in IOR34[A] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/3 - in IOR34[B] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/3 - in IOR35[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
56/3 - in IOR36[A] SO/D1 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
55/3 - in IOR36[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
54/3 - in IOR38[A] DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
53/3 - in IOR38[B] DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
52/3 - in IOR39[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
51/3 - in IOR45[A] RPLL2_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
49/3 - in IOR49[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/3 - in IOR49[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3