Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\TOP.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\fixed_point_divider\fixed_point_divider.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\gowin_rpll\gowin_rpll.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\rpll_peripheral\rpll_peripheral.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\sync_fifo\sync_pkt_fifo.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2_0_softphy\static_macro_define.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2_0_softphy\usb2_0_softphy.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2_0_softphy\usb2_0_softphy_top.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb_descriptor.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb_device_controller\usb_device_controller.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb_fifo.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb_to_multi_serial\usb_to_multi_serial.v
D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb_uart_config.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9 (64-bit)
Part Number GW2AR-LV18QN88C7/I6
Device GW2AR-18
Device Version C
Created Time Mon Dec 25 18:11:08 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 758.273MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.39s, Peak memory usage = 758.273MB
    Optimizing Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 758.273MB
    Optimizing Phase 2: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.512s, Peak memory usage = 758.273MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.283s, Peak memory usage = 758.273MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 758.273MB
    Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 758.273MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 758.273MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.656s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 758.273MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 758.273MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 758.273MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 758.273MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 758.273MB
Generate output files:
    CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.741s, Peak memory usage = 758.273MB
Total Time and Memory Usage CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 758.273MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 20
I/O Buf 19
    IBUF 5
    OBUF 6
    TBUF 1
    IOBUF 6
    ELVDS_IOBUF 1
Register 3854
    DFF 100
    DFFE 384
    DFFS 9
    DFFSE 35
    DFFR 174
    DFFRE 401
    DFFP 53
    DFFPE 49
    DFFC 1289
    DFFCE 1358
    DL 1
    DLN 1
LUT 6788
    LUT2 842
    LUT3 2144
    LUT4 3802
ALU 1066
    ALU 1066
SSRAM 84
    RAM16S4 16
    RAM16SDP4 68
INV 46
    INV 46
IOLOGIC 7
    IDES8 4
    OSER8 1
    IODELAY 2
BSRAM 19
    SDPB 19
CLOCK 4
    CLKDIV 1
    DHCEN 1
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 8404(6834 LUT, 1066 ALU, 84 RAM16) / 20736 41%
Register 3854 / 15750 25%
  --Register as Latch 2 / 15750 <1%
  --Register as FF 3852 / 15750 25%
BSRAM 19 / 46 42%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clkin Base 83.333 12.0 0.000 41.667 clkin_ibuf/I
u_usb_uart_config/jtag_tck_Z Base 10.000 100.0 0.000 5.000 u_usb_uart_config/jtag_tck_Z_s/F
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d Base 10.000 100.0 0.000 5.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_s2/Q
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6 Base 10.000 100.0 0.000 5.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_s2/O
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi1_clk_o_d Base 10.000 100.0 0.000 5.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_clk_o_d_s/F
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n4_6 Base 10.000 100.0 0.000 5.000 u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n4_s2/O
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n9_6 Base 10.000 100.0 0.000 5.000 u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n9_s2/O
u_pll/rpll_inst/CLKOUT.default_gen_clk Generated 2.083 480.0 0.000 1.042 clkin_ibuf/I clkin u_pll/rpll_inst/CLKOUT
u_pll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.083 480.0 0.000 1.042 clkin_ibuf/I clkin u_pll/rpll_inst/CLKOUTP
u_pll/rpll_inst/CLKOUTD.default_gen_clk Generated 16.667 60.0 0.000 8.333 clkin_ibuf/I clkin u_pll/rpll_inst/CLKOUTD
u_pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 6.250 160.0 0.000 3.125 clkin_ibuf/I clkin u_pll/rpll_inst/CLKOUTD3
rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk Generated 20.833 48.0 0.000 10.417 clkin_ibuf/I clkin rpll_peripheral/rpll_inst/CLKOUT
rpll_peripheral/rpll_inst/CLKOUTP.default_gen_clk Generated 20.833 48.0 0.000 10.417 clkin_ibuf/I clkin rpll_peripheral/rpll_inst/CLKOUTP
rpll_peripheral/rpll_inst/CLKOUTD.default_gen_clk Generated 41.667 24.0 0.000 20.833 clkin_ibuf/I clkin rpll_peripheral/rpll_inst/CLKOUTD
rpll_peripheral/rpll_inst/CLKOUTD3.default_gen_clk Generated 62.500 16.0 0.000 31.250 clkin_ibuf/I clkin rpll_peripheral/rpll_inst/CLKOUTD3
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk Generated 8.333 120.0 0.000 4.167 u_pll/rpll_inst/CLKOUT u_pll/rpll_inst/CLKOUT.default_gen_clk u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_usb_uart_config/jtag_tck_Z 100.0(MHz) 130.1(MHz) 9 TOP
2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d 100.0(MHz) 217.9(MHz) 5 TOP
3 u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n4_6 100.0(MHz) 1587.3(MHz) 1 TOP
4 u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/n9_6 100.0(MHz) 1587.3(MHz) 1 TOP
5 u_pll/rpll_inst/CLKOUTD.default_gen_clk 60.0(MHz) 65.6(MHz) 17 TOP
6 rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk 48.0(MHz) 70.2(MHz) 18 TOP
7 u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT.default_gen_clk 120.0(MHz) 138.8(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -7.798
Data Arrival Time 237.945
Data Required Time 230.146
From USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_0_s0
To USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0
Launch Clk rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
229.167 0.000 rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk
230.453 1.287 tCL RR 1125 rpll_peripheral/rpll_inst/CLKOUT
230.678 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_0_s0/CLK
230.968 0.290 tC2Q RF 6 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_0_s0/Q
231.264 0.296 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s16/I1
231.977 0.712 tINS FR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s16/COUT
231.977 0.000 tNET RR 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s17/CIN
232.021 0.044 tINS RF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s17/COUT
232.021 0.000 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s18/CIN
232.065 0.044 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s18/COUT
232.065 0.000 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s19/CIN
232.109 0.044 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s19/COUT
232.109 0.000 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s20/CIN
232.153 0.044 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s20/COUT
232.153 0.000 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s21/CIN
232.197 0.044 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s21/COUT
232.197 0.000 tNET FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s22/CIN
232.241 0.044 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s22/COUT
232.537 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s6/I1
233.231 0.694 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s6/F
233.527 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_2_s13/I2
234.093 0.566 tINS FF 11 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_2_s13/F
234.390 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_0_s11/I2
234.956 0.566 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_0_s11/F
235.252 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_0_s10/I0
235.898 0.646 tINS FF 9 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_0_s10/F
236.195 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s3/I1
236.888 0.694 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s3/F
237.185 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s1/I3
237.648 0.464 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s1/F
237.945 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
230.000 0.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6
230.000 0.000 tCL RR 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_s2/O
230.225 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0/CLK
230.190 -0.035 tUnc USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0
230.146 -0.044 tSu 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0
Path Statistics:
Clock Skew: -1.287
Setup Relationship: 0.833
Logic Level: 10
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%
Arrival Data Path Delay: cell: 4.607, 63.394%; route: 2.370, 32.615%; tC2Q: 0.290, 3.991%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%

Path 2

Path Summary:
Slack -2.911
Data Arrival Time 233.057
Data Required Time 230.146
From USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0
To USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_0_s0
Launch Clk rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
229.167 0.000 rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk
230.453 1.287 tCL RR 1125 rpll_peripheral/rpll_inst/CLKOUT
230.678 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0/CLK
230.968 0.290 tC2Q RF 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0/Q
231.264 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/sclk_1t_s1/I1
231.958 0.694 tINS FF 4 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/sclk_1t_s1/F
232.254 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n362_s1/I2
232.832 0.577 tINS FR 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n362_s1/F
233.057 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_0_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
230.000 0.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6
230.000 0.000 tCL RR 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_s2/O
230.225 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_0_s0/CLK
230.190 -0.035 tUnc USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_0_s0
230.146 -0.044 tSu 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_0_s0
Path Statistics:
Clock Skew: -1.287
Setup Relationship: 0.833
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%
Arrival Data Path Delay: cell: 1.271, 53.442%; route: 0.818, 34.367%; tC2Q: 0.290, 12.191%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%

Path 3

Path Summary:
Slack -2.911
Data Arrival Time 233.057
Data Required Time 230.146
From USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0
To USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_1_s0
Launch Clk rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
229.167 0.000 rpll_peripheral/rpll_inst/CLKOUT.default_gen_clk
230.453 1.287 tCL RR 1125 rpll_peripheral/rpll_inst/CLKOUT
230.678 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0/CLK
230.968 0.290 tC2Q RF 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_reg/reg_spiif_timing_r_5_s0/Q
231.264 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/sclk_1t_s1/I1
231.958 0.694 tINS FF 4 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/sclk_1t_s1/F
232.254 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n362_s1/I2
232.832 0.577 tINS FR 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n362_s1/F
233.057 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
230.000 0.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_6
230.000 0.000 tCL RR 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_gclk_0/n4_s2/O
230.225 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_1_s0/CLK
230.190 -0.035 tUnc USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_1_s0
230.146 -0.044 tSu 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_in_d1_r_1_s0
Path Statistics:
Clock Skew: -1.287
Setup Relationship: 0.833
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%
Arrival Data Path Delay: cell: 1.271, 53.442%; route: 0.818, 34.367%; tC2Q: 0.290, 12.191%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%

Path 4

Path Summary:
Slack -2.890
Data Arrival Time 37.636
Data Required Time 34.746
From USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0
To USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_1_s0
Launch Clk USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
30.000 0.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d
30.000 0.000 tCL RR 18 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_s2/Q
30.225 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0/CLK
30.515 0.290 tC2Q RF 7 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0/Q
30.811 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s13/I1
31.505 0.694 tINS FF 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s13/F
31.801 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s7/I3
32.265 0.464 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s7/F
32.561 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s5/I3
33.025 0.464 tINS FF 4 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s5/F
33.321 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n162_s13/I1
34.015 0.694 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n162_s13/F
34.311 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s11/I0
34.958 0.646 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s11/F
35.254 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s10/I3
35.717 0.464 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s10/F
36.014 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s8/I2
36.580 0.566 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s8/F
36.876 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s7/I3
37.340 0.464 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n164_s7/F
37.636 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
33.333 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
34.600 1.267 tCL RR 2355 u_pll/rpll_inst/CLKOUTD
34.825 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_1_s0/CLK
34.790 -0.035 tUnc USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_1_s0
34.746 -0.044 tSu 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_1_s0
Path Statistics:
Clock Skew: 1.267
Setup Relationship: 3.333
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%
Arrival Data Path Delay: cell: 4.455, 60.111%; route: 2.666, 35.976%; tC2Q: 0.290, 3.913%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%

Path 5

Path Summary:
Slack -2.003
Data Arrival Time 36.749
Data Required Time 34.746
From USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0
To USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_0_s0
Launch Clk USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
30.000 0.000 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_d
30.000 0.000 tCL RR 18 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/jtag_clk_s2/Q
30.225 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0/CLK
30.515 0.290 tC2Q RF 7 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Tap_FSM_u0/state_3_s0/Q
30.811 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s13/I1
31.505 0.694 tINS FF 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s13/F
31.801 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s7/I3
32.265 0.464 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s7/F
32.561 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s3/I2
33.127 0.566 tINS FF 3 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s3/F
33.424 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s1/I3
33.888 0.464 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/n1438_s1/F
34.184 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s12/I2
34.750 0.566 tINS FF 2 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s12/F
35.046 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s9/I3
35.510 0.464 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s9/F
35.806 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s8/I0
36.453 0.646 tINS FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/n165_s8/F
36.749 0.296 tNET FF 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
33.333 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
34.600 1.267 tCL RR 2355 u_pll/rpll_inst/CLKOUTD
34.825 0.225 tNET RR 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_0_s0/CLK
34.790 -0.035 tUnc USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_0_s0
34.746 -0.044 tSu 1 USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Rev_u0/usb_tx_data_0_s0
Path Statistics:
Clock Skew: 1.267
Setup Relationship: 3.333
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%
Arrival Data Path Delay: cell: 3.864, 59.226%; route: 2.370, 36.329%; tC2Q: 0.290, 4.445%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.225, 100.000%