PnR Messages

Report Title PnR Report
Design File D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\impl\gwsynthesis\usb_proj.vg
Physical Constraints File D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2uart.cst
Timing Constraints File D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2uart.sdc
Tool Version V1.9.9 (64-bit)
Part Number GW2AR-LV18QN88C7/I6
Device GW2AR-18
Device Version C
Created Time Mon Dec 25 18:11:28 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Placement Phase 1: CPU time = 0h 0m 0.426s, Elapsed time = 0h 0m 0.426s Placement Phase 2: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Placement Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Total Placement: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s Running routing: Routing Phase 0: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s Routing Phase 1: CPU time = 0h 0m 0.498s, Elapsed time = 0h 0m 0.499s Routing Phase 2: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 758MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 8580/20736 42%
    --LUT,ALU,ROM16 8076(6817 LUT, 1259 ALU, 0 ROM16) -
    --SSRAM(RAM16) 84 -
Register 3854/15750 25%
    --Logic Register as Latch 2/15552 <1%
    --Logic Register as FF 3841/15552 25%
    --I/O Register as Latch 0/198 0%
    --I/O Register as FF 11/198 6%
CLS 5808/10368 57%
I/O Port 20 -
I/O Buf 19 -
    --Input Buf 5 -
    --Output Buf 7 -
    --Inout Buf 7 -
IOLOGIC 4 IDES8
1 OSER8
2 IODELAY
9%
BSRAM 19 SDPB
42%
DSP 00%
PLL 2/2 100%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 1/8 13%
DLLDLY 0/8 0%
DQS 0/1 0%
DHCEN 1/16 7%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 1/8(12%)
bank 1 8/9(88%)
bank 2 0/4(0%)
bank 3 0/17(0%)
bank 4 6/8(75%)
bank 5 6/10(60%)
bank 6 1/9(11%)
bank 7 0/1(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 5/8(63%)
LW 8/8(100%)
GCLK_PIN 3/5(60%)
PLL 2/2(100%)
CLKDIV 1/8(13%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
clkin_d PRIMARY PTR0 PTR1
PHY_CLKOUT PRIMARY PTR0 PTR1
clk_48 PRIMARY PTR0 PTR1
jtag_tck_Z PRIMARY PTR0
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/sclk PRIMARY PTR0 PTR1
PHY_RESET LW -
jtag_clk_d LW -
spi1_clk_o_d LW -
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/reset_calib_Z LW -
u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/reset_r_0[1] LW -
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n21_3 LW -
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n89_3 LW -
USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/u_usb_i2c1_ctrl/u1_i2c/u_fifo/n18_3 LW -
fclk_480M HCLK TOP[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clkin 10/6 Y in IOL29[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
uart_rxd 28/5 Y in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
jtag_tdo 29/5 Y in IOB14[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
usb_rxdp_i 77/1 Y in IOT30[A] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
usb_rxdn_i 71/1 Y in IOT44[A] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
uart_txd 26/5 Y out IOB6[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
jtag_clk 33/5 Y out IOB24[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
jtag_tms 27/5 Y out IOB8[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
jtag_tdi 31/5 Y out IOB18[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
spi1_clk_o 41/4 Y out IOB43[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
spi1_cs_n_o 39/4 Y out IOB40[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
usb_pullup_en_o 80/0 Y out IOT27[A] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
I2C1_SCL 37/4 Y io IOB34[A] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
I2C1_SDA 38/4 Y io IOB34[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
spi1_miso_io 42/4 Y io IOB42[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
spi1_mosi_io 40/4 Y io IOB40[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
usb_dxp_io usb_dxn_io 73,72/1 Y io IOT40 LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
usb_term_dp_io 75/1 Y io IOT34[A] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3
usb_term_dn_io 74/1 Y io IOT34[B] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
86/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
85/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
84/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
83/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
82/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
81/0 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
80/0 usb_pullup_en_o out IOT27[A] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
79/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
77/1 usb_rxdp_i(p) in IOT30[A] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
76/1 usb_rxdp_i(n) in IOT30[B] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
75/1 usb_term_dp_io io IOT34[A] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3
74/1 usb_term_dn_io io IOT34[B] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3
73/1 usb_dxp_io io IOT40[A] LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
72/1 usb_dxn_io io IOT40[B] LVCMOS33D 4 NONE NA NA NA NA NA NA 3.3
71/1 usb_rxdn_i(p) in IOT44[A] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
70/1 usb_rxdn_i(n) in IOT44[B] LVDS25 NA NONE NA NA NA NA NA OFF 3.3
69/1 - in IOT50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
25/5 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
26/5 uart_txd out IOB6[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
27/5 jtag_tms out IOB8[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
28/5 uart_rxd in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
29/5 jtag_tdo in IOB14[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
30/5 - in IOB14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
31/5 jtag_tdi out IOB18[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
32/5 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
33/5 jtag_clk out IOB24[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
34/5 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
35/4 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
36/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
37/4 I2C1_SCL io IOB34[A] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
38/4 I2C1_SDA io IOB34[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
39/4 spi1_cs_n_o out IOB40[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
40/4 spi1_mosi_io io IOB40[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
42/4 spi1_miso_io io IOB42[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
41/4 spi1_clk_o out IOB43[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
4/7 - in IOL7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
10/6 clkin in IOL29[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
11/6 - in IOL29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
13/6 - in IOL45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
15/6 - in IOL47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
16/6 - in IOL47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
17/6 - in IOL49[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
18/6 - in IOL49[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
19/6 - in IOL51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
20/6 - in IOL51[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
8/2 - out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.2
5/2 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
6/2 - in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
7/2 - in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
63/3 - in IOR29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/3 - in IOR35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/3 - in IOR36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
55/3 - in IOR36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/3 - in IOR38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
53/3 - in IOR38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/3 - in IOR39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
51/3 - in IOR45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/3 - in IOR49[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/3 - in IOR49[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8