Timing Messages
Report Title | Timing Analysis Report |
Design File | D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\impl\gwsynthesis\usb_proj.vg |
Physical Constraints File | D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2uart.cst |
Timing Constraint File | D:\project\12-IP_realease\1_USB_to_Multi_Serial_Protocol_Bridging\6-ref_design\Gowin USB to Multi Serial Protocol Bridge IP RefDesign_2\project\USB_to_Multi_Serial_Protocol_Bridge_Pro_1\src\usb2uart.sdc |
Tool Version | V1.9.9 (64-bit) |
Part Number | GW2AR-LV18QN88C7/I6 |
Device | GW2AR-18 |
Device Version | C |
Created Time | Mon Dec 25 18:11:29 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C7/I6 |
Hold Delay Model | Fast 1.05V 0C C7/I6 |
Numbers of Paths Analyzed | 11785 |
Numbers of Endpoints Analyzed | 11052 |
Numbers of Falling Endpoints | 8 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
peripheral_clk | Base | 20.833 | 48.001 | 0.000 | 10.416 | rpll_peripheral/rpll_inst/CLKOUT | ||
jtag_tck | Base | 33.333 | 30.000 | 0.000 | 16.666 | jtag_tck_Z | ||
clk_in | Base | 83.333 | 12.000 | 0.000 | 41.670 | clkin | ||
clk_480 | Base | 2.083 | 480.077 | 0.000 | 1.042 | u_pll/rpll_inst/CLKOUT | ||
clk_60 | Base | 16.667 | 59.999 | 0.000 | 8.330 | u_pll/rpll_inst/CLKOUTD | ||
clk_120 | Base | 8.333 | 120.005 | 0.000 | 4.170 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT | ||
spi1_clk | Base | 20.833 | 48.001 | 0.000 | 10.416 | spi1_clk_o spi1_clk_o_d | ||
jtag_clk | Base | 33.333 | 30.000 | 0.000 | 16.666 | jtag_clk jtag_clk_d | ||
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.083 | 480.002 | 0.000 | 1.042 | clkin_ibuf/I | clk_in | u_pll/rpll_inst/CLKOUTP |
u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 6.250 | 160.001 | 0.000 | 3.125 | clkin_ibuf/I | clk_in | u_pll/rpll_inst/CLKOUTD3 |
rpll_peripheral/rpll_inst/CLKOUTP.default_gen_clk | Generated | 20.833 | 48.000 | 0.000 | 10.417 | clkin_ibuf/I | clk_in | rpll_peripheral/rpll_inst/CLKOUTP |
rpll_peripheral/rpll_inst/CLKOUTD.default_gen_clk | Generated | 41.667 | 24.000 | 0.000 | 20.833 | clkin_ibuf/I | clk_in | rpll_peripheral/rpll_inst/CLKOUTD |
rpll_peripheral/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 62.500 | 16.000 | 0.000 | 31.250 | clkin_ibuf/I | clk_in | rpll_peripheral/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | peripheral_clk | 48.001(MHz) | 49.912(MHz) | 9 | TOP |
2 | jtag_tck | 30.000(MHz) | 102.133(MHz) | 9 | TOP |
3 | clk_60 | 59.999(MHz) | 60.773(MHz) | 12 | TOP |
4 | clk_120 | 120.005(MHz) | 131.928(MHz) | 8 | TOP |
5 | jtag_clk | 30.000(MHz) | 155.728(MHz) | 5 | TOP |
No timing paths to get frequency of clk_in!
No timing paths to get frequency of clk_480!
No timing paths to get frequency of spi1_clk!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of rpll_peripheral/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of rpll_peripheral/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of rpll_peripheral/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
peripheral_clk | Setup | 0.000 | 0 |
peripheral_clk | Hold | 0.000 | 0 |
jtag_tck | Setup | 0.000 | 0 |
jtag_tck | Hold | 0.000 | 0 |
clk_in | Setup | 0.000 | 0 |
clk_in | Hold | 0.000 | 0 |
clk_480 | Setup | 0.000 | 0 |
clk_480 | Hold | 0.000 | 0 |
clk_60 | Setup | 0.000 | 0 |
clk_60 | Hold | 0.000 | 0 |
clk_120 | Setup | 0.000 | 0 |
clk_120 | Hold | 0.000 | 0 |
spi1_clk | Setup | 0.000 | 0 |
spi1_clk | Hold | 0.000 | 0 |
jtag_clk | Setup | 0.000 | 0 |
jtag_clk | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
rpll_peripheral/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.212 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_9_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.411 |
2 | 0.399 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_3_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0/D | peripheral_clk:[R] | peripheral_clk:[F] | 10.416 | -0.023 | 9.996 |
3 | 0.426 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_10_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.197 |
4 | 0.486 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.138 |
5 | 0.548 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_9_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.075 |
6 | 0.570 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_10_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.053 |
7 | 0.589 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 16.034 |
8 | 0.698 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.925 |
9 | 0.753 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D | clk_120:[R] | clk_120:[R] | 8.333 | 0.000 | 7.536 |
10 | 0.753 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/D | clk_120:[R] | clk_120:[R] | 8.333 | 0.000 | 7.536 |
11 | 0.756 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.867 |
12 | 0.810 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.813 |
13 | 0.974 | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.649 |
14 | 1.088 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.535 |
15 | 1.121 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.503 |
16 | 1.165 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/Q4 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D | clk_120:[R] | clk_120:[R] | 8.333 | 0.000 | 7.124 |
17 | 1.168 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.456 |
18 | 1.233 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.390 |
19 | 1.250 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_9_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.374 |
20 | 1.258 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_6_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.365 |
21 | 1.265 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/Q4 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D | clk_120:[R] | clk_120:[R] | 8.333 | 0.000 | 7.025 |
22 | 1.270 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_6_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.354 |
23 | 1.297 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/D | clk_120:[R] | clk_120:[R] | 8.333 | 0.000 | 6.993 |
24 | 1.319 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.304 |
25 | 1.343 | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_7_s1/D | clk_60:[R] | clk_60:[R] | 16.667 | 0.000 | 15.280 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.103 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[6] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.415 |
2 | 0.103 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/Q | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[3] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.415 |
3 | 0.249 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[7] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.561 |
4 | 0.249 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[6] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.561 |
5 | 0.257 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[0] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.569 |
6 | 0.264 | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/rp_8_s0/Q | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/RAM_RAM_0_0_s/ADB[11] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.411 |
7 | 0.267 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_7_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[7] | jtag_tck:[R] | jtag_tck:[R] | 0.000 | 0.000 | 0.578 |
8 | 0.267 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_6_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[6] | jtag_tck:[R] | jtag_tck:[R] | 0.000 | 0.000 | 0.578 |
9 | 0.268 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[7] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.580 |
10 | 0.268 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[6] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.580 |
11 | 0.268 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[3] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.580 |
12 | 0.268 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[2] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.580 |
13 | 0.268 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_1_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.580 |
14 | 0.270 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_7_s0/Q | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[7] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.581 |
15 | 0.271 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[1] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.583 |
16 | 0.283 | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_5_s0/Q | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[5] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.595 |
17 | 0.283 | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_4_s0/Q | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[4] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.595 |
18 | 0.283 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.595 |
19 | 0.283 | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/Q | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[2] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.595 |
20 | 0.285 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_29_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[29] | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 0.596 |
21 | 0.286 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_21_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[21] | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 0.598 |
22 | 0.286 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_17_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[17] | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 0.598 |
23 | 0.286 | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q | usb_fifo/usb_rx_buf_ep4/sync_pkt_fifo/RAM_RAM_0_0_s/DI[1] | clk_60:[R] | clk_60:[R] | 0.000 | 0.000 | 0.598 |
24 | 0.288 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_12_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[12] | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 0.599 |
25 | 0.292 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser8txd/D6 | clk_120:[R] | clk_120:[R] | 0.000 | 0.000 | 0.411 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.931 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
2 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
3 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
4 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
5 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
6 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
7 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
8 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
9 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
10 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
11 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
12 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
13 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
14 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_2_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
15 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
16 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
17 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
18 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
19 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
20 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
21 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
22 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
23 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
24 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
25 | 1.435 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR | clk_120:[F] | clk_120:[R] | 4.163 | 0.023 | 2.662 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.097 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.111 |
2 | 1.097 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.111 |
3 | 1.117 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.131 |
4 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
5 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
6 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
7 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
8 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
9 | 1.125 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.139 |
10 | 1.201 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_7_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.215 |
11 | 1.219 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.233 |
12 | 1.223 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.237 |
13 | 1.223 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.237 |
14 | 1.223 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.237 |
15 | 1.223 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_6_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.237 |
16 | 1.274 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.287 |
17 | 1.274 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_6_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.287 |
18 | 1.274 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_7_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.287 |
19 | 1.281 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.295 |
20 | 1.281 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.295 |
21 | 1.281 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.295 |
22 | 1.281 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.295 |
23 | 1.285 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.299 |
24 | 1.285 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.299 |
25 | 1.285 | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0/CLEAR | peripheral_clk:[R] | peripheral_clk:[R] | 0.000 | 0.000 | 1.299 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0 |
2 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0 |
3 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0 |
4 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0 |
5 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0 |
6 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0 |
7 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
8 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
9 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0 |
10 | 2.817 | 4.067 | 1.250 | Low Pulse Width | clk_120 | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.212 |
Data Arrival Time | 16.715 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_9_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.131 | 1.269 | tNET | FF | 1 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/I0 |
11.777 | 0.646 | tINS | FF | 5 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/F |
12.601 | 0.823 | tNET | FF | 1 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/I2 |
13.313 | 0.712 | tINS | FR | 2 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/F |
13.317 | 0.003 | tNET | RR | 1 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/I3 |
13.883 | 0.566 | tINS | RF | 4 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/F |
13.899 | 0.016 | tNET | FF | 1 | R16C18[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n101_s2/I3 |
14.545 | 0.646 | tINS | FF | 3 | R16C18[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n101_s2/F |
15.075 | 0.529 | tNET | FF | 1 | R17C17[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n100_s2/I1 |
15.787 | 0.712 | tINS | FR | 1 | R17C17[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n100_s2/F |
16.003 | 0.216 | tNET | RR | 1 | R17C17[2][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n100_s0/I1 |
16.715 | 0.712 | tINS | RR | 1 | R17C17[2][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n100_s0/F |
16.715 | 0.000 | tNET | RR | 1 | R17C17[2][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R17C17[2][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_9_s1/CLK |
16.927 | -0.044 | tSu | 1 | R17C17[2][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.841, 41.687%; route: 9.280, 56.546%; tC2Q: 0.290, 1.767% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path2
Path Summary:
Slack | 0.399 |
Data Arrival Time | 10.300 |
Data Required Time | 10.699 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_3_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 1 | R48C37[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_3_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 3 | R48C37[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_3_s1/Q |
1.699 | 1.105 | tNET | FF | 2 | R47C38[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s19/I0 |
2.385 | 0.686 | tINS | FR | 1 | R47C38[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s19/COUT |
2.385 | 0.000 | tNET | RR | 2 | R47C38[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s20/CIN |
2.429 | 0.044 | tINS | RF | 1 | R47C38[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s20/COUT |
2.429 | 0.000 | tNET | FF | 2 | R47C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s21/CIN |
2.473 | 0.044 | tINS | FF | 1 | R47C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s21/COUT |
2.473 | 0.000 | tNET | FF | 2 | R47C39[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s22/CIN |
2.517 | 0.044 | tINS | FF | 1 | R47C39[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/n154_s22/COUT |
3.110 | 0.593 | tNET | FF | 1 | R47C39[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s6/I1 |
3.804 | 0.694 | tINS | FF | 2 | R47C39[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s6/F |
4.118 | 0.314 | tNET | FF | 1 | R47C37[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s4/I3 |
4.582 | 0.464 | tINS | FF | 3 | R47C37[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/period_cnt_r_7_s4/F |
5.201 | 0.619 | tNET | FF | 1 | R50C37[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_txdata_rd_Z_s5/I3 |
5.888 | 0.686 | tINS | FR | 5 | R50C37[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_txdata_rd_Z_s5/F |
6.111 | 0.223 | tNET | RR | 1 | R51C37[3][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_1_s9/I0 |
6.757 | 0.646 | tINS | RF | 5 | R51C37[3][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_1_s9/F |
7.284 | 0.527 | tNET | FF | 1 | R50C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_1_s12/I0 |
7.850 | 0.566 | tINS | FF | 5 | R50C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/spi_ns_1_s12/F |
8.365 | 0.514 | tNET | FF | 1 | R48C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s1/I1 |
9.011 | 0.646 | tINS | FF | 2 | R48C38[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_en_s1/F |
10.300 | 1.289 | tNET | FF | 1 | R45C37[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.416 | 10.416 | active clock edge time | ||||
10.416 | 0.000 | peripheral_clk | ||||
10.416 | 0.000 | tCL | FF | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
10.743 | 0.327 | tNET | FF | 1 | R45C37[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0/CLK |
10.699 | -0.044 | tSu | 1 | R45C37[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_spiif/master_clk_d_en_r_s0 |
Path Statistics:
Clock Skew | 0.023 |
Setup Relationship | 10.416 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 4.521, 45.226%; route: 5.185, 51.873%; tC2Q: 0.290, 2.901% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Path3
Path Summary:
Slack | 0.426 |
Data Arrival Time | 16.501 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_10_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.131 | 1.269 | tNET | FF | 1 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/I0 |
11.777 | 0.646 | tINS | FF | 5 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/F |
12.601 | 0.823 | tNET | FF | 1 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/I2 |
13.313 | 0.712 | tINS | FR | 2 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/F |
13.317 | 0.003 | tNET | RR | 1 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/I3 |
13.883 | 0.566 | tINS | RF | 4 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/F |
13.899 | 0.016 | tNET | FF | 1 | R16C18[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n101_s2/I3 |
14.545 | 0.646 | tINS | FF | 3 | R16C18[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n101_s2/F |
15.075 | 0.529 | tNET | FF | 1 | R17C17[1][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n99_s1/I2 |
15.787 | 0.712 | tINS | FR | 1 | R17C17[1][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n99_s1/F |
15.789 | 0.002 | tNET | RR | 1 | R17C17[1][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n99_s0/I0 |
16.501 | 0.712 | tINS | RR | 1 | R17C17[1][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n99_s0/F |
16.501 | 0.000 | tNET | RR | 1 | R17C17[1][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R17C17[1][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_10_s1/CLK |
16.927 | -0.044 | tSu | 1 | R17C17[1][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.841, 42.238%; route: 9.066, 55.972%; tC2Q: 0.290, 1.790% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path4
Path Summary:
Slack | 0.486 |
Data Arrival Time | 16.442 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.805 | 1.175 | tNET | FF | 1 | R17C48[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s6/I1 |
14.269 | 0.464 | tINS | FF | 1 | R17C48[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s6/F |
14.275 | 0.005 | tNET | FF | 1 | R17C48[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s5/I0 |
14.961 | 0.686 | tINS | FR | 1 | R17C48[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s5/F |
14.962 | 0.002 | tNET | RR | 1 | R17C48[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s2/I1 |
15.540 | 0.577 | tINS | RR | 1 | R17C48[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s2/F |
15.756 | 0.216 | tNET | RR | 1 | R18C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s1/I0 |
16.442 | 0.686 | tINS | RR | 1 | R18C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1085_s1/F |
16.442 | 0.000 | tNET | RR | 1 | R18C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R18C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1/CLK |
16.927 | -0.044 | tSu | 1 | R18C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_16_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 17 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 9.016, 55.872%; route: 6.831, 42.331%; tC2Q: 0.290, 1.797% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path5
Path Summary:
Slack | 0.548 |
Data Arrival Time | 16.379 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_9_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.487 | 1.625 | tNET | FF | 1 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/I0 |
12.065 | 0.577 | tINS | FR | 5 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/F |
12.285 | 0.221 | tNET | RR | 1 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/I2 |
12.863 | 0.577 | tINS | RR | 2 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/F |
13.080 | 0.217 | tNET | RR | 1 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/I3 |
13.774 | 0.694 | tINS | RF | 4 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/F |
14.101 | 0.327 | tNET | FF | 1 | R7C20[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n101_s2/I3 |
14.678 | 0.577 | tINS | FR | 3 | R7C20[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n101_s2/F |
14.900 | 0.221 | tNET | RR | 1 | R8C20[0][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n100_s2/I1 |
15.477 | 0.577 | tINS | RR | 1 | R8C20[0][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n100_s2/F |
15.693 | 0.216 | tNET | RR | 1 | R9C20[2][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n100_s0/I1 |
16.379 | 0.686 | tINS | RR | 1 | R9C20[2][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n100_s0/F |
16.379 | 0.000 | tNET | RR | 1 | R9C20[2][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R9C20[2][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_9_s1/CLK |
16.927 | -0.044 | tSu | 1 | R9C20[2][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.535, 40.653%; route: 9.250, 57.542%; tC2Q: 0.290, 1.804% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path6
Path Summary:
Slack | 0.570 |
Data Arrival Time | 16.357 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_10_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.487 | 1.625 | tNET | FF | 1 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/I0 |
12.065 | 0.577 | tINS | FR | 5 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/F |
12.285 | 0.221 | tNET | RR | 1 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/I2 |
12.863 | 0.577 | tINS | RR | 2 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/F |
13.080 | 0.217 | tNET | RR | 1 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/I3 |
13.774 | 0.694 | tINS | RF | 4 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/F |
14.101 | 0.327 | tNET | FF | 1 | R7C20[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n101_s2/I3 |
14.667 | 0.566 | tINS | FF | 3 | R7C20[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n101_s2/F |
15.200 | 0.533 | tNET | FF | 1 | R8C19[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n99_s1/I2 |
15.778 | 0.577 | tINS | FR | 1 | R8C19[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n99_s1/F |
15.780 | 0.002 | tNET | RR | 1 | R8C19[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n99_s0/I0 |
16.357 | 0.577 | tINS | RR | 1 | R8C19[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n99_s0/F |
16.357 | 0.000 | tNET | RR | 1 | R8C19[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R8C19[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_10_s1/CLK |
16.927 | -0.044 | tSu | 1 | R8C19[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.415, 39.962%; route: 9.348, 58.232%; tC2Q: 0.290, 1.807% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path7
Path Summary:
Slack | 0.589 |
Data Arrival Time | 16.338 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.808 | 1.946 | tNET | FF | 1 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/I0 |
12.502 | 0.694 | tINS | FF | 5 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/F |
12.829 | 0.327 | tNET | FF | 1 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/I2 |
13.293 | 0.464 | tINS | FF | 2 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/F |
13.517 | 0.224 | tNET | FF | 1 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/I3 |
14.084 | 0.566 | tINS | FF | 4 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/F |
14.100 | 0.016 | tNET | FF | 1 | R16C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n101_s2/I3 |
14.564 | 0.464 | tINS | FF | 3 | R16C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n101_s2/F |
15.073 | 0.509 | tNET | FF | 1 | R17C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n99_s1/I2 |
15.759 | 0.686 | tINS | FR | 1 | R17C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n99_s1/F |
15.761 | 0.002 | tNET | RR | 1 | R17C3[1][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n99_s0/I0 |
16.338 | 0.577 | tINS | RR | 1 | R17C3[1][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n99_s0/F |
16.338 | 0.000 | tNET | RR | 1 | R17C3[1][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R17C3[1][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1/CLK |
16.927 | -0.044 | tSu | 1 | R17C3[1][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.296, 39.268%; route: 9.448, 58.923%; tC2Q: 0.290, 1.809% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path8
Path Summary:
Slack | 0.698 |
Data Arrival Time | 16.229 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.805 | 1.175 | tNET | FF | 1 | R18C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s5/I1 |
14.383 | 0.577 | tINS | FR | 1 | R18C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s5/F |
14.384 | 0.002 | tNET | RR | 1 | R18C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s4/I0 |
14.962 | 0.577 | tINS | RR | 1 | R18C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s4/F |
14.964 | 0.002 | tNET | RR | 1 | R18C48[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s2/I1 |
15.650 | 0.686 | tINS | RR | 1 | R18C48[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s2/F |
15.652 | 0.002 | tNET | RR | 1 | R18C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s1/I0 |
16.229 | 0.577 | tINS | RR | 1 | R18C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1086_s1/F |
16.229 | 0.000 | tNET | RR | 1 | R18C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R18C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1/CLK |
16.927 | -0.044 | tSu | 1 | R18C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_15_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 17 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 9.021, 56.650%; route: 6.613, 41.529%; tC2Q: 0.290, 1.821% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path9
Path Summary:
Slack | 0.753 |
Data Arrival Time | 7.840 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 1 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 4 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
1.128 | 0.533 | tNET | FF | 1 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
1.774 | 0.646 | tINS | FF | 3 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
2.094 | 0.320 | tNET | FF | 1 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
2.558 | 0.464 | tINS | FF | 6 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
3.087 | 0.529 | tNET | FF | 1 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
3.664 | 0.577 | tINS | FR | 2 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
3.667 | 0.003 | tNET | RR | 1 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
4.314 | 0.646 | tINS | RF | 2 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
4.836 | 0.522 | tNET | FF | 2 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
5.522 | 0.686 | tINS | FR | 1 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
5.522 | 0.000 | tNET | RR | 2 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
5.566 | 0.044 | tINS | RF | 1 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
5.566 | 0.000 | tNET | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
5.610 | 0.044 | tINS | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
6.512 | 0.902 | tNET | FF | 1 | R22C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0 |
7.158 | 0.646 | tINS | FF | 2 | R22C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F |
7.840 | 0.682 | tNET | FF | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 8.333 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 3.754, 49.817%; route: 3.492, 46.335%; tC2Q: 0.290, 3.848% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path10
Path Summary:
Slack | 0.753 |
Data Arrival Time | 7.840 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0 |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 1 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 4 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
1.128 | 0.533 | tNET | FF | 1 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
1.774 | 0.646 | tINS | FF | 3 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
2.094 | 0.320 | tNET | FF | 1 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
2.558 | 0.464 | tINS | FF | 6 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
3.087 | 0.529 | tNET | FF | 1 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
3.664 | 0.577 | tINS | FR | 2 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
3.667 | 0.003 | tNET | RR | 1 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
4.314 | 0.646 | tINS | RF | 2 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
4.836 | 0.522 | tNET | FF | 2 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
5.522 | 0.686 | tINS | FR | 1 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
5.522 | 0.000 | tNET | RR | 2 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
5.566 | 0.044 | tINS | RF | 1 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
5.566 | 0.000 | tNET | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
5.610 | 0.044 | tINS | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
6.512 | 0.902 | tNET | FF | 1 | R22C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/I0 |
7.158 | 0.646 | tINS | FF | 2 | R22C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/w_empty_s0/F |
7.840 | 0.682 | tNET | FF | 1 | R22C53[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C53[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C53[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q_empty_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 8.333 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 3.754, 49.817%; route: 3.492, 46.335%; tC2Q: 0.290, 3.848% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path11
Path Summary:
Slack | 0.756 |
Data Arrival Time | 16.172 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.808 | 1.946 | tNET | FF | 1 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/I0 |
12.502 | 0.694 | tINS | FF | 5 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/F |
12.829 | 0.327 | tNET | FF | 1 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/I2 |
13.293 | 0.464 | tINS | FF | 2 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/F |
13.517 | 0.224 | tNET | FF | 1 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/I3 |
14.084 | 0.566 | tINS | FF | 4 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/F |
14.100 | 0.016 | tNET | FF | 1 | R16C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n101_s2/I3 |
14.564 | 0.464 | tINS | FF | 3 | R16C3[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n101_s2/F |
14.782 | 0.219 | tNET | FF | 1 | R17C3[2][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n100_s2/I1 |
15.246 | 0.464 | tINS | FF | 1 | R17C3[2][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n100_s2/F |
15.459 | 0.213 | tNET | FF | 1 | R17C4[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n100_s0/I1 |
16.172 | 0.712 | tINS | FR | 1 | R17C4[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n100_s0/F |
16.172 | 0.000 | tNET | RR | 1 | R17C4[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R17C4[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1/CLK |
16.927 | -0.044 | tSu | 1 | R17C4[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.209, 39.129%; route: 9.369, 59.043%; tC2Q: 0.290, 1.828% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path12
Path Summary:
Slack | 0.810 |
Data Arrival Time | 16.117 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.665 | 1.802 | tNET | FF | 1 | R13C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n75_s0/I0 |
12.129 | 0.464 | tINS | FF | 5 | R13C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n75_s0/F |
12.656 | 0.527 | tNET | FF | 1 | R16C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n106_s2/I3 |
13.223 | 0.566 | tINS | FF | 4 | R16C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n106_s2/F |
13.239 | 0.016 | tNET | FF | 1 | R16C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n103_s2/I3 |
13.817 | 0.577 | tINS | FR | 4 | R16C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n103_s2/F |
14.035 | 0.219 | tNET | RR | 1 | R15C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s2/I3 |
14.748 | 0.712 | tINS | RR | 2 | R15C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s2/F |
14.751 | 0.003 | tNET | RR | 1 | R15C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n99_s1/I1 |
15.438 | 0.686 | tINS | RR | 1 | R15C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n99_s1/F |
15.653 | 0.216 | tNET | RR | 1 | R14C11[1][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n99_s0/I0 |
16.117 | 0.464 | tINS | RF | 1 | R14C11[1][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n99_s0/F |
16.117 | 0.000 | tNET | FF | 1 | R14C11[1][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R14C11[1][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1/CLK |
16.927 | -0.044 | tSu | 1 | R14C11[1][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.315, 39.936%; route: 9.208, 58.230%; tC2Q: 0.290, 1.834% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path13
Path Summary:
Slack | 0.974 |
Data Arrival Time | 15.954 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0 |
To | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R8C39[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 35 | R8C39[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_ctlparam_7_s0/Q |
2.408 | 1.814 | tNET | FF | 1 | R8C32[3][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1807_s12/I1 |
2.872 | 0.464 | tINS | FF | 3 | R8C32[3][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1807_s12/F |
3.102 | 0.230 | tNET | FF | 1 | R8C31[2][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_11_s10/I2 |
3.668 | 0.566 | tINS | FF | 9 | R8C31[2][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_11_s10/F |
4.532 | 0.864 | tNET | FF | 1 | R6C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/descrom_start_15_s16/I3 |
5.098 | 0.566 | tINS | FF | 21 | R6C29[0][A] | u_usb_device_controller_top/u_usb_device_controller/descrom_start_15_s16/F |
6.834 | 1.736 | tNET | FF | 1 | R14C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_1_s10/I0 |
7.528 | 0.694 | tINS | FF | 2 | R14C28[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_1_s10/F |
8.485 | 0.956 | tNET | FF | 1 | R8C30[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_1_s17/I2 |
9.178 | 0.694 | tINS | FF | 1 | R8C30[3][A] | u_usb_device_controller_top/u_usb_device_controller/usbc_dsclen_1_s17/F |
9.998 | 0.820 | tNET | FF | 2 | R6C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1470_s0/I1 |
10.711 | 0.712 | tINS | FR | 1 | R6C31[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1470_s0/COUT |
10.711 | 0.000 | tNET | RR | 2 | R6C31[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1471_s0/CIN |
10.755 | 0.044 | tINS | RF | 1 | R6C31[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1471_s0/COUT |
10.755 | 0.000 | tNET | FF | 2 | R6C31[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1472_s0/CIN |
10.799 | 0.044 | tINS | FF | 1 | R6C31[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1472_s0/COUT |
10.799 | 0.000 | tNET | FF | 2 | R6C31[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1473_s0/CIN |
10.843 | 0.044 | tINS | FF | 1 | R6C31[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1473_s0/COUT |
10.843 | 0.000 | tNET | FF | 2 | R6C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1474_s0/CIN |
10.887 | 0.044 | tINS | FF | 1 | R6C32[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1474_s0/COUT |
10.887 | 0.000 | tNET | FF | 2 | R6C32[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1475_s0/CIN |
10.931 | 0.044 | tINS | FF | 1 | R6C32[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1475_s0/COUT |
10.931 | 0.000 | tNET | FF | 2 | R6C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1476_s0/CIN |
10.975 | 0.044 | tINS | FF | 1 | R6C32[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1476_s0/COUT |
10.975 | 0.000 | tNET | FF | 2 | R6C32[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1477_s0/CIN |
11.019 | 0.044 | tINS | FF | 1 | R6C32[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1477_s0/COUT |
11.019 | 0.000 | tNET | FF | 2 | R6C32[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1478_s0/CIN |
11.063 | 0.044 | tINS | FF | 1 | R6C32[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1478_s0/COUT |
11.063 | 0.000 | tNET | FF | 2 | R6C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1479_s0/CIN |
11.107 | 0.044 | tINS | FF | 1 | R6C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1479_s0/COUT |
11.107 | 0.000 | tNET | FF | 2 | R6C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1480_s0/CIN |
11.151 | 0.044 | tINS | FF | 1 | R6C33[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1480_s0/COUT |
11.151 | 0.000 | tNET | FF | 2 | R6C33[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1481_s0/CIN |
11.195 | 0.044 | tINS | FF | 1 | R6C33[0][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1481_s0/COUT |
11.195 | 0.000 | tNET | FF | 2 | R6C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1482_s0/CIN |
11.239 | 0.044 | tINS | FF | 1 | R6C33[1][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1482_s0/COUT |
11.239 | 0.000 | tNET | FF | 2 | R6C33[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1483_s0/CIN |
11.283 | 0.044 | tINS | FF | 1 | R6C33[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1483_s0/COUT |
11.283 | 0.000 | tNET | FF | 2 | R6C33[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1484_s0/CIN |
11.327 | 0.044 | tINS | FF | 5 | R6C33[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1484_s0/COUT |
12.453 | 1.126 | tNET | FF | 1 | R7C32[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1729_s19/I1 |
13.019 | 0.566 | tINS | FF | 3 | R7C32[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1729_s19/F |
13.734 | 0.715 | tNET | FF | 1 | R7C34[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s48/I3 |
14.446 | 0.712 | tINS | FR | 1 | R7C34[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s48/F |
14.448 | 0.002 | tNET | RR | 1 | R7C34[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s43/I0 |
15.026 | 0.577 | tINS | RR | 1 | R7C34[2][A] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s43/F |
15.241 | 0.216 | tNET | RR | 1 | R7C35[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s40/I2 |
15.954 | 0.712 | tINS | RR | 1 | R7C35[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/n1746_s40/F |
15.954 | 0.000 | tNET | RR | 1 | R7C35[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R7C35[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2/CLK |
16.927 | -0.044 | tSu | 1 | R7C35[1][B] | u_usb_device_controller_top/u_usb_device_controller/usb_control_inst/s_state_9_s2 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 13 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.881, 43.969%; route: 8.479, 54.177%; tC2Q: 0.290, 1.853% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path14
Path Summary:
Slack | 1.088 |
Data Arrival Time | 15.839 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.846 | 1.216 | tNET | FF | 1 | R20C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s11/I2 |
14.413 | 0.566 | tINS | FF | 1 | R20C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s11/F |
14.413 | 0.000 | tNET | FF | 1 | R20C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s10/I0 |
14.541 | 0.129 | tINS | FF | 1 | R20C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s10/O |
14.541 | 0.000 | tNET | FF | 1 | R20C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s5/I1 |
14.670 | 0.129 | tINS | FF | 1 | R20C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1012_s5/O |
14.986 | 0.316 | tNET | FF | 1 | R20C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1088_s7/I0 |
15.699 | 0.712 | tINS | FR | 1 | R20C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1088_s7/F |
15.699 | 0.000 | tNET | RR | 1 | R20C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1088_s4/I1 |
15.830 | 0.131 | tINS | RR | 1 | R20C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1088_s4/O |
15.839 | 0.009 | tNET | RR | 1 | R20C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R20C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1/CLK |
16.927 | -0.044 | tSu | 1 | R20C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 8.270, 53.237%; route: 6.975, 44.896%; tC2Q: 0.290, 1.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path15
Path Summary:
Slack | 1.121 |
Data Arrival Time | 15.807 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.814 | 1.184 | tNET | FF | 1 | R21C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s11/I2 |
14.381 | 0.566 | tINS | FF | 1 | R21C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s11/F |
14.381 | 0.000 | tNET | FF | 1 | R21C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s10/I0 |
14.509 | 0.129 | tINS | FF | 1 | R21C48[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s10/O |
14.509 | 0.000 | tNET | FF | 1 | R21C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s5/I1 |
14.638 | 0.129 | tINS | FF | 1 | R21C48[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1016_s5/O |
14.954 | 0.316 | tNET | FF | 1 | R21C49[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1092_s7/I0 |
15.667 | 0.712 | tINS | FR | 1 | R21C49[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1092_s7/F |
15.667 | 0.000 | tNET | RR | 1 | R21C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1092_s4/I1 |
15.798 | 0.131 | tINS | RR | 1 | R21C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1092_s4/O |
15.807 | 0.009 | tNET | RR | 1 | R21C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R21C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1/CLK |
16.927 | -0.044 | tSu | 1 | R21C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 8.270, 53.347%; route: 6.942, 44.782%; tC2Q: 0.290, 1.871% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path16
Path Summary:
Slack | 1.165 |
Data Arrival Time | 7.428 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2 |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 8 | IOT39[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/PCLK |
1.098 | 0.794 | tC2Q | RF | 5 | IOT39[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/Q4 |
2.304 | 1.206 | tNET | FF | 1 | R6C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s22/I3 |
2.950 | 0.646 | tINS | FF | 1 | R6C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s22/F |
3.447 | 0.496 | tNET | FF | 1 | R6C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s16/I0 |
4.024 | 0.577 | tINS | FR | 1 | R6C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s16/F |
4.026 | 0.002 | tNET | RR | 1 | R6C43[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/I3 |
4.592 | 0.566 | tINS | RF | 5 | R6C43[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/F |
5.109 | 0.517 | tNET | FF | 1 | R8C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/I0 |
5.573 | 0.464 | tINS | FF | 2 | R8C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s4/F |
5.584 | 0.011 | tNET | FF | 1 | R8C43[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/I2 |
6.161 | 0.577 | tINS | FR | 1 | R8C43[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s1/F |
6.163 | 0.002 | tNET | RR | 1 | R8C43[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s15/I3 |
6.740 | 0.577 | tINS | RR | 1 | R8C43[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n264_s15/F |
6.742 | 0.002 | tNET | RR | 1 | R8C43[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n332_s3/I0 |
7.428 | 0.686 | tINS | RR | 1 | R8C43[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n332_s3/F |
7.428 | 0.000 | tNET | RR | 1 | R8C43[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R8C43[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2/CLK |
8.593 | -0.044 | tSu | 1 | R8C43[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/dru_locked_s2 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 8.333 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 4.095, 57.480%; route: 2.235, 31.379%; tC2Q: 0.794, 11.142% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path17
Path Summary:
Slack | 1.168 |
Data Arrival Time | 15.760 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1011_s14/I1 |
11.514 | 0.646 | tINS | FF | 5 | R17C49[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1011_s14/F |
12.060 | 0.546 | tNET | FF | 1 | R17C46[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n973_s6/I3 |
12.524 | 0.464 | tINS | FF | 15 | R17C46[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n973_s6/F |
13.687 | 1.163 | tNET | FF | 1 | R20C49[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s14/I2 |
14.333 | 0.646 | tINS | FF | 1 | R20C49[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s14/F |
14.333 | 0.000 | tNET | FF | 1 | R20C49[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s9/I1 |
14.462 | 0.129 | tINS | FF | 1 | R20C49[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s9/O |
14.462 | 0.000 | tNET | FF | 1 | R20C49[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s5/I0 |
14.591 | 0.129 | tINS | FF | 1 | R20C49[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1019_s5/O |
14.907 | 0.316 | tNET | FF | 1 | R20C49[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1095_s7/I0 |
15.620 | 0.712 | tINS | FR | 1 | R20C49[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1095_s7/F |
15.620 | 0.000 | tNET | RR | 1 | R20C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1095_s4/I1 |
15.751 | 0.131 | tINS | RR | 1 | R20C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1095_s4/O |
15.760 | 0.009 | tNET | RR | 1 | R20C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R20C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1/CLK |
16.927 | -0.044 | tSu | 1 | R20C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 8.350, 54.027%; route: 6.815, 44.097%; tC2Q: 0.290, 1.876% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path18
Path Summary:
Slack | 1.233 |
Data Arrival Time | 15.695 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.804 | 1.174 | tNET | FF | 1 | R21C49[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s11/I2 |
14.268 | 0.464 | tINS | FF | 1 | R21C49[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s11/F |
14.268 | 0.000 | tNET | FF | 1 | R21C49[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s10/I0 |
14.397 | 0.129 | tINS | FF | 1 | R21C49[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s10/O |
14.397 | 0.000 | tNET | FF | 1 | R21C49[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s5/I1 |
14.526 | 0.129 | tINS | FF | 1 | R21C49[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1022_s5/O |
14.842 | 0.316 | tNET | FF | 1 | R21C49[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1098_s7/I0 |
15.554 | 0.712 | tINS | FR | 1 | R21C49[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1098_s7/F |
15.554 | 0.000 | tNET | RR | 1 | R21C49[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1098_s4/I1 |
15.686 | 0.131 | tINS | RR | 1 | R21C49[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1098_s4/O |
15.695 | 0.009 | tNET | RR | 1 | R21C49[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R21C49[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1/CLK |
16.927 | -0.044 | tSu | 1 | R21C49[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 8.168, 53.071%; route: 6.933, 45.045%; tC2Q: 0.290, 1.884% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path19
Path Summary:
Slack | 1.250 |
Data Arrival Time | 15.678 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_9_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.665 | 1.802 | tNET | FF | 1 | R13C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n75_s0/I0 |
12.129 | 0.464 | tINS | FF | 5 | R13C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n75_s0/F |
12.656 | 0.527 | tNET | FF | 1 | R16C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n106_s2/I3 |
13.223 | 0.566 | tINS | FF | 4 | R16C11[3][A] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n106_s2/F |
13.239 | 0.016 | tNET | FF | 1 | R16C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n103_s2/I3 |
13.817 | 0.577 | tINS | FR | 4 | R16C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n103_s2/F |
14.035 | 0.219 | tNET | RR | 1 | R15C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s2/I3 |
14.748 | 0.712 | tINS | RR | 2 | R15C11[3][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s2/F |
14.965 | 0.217 | tNET | RR | 1 | R15C10[0][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s0/I2 |
15.678 | 0.712 | tINS | RR | 1 | R15C10[0][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/n100_s0/F |
15.678 | 0.000 | tNET | RR | 1 | R15C10[0][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_9_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R15C10[0][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_9_s1/CLK |
16.927 | -0.044 | tSu | 1 | R15C10[0][B] | usb_fifo/usb_tx_buf_ep2/sync_tx_pkt_fifo/rp_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 5.878, 38.231%; route: 9.206, 59.883%; tC2Q: 0.290, 1.886% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path20
Path Summary:
Slack | 1.258 |
Data Arrival Time | 15.669 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_6_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.808 | 1.946 | tNET | FF | 1 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/I0 |
12.502 | 0.694 | tINS | FF | 5 | R14C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n75_s0/F |
12.829 | 0.327 | tNET | FF | 1 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/I2 |
13.293 | 0.464 | tINS | FF | 2 | R16C4[3][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n107_s2/F |
13.517 | 0.224 | tNET | FF | 1 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/I3 |
14.084 | 0.566 | tINS | FF | 4 | R16C3[1][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n104_s2/F |
14.319 | 0.235 | tNET | FF | 1 | R16C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n103_s2/I1 |
14.783 | 0.464 | tINS | FF | 1 | R16C4[3][A] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n103_s2/F |
15.092 | 0.309 | tNET | FF | 1 | R17C4[0][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n103_s0/I1 |
15.669 | 0.577 | tINS | FR | 1 | R17C4[0][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/n103_s0/F |
15.669 | 0.000 | tNET | RR | 1 | R17C4[0][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R17C4[0][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_6_s1/CLK |
16.927 | -0.044 | tSu | 1 | R17C4[0][B] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/rp_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 5.610, 36.512%; route: 9.465, 61.601%; tC2Q: 0.290, 1.887% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path21
Path Summary:
Slack | 1.265 |
Data Arrival Time | 7.329 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1 |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 8 | IOT39[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/PCLK |
1.098 | 0.794 | tC2Q | RF | 5 | IOT39[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/uut_ides8_b/Q4 |
2.304 | 1.206 | tNET | FF | 1 | R6C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s22/I3 |
2.950 | 0.646 | tINS | FF | 1 | R6C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s22/F |
3.447 | 0.496 | tNET | FF | 1 | R6C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s16/I0 |
4.024 | 0.577 | tINS | FR | 1 | R6C43[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s16/F |
4.026 | 0.002 | tNET | RR | 1 | R6C43[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/I3 |
4.592 | 0.566 | tINS | RF | 5 | R6C43[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n327_s11/F |
5.109 | 0.517 | tNET | FF | 1 | R8C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/I2 |
5.687 | 0.577 | tINS | FR | 1 | R8C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s11/F |
5.688 | 0.002 | tNET | RR | 1 | R8C43[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/I2 |
6.401 | 0.712 | tINS | RR | 1 | R8C43[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s10/F |
6.616 | 0.216 | tNET | RR | 1 | R9C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/I2 |
7.329 | 0.712 | tINS | RR | 1 | R9C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/n328_s9/F |
7.329 | 0.000 | tNET | RR | 1 | R9C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R9C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1/CLK |
8.593 | -0.044 | tSu | 1 | R9C43[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/DRU_500M_Top/u_dru_500m_logic/status_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 8.333 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 3.793, 53.988%; route: 2.438, 34.713%; tC2Q: 0.794, 11.299% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path22
Path Summary:
Slack | 1.270 |
Data Arrival Time | 15.658 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_6_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.487 | 1.625 | tNET | FF | 1 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/I0 |
12.065 | 0.577 | tINS | FR | 5 | R7C20[1][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n75_s0/F |
12.285 | 0.221 | tNET | RR | 1 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/I2 |
12.863 | 0.577 | tINS | RR | 2 | R7C19[0][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n107_s2/F |
13.080 | 0.217 | tNET | RR | 1 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/I3 |
13.774 | 0.694 | tINS | RF | 4 | R7C18[3][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n104_s2/F |
14.301 | 0.527 | tNET | FF | 1 | R8C19[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n103_s2/I1 |
15.014 | 0.712 | tINS | FR | 1 | R8C19[2][B] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n103_s2/F |
15.194 | 0.180 | tNET | RR | 1 | R8C19[1][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n103_s0/I1 |
15.658 | 0.464 | tINS | RF | 1 | R8C19[1][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/n103_s0/F |
15.658 | 0.000 | tNET | FF | 1 | R8C19[1][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_6_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R8C19[1][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_6_s1/CLK |
16.927 | -0.044 | tSu | 1 | R8C19[1][A] | usb_fifo/usb_tx_buf_ep5/sync_tx_pkt_fifo/rp_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 5.870, 38.232%; route: 9.194, 59.879%; tC2Q: 0.290, 1.889% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path23
Path Summary:
Slack | 1.297 |
Data Arrival Time | 7.297 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0 |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.304 | 0.304 | tNET | RR | 1 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 4 | R22C53[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/q2_empty_s0/Q |
1.128 | 0.533 | tNET | FF | 1 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/I0 |
1.774 | 0.646 | tINS | FF | 3 | R23C51[3][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n28_s0/F |
2.094 | 0.320 | tNET | FF | 1 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/I3 |
2.558 | 0.464 | tINS | FF | 6 | R25C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_3_s4/F |
3.087 | 0.529 | tNET | FF | 1 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/I1 |
3.664 | 0.577 | tINS | FR | 2 | R26C51[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_next_4_s3/F |
3.667 | 0.003 | tNET | RR | 1 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/I2 |
4.314 | 0.646 | tINS | RF | 2 | R26C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rgraynext_2_s1/F |
4.836 | 0.522 | tNET | FF | 2 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/I0 |
5.522 | 0.686 | tINS | FR | 1 | R24C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n163_s0/COUT |
5.522 | 0.000 | tNET | RR | 2 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/CIN |
5.566 | 0.044 | tINS | RF | 1 | R24C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n164_s0/COUT |
5.566 | 0.000 | tNET | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/CIN |
5.610 | 0.044 | tINS | FF | 2 | R24C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/n165_s0/COUT |
6.719 | 1.109 | tNET | FF | 1 | R22C53[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n648_s0/I2 |
7.297 | 0.577 | tINS | FR | 1 | R22C53[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/n648_s0/F |
7.297 | 0.000 | tNET | RR | 1 | R22C53[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C53[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C53[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/data_out_en_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 8.333 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 3.685, 52.705%; route: 3.017, 43.148%; tC2Q: 0.290, 4.147% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path24
Path Summary:
Slack | 1.319 |
Data Arrival Time | 15.608 |
Data Required Time | 16.927 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/CLK |
0.594 | 0.290 | tC2Q | RF | 6 | R20C45[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_5_s1/Q |
1.463 | 0.869 | tNET | FF | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/I0 |
2.041 | 0.577 | tINS | FR | 1 | R21C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s2/F |
2.042 | 0.002 | tNET | RR | 1 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/I0 |
2.729 | 0.686 | tINS | RR | 2 | R21C50[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n611_s1/F |
2.948 | 0.220 | tNET | RR | 1 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/I1 |
3.412 | 0.464 | tINS | RF | 9 | R20C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1175_s10/F |
4.255 | 0.843 | tNET | FF | 1 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/I2 |
4.719 | 0.464 | tINS | FF | 4 | R17C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s3/F |
5.238 | 0.519 | tNET | FF | 1 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/I2 |
5.950 | 0.712 | tINS | FR | 9 | R17C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s2/F |
5.957 | 0.007 | tNET | RR | 1 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/I0 |
6.421 | 0.464 | tINS | RF | 4 | R17C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_1_s1/F |
6.741 | 0.320 | tNET | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/I3 |
7.204 | 0.464 | tINS | FF | 1 | R17C50[3][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/w_offset_inc_0_s2/F |
8.039 | 0.835 | tNET | FF | 2 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/I1 |
8.503 | 0.464 | tINS | FF | 1 | R17C44[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n593_s/COUT |
8.503 | 0.000 | tNET | FF | 2 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/CIN |
8.547 | 0.044 | tINS | FF | 1 | R17C44[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n592_s/COUT |
8.547 | 0.000 | tNET | FF | 2 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/CIN |
9.134 | 0.587 | tINS | FF | 4 | R17C44[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n591_s/SUM |
9.798 | 0.664 | tNET | FF | 1 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/I1 |
10.365 | 0.566 | tINS | FF | 2 | R17C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s8/F |
10.868 | 0.503 | tNET | FF | 1 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/I1 |
11.514 | 0.646 | tINS | FF | 19 | R17C49[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s6/F |
12.167 | 0.652 | tNET | FF | 1 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/I3 |
12.630 | 0.464 | tINS | FF | 18 | R17C45[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n935_s10/F |
13.814 | 1.184 | tNET | FF | 1 | R21C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s11/I2 |
14.278 | 0.464 | tINS | FF | 1 | R21C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s11/F |
14.278 | 0.000 | tNET | FF | 1 | R21C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s10/I0 |
14.407 | 0.129 | tINS | FF | 1 | R21C48[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s10/O |
14.407 | 0.000 | tNET | FF | 1 | R21C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s5/I1 |
14.536 | 0.129 | tINS | FF | 1 | R21C48[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1013_s5/O |
14.756 | 0.220 | tNET | FF | 1 | R20C48[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1089_s7/I0 |
15.468 | 0.712 | tINS | FR | 1 | R20C48[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1089_s7/F |
15.468 | 0.000 | tNET | RR | 1 | R20C48[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1089_s4/I1 |
15.600 | 0.131 | tINS | RR | 1 | R20C48[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/n1089_s4/O |
15.608 | 0.009 | tNET | RR | 1 | R20C48[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R20C48[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1/CLK |
16.927 | -0.044 | tSu | 1 | R20C48[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/q_w_data_19_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 8.168, 53.369%; route: 6.847, 44.736%; tC2Q: 0.290, 1.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path25
Path Summary:
Slack | 1.343 |
Data Arrival Time | 15.584 |
Data Required Time | 16.927 |
From | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0 |
To | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_7_s1 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.304 | 0.304 | tNET | RR | 1 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/CLK |
0.594 | 0.290 | tC2Q | RF | 34 | R23C39[0][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/s_endpt_1_s0/Q |
2.862 | 2.268 | tNET | FF | 1 | R17C27[3][B] | usb_txdat_7_s2/I1 |
3.326 | 0.464 | tINS | FF | 23 | R17C27[3][B] | usb_txdat_7_s2/F |
4.891 | 1.565 | tNET | FF | 1 | R30C33[0][B] | n204_s0/I1 |
5.585 | 0.694 | tINS | FF | 10 | R30C33[0][B] | n204_s0/F |
7.008 | 1.423 | tNET | FF | 1 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/I3 |
7.472 | 0.464 | tINS | FF | 3 | R11C34[0][B] | u_usb_device_controller_top/u_usb_device_controller/u_usb_packet/n622_s42/F |
8.636 | 1.164 | tNET | FF | 1 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/I1 |
9.213 | 0.577 | tINS | FR | 2 | R22C32[2][B] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s0/F |
9.216 | 0.003 | tNET | RR | 1 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/I0 |
9.863 | 0.646 | tINS | RF | 23 | R22C32[3][A] | u_usb_device_controller_top/u_usb_device_controller/usb_transact_inst/txpop_o_d_s/F |
11.131 | 1.269 | tNET | FF | 1 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/I0 |
11.777 | 0.646 | tINS | FF | 5 | R15C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n75_s0/F |
12.601 | 0.823 | tNET | FF | 1 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/I2 |
13.313 | 0.712 | tINS | FR | 2 | R16C18[3][A] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n107_s2/F |
13.317 | 0.003 | tNET | RR | 1 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/I3 |
13.883 | 0.566 | tINS | RF | 4 | R16C18[3][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n104_s2/F |
14.210 | 0.327 | tNET | FF | 1 | R16C16[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n102_s1/I2 |
14.896 | 0.686 | tINS | FR | 1 | R16C16[2][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n102_s1/F |
14.898 | 0.002 | tNET | RR | 1 | R16C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n102_s0/I0 |
15.584 | 0.686 | tINS | RR | 1 | R16C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/n102_s0/F |
15.584 | 0.000 | tNET | RR | 1 | R16C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_7_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
16.667 | 16.667 | active clock edge time | ||||
16.667 | 0.000 | clk_60 | ||||
16.667 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
16.971 | 0.304 | tNET | RR | 1 | R16C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_7_s1/CLK |
16.927 | -0.044 | tSu | 1 | R16C16[0][B] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/rp_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 16.667 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Arrival Data Path Delay | cell: 6.143, 40.200%; route: 8.847, 57.902%; tC2Q: 0.290, 1.898% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.103 |
Data Arrival Time | 0.645 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0 |
To | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C20[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 4 | R27C20[1][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_6_s0/Q |
0.645 | 0.163 | tNET | FF | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.163, 39.420%; tC2Q: 0.251, 60.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path2
Path Summary:
Slack | 0.103 |
Data Arrival Time | 0.645 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0 |
To | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C20[1][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 4 | R27C20[1][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_3_s0/Q |
0.645 | 0.163 | tNET | FF | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.163, 39.420%; tC2Q: 0.251, 60.580% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path3
Path Summary:
Slack | 0.249 |
Data Arrival Time | 0.791 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C6[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C6[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/Q |
0.791 | 0.308 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.308, 54.955%; tC2Q: 0.252, 45.045% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path4
Path Summary:
Slack | 0.249 |
Data Arrival Time | 0.791 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C6[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C6[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/Q |
0.791 | 0.308 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.308, 54.955%; tC2Q: 0.252, 45.045% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path5
Path Summary:
Slack | 0.257 |
Data Arrival Time | 0.799 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0 |
To | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C20[2][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 4 | R27C20[2][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_0_s0/Q |
0.799 | 0.316 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[0] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.316, 55.591%; tC2Q: 0.252, 44.409% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path6
Path Summary:
Slack | 0.264 |
Data Arrival Time | 0.641 |
Data Required Time | 0.378 |
From | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/rp_8_s0 |
To | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R29C11[0][B] | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/rp_8_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 6 | R29C11[0][B] | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/rp_8_s0/Q |
0.641 | 0.159 | tNET | RR | 1 | BSRAM_R28[3] | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/RAM_RAM_0_0_s/ADB[11] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[3] | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/RAM_RAM_0_0_s/CLKB |
0.378 | 0.148 | tHld | 1 | BSRAM_R28[3] | usb_fifo/usb_rx_buf_ep2/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.159, 38.581%; tC2Q: 0.252, 61.419% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path7
Path Summary:
Slack | 0.267 |
Data Arrival Time | 1.334 |
Data Required Time | 1.067 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_7_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Launch Clk | jtag_tck:[R] |
Latch Clk | jtag_tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | jtag_tck | ||||
0.000 | 0.000 | tCL | RR | 319 | R33C34[3][B] | u_usb_uart_config/jtag_tck_Z_s/F |
0.756 | 0.756 | tNET | RR | 1 | R47C12[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_7_s1/CLK |
1.008 | 0.252 | tC2Q | RR | 1 | R47C12[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_7_s1/Q |
1.334 | 0.325 | tNET | RR | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | jtag_tck | ||||
0.000 | 0.000 | tCL | RR | 319 | R33C34[3][B] | u_usb_uart_config/jtag_tck_Z_s/F |
0.756 | 0.756 | tNET | RR | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
1.067 | 0.311 | tHld | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.756, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.325, 56.314%; tC2Q: 0.252, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.756, 100.000% |
Path8
Path Summary:
Slack | 0.267 |
Data Arrival Time | 1.334 |
Data Required Time | 1.067 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_6_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Launch Clk | jtag_tck:[R] |
Latch Clk | jtag_tck:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | jtag_tck | ||||
0.000 | 0.000 | tCL | RR | 319 | R33C34[3][B] | u_usb_uart_config/jtag_tck_Z_s/F |
0.756 | 0.756 | tNET | RR | 1 | R47C12[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_6_s1/CLK |
1.008 | 0.252 | tC2Q | RR | 1 | R47C12[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_data_in_6_s1/Q |
1.334 | 0.325 | tNET | RR | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | jtag_tck | ||||
0.000 | 0.000 | tCL | RR | 319 | R33C34[3][B] | u_usb_uart_config/jtag_tck_Z_s/F |
0.756 | 0.756 | tNET | RR | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
1.067 | 0.311 | tHld | 1 | BSRAM_R46[2] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/Usb_MPB_top_m0/Usb_Data_Decoder_u0/tx_usb_fifo/fifo_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.756, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.325, 56.314%; tC2Q: 0.252, 43.686% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.756, 100.000% |
Path9
Path Summary:
Slack | 0.268 |
Data Arrival Time | 0.810 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C6[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C6[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_7_s0/Q |
0.810 | 0.327 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.327, 56.429%; tC2Q: 0.252, 43.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path10
Path Summary:
Slack | 0.268 |
Data Arrival Time | 0.810 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C6[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C6[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_6_s0/Q |
0.810 | 0.327 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[6] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.327, 56.429%; tC2Q: 0.252, 43.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path11
Path Summary:
Slack | 0.268 |
Data Arrival Time | 0.810 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C4[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C4[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/Q |
0.810 | 0.327 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.327, 56.429%; tC2Q: 0.252, 43.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path12
Path Summary:
Slack | 0.268 |
Data Arrival Time | 0.810 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C4[0][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C4[0][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/Q |
0.810 | 0.327 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.327, 56.429%; tC2Q: 0.252, 43.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path13
Path Summary:
Slack | 0.268 |
Data Arrival Time | 0.810 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_1_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C5[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_1_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C5[2][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_1_s0/Q |
0.810 | 0.327 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[0] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.327, 56.429%; tC2Q: 0.252, 43.571% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path14
Path Summary:
Slack | 0.270 |
Data Arrival Time | 0.811 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_7_s0 |
To | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C21[0][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_7_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 4 | R27C21[0][A] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_7_s0/Q |
0.811 | 0.329 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[7] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.329, 56.544%; tC2Q: 0.252, 43.456% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path15
Path Summary:
Slack | 0.271 |
Data Arrival Time | 0.813 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0 |
To | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C21[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 4 | R27C21[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q |
0.813 | 0.330 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[6] | usb_fifo/usb_rx_buf_ep5/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.330, 56.658%; tC2Q: 0.252, 43.342% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path16
Path Summary:
Slack | 0.283 |
Data Arrival Time | 0.825 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_5_s0 |
To | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R14C22[1][A] | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_5_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R14C22[1][A] | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_5_s0/Q |
0.825 | 0.342 | tNET | RR | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[5] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.342, 57.536%; tC2Q: 0.252, 42.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path17
Path Summary:
Slack | 0.283 |
Data Arrival Time | 0.825 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_4_s0 |
To | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R14C22[0][A] | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_4_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R14C22[0][A] | usb_fifo/usb_tx_buf_ep4/clk_cross_fifo_inst/Q_4_s0/Q |
0.825 | 0.342 | tNET | RR | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/DI[4] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[5] | usb_fifo/usb_tx_buf_ep4/sync_tx_pkt_fifo/RAM_RAM_0_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.342, 57.536%; tC2Q: 0.252, 42.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path18
Path Summary:
Slack | 0.283 |
Data Arrival Time | 0.825 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C4[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C4[1][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_3_s0/Q |
0.825 | 0.342 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[3] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.342, 57.536%; tC2Q: 0.252, 42.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path19
Path Summary:
Slack | 0.283 |
Data Arrival Time | 0.825 |
Data Required Time | 0.542 |
From | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0 |
To | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R8C4[0][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 2 | R8C4[0][A] | usb_fifo/usb_tx_buf_ep3/clk_cross_fifo_inst/Q_2_s0/Q |
0.825 | 0.342 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/DI[2] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R10[1] | usb_fifo/usb_tx_buf_ep3/sync_tx_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.342, 57.536%; tC2Q: 0.252, 42.464% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path20
Path Summary:
Slack | 0.285 |
Data Arrival Time | 0.826 |
Data Required Time | 0.542 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_29_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R38C45[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_29_s1/CLK |
0.483 | 0.252 | tC2Q | RR | 3 | R38C45[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_29_s1/Q |
0.826 | 0.344 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[29] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.344, 57.645%; tC2Q: 0.252, 42.355% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path21
Path Summary:
Slack | 0.286 |
Data Arrival Time | 0.828 |
Data Required Time | 0.542 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_21_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R38C43[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_21_s1/CLK |
0.483 | 0.252 | tC2Q | RR | 4 | R38C43[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_21_s1/Q |
0.828 | 0.345 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[21] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.345, 57.753%; tC2Q: 0.252, 42.247% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path22
Path Summary:
Slack | 0.286 |
Data Arrival Time | 0.828 |
Data Required Time | 0.542 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_17_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R38C43[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_17_s1/CLK |
0.483 | 0.252 | tC2Q | RR | 5 | R38C43[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_17_s1/Q |
0.828 | 0.345 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[17] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.345, 57.753%; tC2Q: 0.252, 42.247% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path23
Path Summary:
Slack | 0.286 |
Data Arrival Time | 0.828 |
Data Required Time | 0.542 |
From | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0 |
To | usb_fifo/usb_rx_buf_ep4/sync_pkt_fifo/RAM_RAM_0_0_s |
Launch Clk | clk_60:[R] |
Latch Clk | clk_60:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | R27C21[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/CLK |
0.483 | 0.252 | tC2Q | RR | 4 | R27C21[0][B] | usb_fifo/usb_rx_buf_ep2/pkt_fifo_wr_data_1_s0/Q |
0.828 | 0.345 | tNET | RR | 1 | BSRAM_R28[5] | usb_fifo/usb_rx_buf_ep4/sync_pkt_fifo/RAM_RAM_0_0_s/DI[1] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_60 | ||||
0.000 | 0.000 | tCL | RR | 2356 | PLL_L[1] | u_pll/rpll_inst/CLKOUTD |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R28[5] | usb_fifo/usb_rx_buf_ep4/sync_pkt_fifo/RAM_RAM_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R28[5] | usb_fifo/usb_rx_buf_ep4/sync_pkt_fifo/RAM_RAM_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.345, 57.753%; tC2Q: 0.252, 42.247% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path24
Path Summary:
Slack | 0.288 |
Data Arrival Time | 0.830 |
Data Required Time | 0.542 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_12_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R36C45[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_12_s1/CLK |
0.483 | 0.252 | tC2Q | RR | 6 | R36C45[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/pwdata_spi_12_s1/Q |
0.830 | 0.347 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/DI[12] |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s/CLKA |
0.542 | 0.311 | tHld | 1 | BSRAM_R46[13] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/mem_mem_0_0_s |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.347, 57.861%; tC2Q: 0.252, 42.139% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path25
Path Summary:
Slack | 0.292 |
Data Arrival Time | 0.641 |
Data Required Time | 0.349 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser8txd |
Launch Clk | clk_120:[R] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R2C40[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R2C40[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/tx_data_2_s0/Q |
0.641 | 0.159 | tNET | FF | 1 | IOT40[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser8txd/D6 |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk_120 | ||||
0.000 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | IOT40[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser8txd/PCLK |
0.349 | 0.119 | tHld | 1 | IOT40[A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/oser8txd |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.159, 38.816%; tC2Q: 0.251, 61.184% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.931 |
Data Arrival Time | 7.158 |
Data Required Time | 8.090 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 8 | BSRAM_R28[13] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/RESETB |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | BSRAM_R28[13] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
8.090 | -0.548 | tSu | 1 | BSRAM_R28[13] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path2
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Empty_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path3
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C52[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path4
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R25C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R25C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0/CLK |
8.593 | -0.044 | tSu | 1 | R25C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_1_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path5
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R26C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R26C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0/CLK |
8.593 | -0.044 | tSu | 1 | R26C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_2_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path6
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R26C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R26C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0/CLK |
8.593 | -0.044 | tSu | 1 | R26C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rptr_3_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path7
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path8
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R24C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R24C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0/CLK |
8.593 | -0.044 | tSu | 1 | R24C53[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_1_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path9
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_2_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path10
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_3_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path11
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq2_wptr_4_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path12
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C52[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path13
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C52[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_1_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path14
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_2_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R21C50[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R21C50[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_2_s0/CLK |
8.593 | -0.044 | tSu | 1 | R21C50[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_2_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path15
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_3_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path16
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.rq1_wptr_4_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path17
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path18
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R23C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R23C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0/CLK |
8.593 | -0.044 | tSu | 1 | R23C51[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_1_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path19
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R24C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R24C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0/CLK |
8.593 | -0.044 | tSu | 1 | R24C51[1][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_2_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path20
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R22C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R22C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0/CLK |
8.593 | -0.044 | tSu | 1 | R22C51[2][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_3_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path21
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R26C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R26C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0/CLK |
8.593 | -0.044 | tSu | 1 | R26C51[0][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_4_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path22
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R26C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R26C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0/CLK |
8.593 | -0.044 | tSu | 1 | R26C51[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_5_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path23
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R7C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R7C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0/CLK |
8.593 | -0.044 | tSu | 1 | R7C52[1][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Full_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path24
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R8C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R8C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0/CLK |
8.593 | -0.044 | tSu | 1 | R8C52[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_0_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Path25
Path Summary:
Slack | 1.435 |
Data Arrival Time | 7.158 |
Data Required Time | 8.593 |
From | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
To | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0 |
Launch Clk | clk_120:[F] |
Latch Clk | clk_120:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
4.170 | 4.170 | active clock edge time | ||||
4.170 | 0.000 | clk_120 | ||||
4.170 | 0.000 | tCL | FF | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | 1 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
4.787 | 0.290 | tC2Q | FF | 46 | R7C53[2][A] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/Q |
7.158 | 2.372 | tNET | FF | 1 | R6C53[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
8.333 | 8.333 | active clock edge time | ||||
8.333 | 0.000 | clk_120 | ||||
8.333 | 0.000 | tCL | RR | 163 | TOPSIDE[0] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.637 | 0.304 | tNET | RR | 1 | R6C53[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0/CLK |
8.593 | -0.044 | tSu | 1 | R6C53[0][B] | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wbin_1_s0 |
Path Statistics:
Clock Skew | -0.023 |
Setup Relationship | 4.163 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.372, 89.105%; tC2Q: 0.290, 10.895% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.304, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.097 |
Data Arrival Time | 1.341 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.341 | 0.313 | tNET | RR | 1 | R41C41[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C41[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C41[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.892%; route: 0.472, 42.485%; tC2Q: 0.251, 22.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path2
Path Summary:
Slack | 1.097 |
Data Arrival Time | 1.341 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.341 | 0.313 | tNET | RR | 1 | R41C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.892%; route: 0.472, 42.485%; tC2Q: 0.251, 22.623% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path3
Path Summary:
Slack | 1.117 |
Data Arrival Time | 1.362 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.362 | 0.334 | tNET | RR | 1 | R39C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R39C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.255%; route: 0.492, 43.535%; tC2Q: 0.251, 22.210% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path4
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wbin_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path5
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path6
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path7
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path8
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path9
Path Summary:
Slack | 1.125 |
Data Arrival Time | 1.369 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.369 | 0.341 | tNET | RR | 1 | R41C42[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C42[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C42[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 34.029%; route: 0.500, 43.907%; tC2Q: 0.251, 22.064% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path10
Path Summary:
Slack | 1.201 |
Data Arrival Time | 1.445 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_7_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.445 | 0.333 | tNET | RR | 1 | R41C52[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C52[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_7_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C52[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 39.505%; route: 0.484, 39.817%; tC2Q: 0.251, 20.678% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path11
Path Summary:
Slack | 1.219 |
Data Arrival Time | 1.463 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.463 | 0.351 | tNET | RR | 1 | R43C52[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R43C52[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R43C52[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 38.930%; route: 0.502, 40.692%; tC2Q: 0.251, 20.378% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path12
Path Summary:
Slack | 1.223 |
Data Arrival Time | 1.467 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.467 | 0.355 | tNET | RR | 1 | R43C53[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R43C53[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R43C53[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 38.812%; route: 0.505, 40.872%; tC2Q: 0.251, 20.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path13
Path Summary:
Slack | 1.223 |
Data Arrival Time | 1.467 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.467 | 0.355 | tNET | RR | 1 | R43C53[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R43C53[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0/CLK |
0.244 | 0.014 | tHld | 1 | R43C53[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq2_rptr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 38.812%; route: 0.505, 40.872%; tC2Q: 0.251, 20.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path14
Path Summary:
Slack | 1.223 |
Data Arrival Time | 1.467 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.467 | 0.355 | tNET | RR | 1 | R43C53[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R43C53[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0/CLK |
0.244 | 0.014 | tHld | 1 | R43C53[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 38.812%; route: 0.505, 40.872%; tC2Q: 0.251, 20.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path15
Path Summary:
Slack | 1.223 |
Data Arrival Time | 1.467 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_6_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/CLK |
0.482 | 0.251 | tC2Q | RF | 2 | R39C51[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/rxf_clr_sync/b_signal_s0/Q |
0.632 | 0.150 | tNET | FF | 1 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/I1 |
1.112 | 0.480 | tINS | FR | 32 | R39C51[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n87_s0/F |
1.467 | 0.355 | tNET | RR | 1 | R43C53[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R43C53[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_6_s0/CLK |
0.244 | 0.014 | tHld | 1 | R43C53[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_rxfifo/wq1_rptr_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.480, 38.812%; route: 0.505, 40.872%; tC2Q: 0.251, 20.316% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path16
Path Summary:
Slack | 1.274 |
Data Arrival Time | 1.518 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.518 | 0.490 | tNET | RR | 1 | R40C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R40C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R40C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 30.097%; route: 0.649, 50.388%; tC2Q: 0.251, 19.515% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path17
Path Summary:
Slack | 1.274 |
Data Arrival Time | 1.518 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_6_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.518 | 0.490 | tNET | RR | 1 | R40C44[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R40C44[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_6_s0/CLK |
0.244 | 0.014 | tHld | 1 | R40C44[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 30.097%; route: 0.649, 50.388%; tC2Q: 0.251, 19.515% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path18
Path Summary:
Slack | 1.274 |
Data Arrival Time | 1.518 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_7_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.518 | 0.490 | tNET | RR | 1 | R40C44[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R40C44[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_7_s0/CLK |
0.244 | 0.014 | tHld | 1 | R40C44[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 30.097%; route: 0.649, 50.388%; tC2Q: 0.251, 19.515% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path19
Path Summary:
Slack | 1.281 |
Data Arrival Time | 1.525 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.525 | 0.498 | tNET | RR | 1 | R41C44[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C44[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C44[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.923%; route: 0.656, 50.675%; tC2Q: 0.251, 19.402% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path20
Path Summary:
Slack | 1.281 |
Data Arrival Time | 1.525 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.525 | 0.498 | tNET | RR | 1 | R41C44[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C44[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C44[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.923%; route: 0.656, 50.675%; tC2Q: 0.251, 19.402% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path21
Path Summary:
Slack | 1.281 |
Data Arrival Time | 1.525 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.525 | 0.498 | tNET | RR | 1 | R41C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C44[0][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.923%; route: 0.656, 50.675%; tC2Q: 0.251, 19.402% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path22
Path Summary:
Slack | 1.281 |
Data Arrival Time | 1.525 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.525 | 0.498 | tNET | RR | 1 | R41C44[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C44[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C44[1][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq1_rptr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.923%; route: 0.656, 50.675%; tC2Q: 0.251, 19.402% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path23
Path Summary:
Slack | 1.285 |
Data Arrival Time | 1.529 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.529 | 0.501 | tNET | RR | 1 | R41C43[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C43[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C43[2][B] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.837%; route: 0.660, 50.817%; tC2Q: 0.251, 19.346% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path24
Path Summary:
Slack | 1.285 |
Data Arrival Time | 1.529 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.529 | 0.501 | tNET | RR | 1 | R41C43[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C43[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C43[2][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wptr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.837%; route: 0.660, 50.817%; tC2Q: 0.251, 19.346% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Path25
Path Summary:
Slack | 1.285 |
Data Arrival Time | 1.529 |
Data Required Time | 0.244 |
From | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1 |
To | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0 |
Launch Clk | peripheral_clk:[R] |
Latch Clk | peripheral_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/CLK |
0.482 | 0.251 | tC2Q | RF | 3 | R39C41[0][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/txf_clr_level_s1/Q |
0.640 | 0.159 | tNET | FF | 1 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/I1 |
1.028 | 0.387 | tINS | FR | 40 | R39C41[3][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/n19_s0/F |
1.529 | 0.501 | tNET | RR | 1 | R41C43[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | peripheral_clk | ||||
0.000 | 0.000 | tCL | RR | 1127 | PLL_R[1] | rpll_peripheral/rpll_inst/CLKOUT |
0.230 | 0.230 | tNET | RR | 1 | R41C43[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0/CLK |
0.244 | 0.014 | tHld | 1 | R41C43[1][A] | USB_to_Multi_Serial/usb_to_multi_serial_wrapper_u0/usb_spi1_ctrl/atcspi200_top_inst/atcspi200_inst/u_spi_fifo/u_spi_txfifo/wq2_rptr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Arrival Data Path Delay | cell: 0.387, 29.837%; route: 0.660, 50.817%; tC2Q: 0.251, 19.346% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.230, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_2_s0/CLK |
MPW2
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_1_s0/CLK |
MPW3
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/rx_data_0_s0/CLK |
MPW4
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wq2_rptr_0_s0/CLK |
MPW5
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_5_s0/CLK |
MPW6
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/Equal.wptr_4_s0/CLK |
MPW7
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/rbin_num_0_s0/CLK |
MPW8
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/Small.mem_Small.mem_0_0_s/CLKB |
MPW9
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_rx_phy/u_cdr_serdes_x8_dx/fifo_rx/fifo_4to8_sub_inst/reset_w_0_s0/CLK |
MPW10
MPW Summary:
Slack: | 2.817 |
Actual Width: | 4.067 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_120 |
Objects: | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
4.170 | 0.000 | active clock edge time | ||
4.170 | 0.000 | clk_120 | ||
4.170 | 0.000 | tCL | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
4.497 | 0.327 | tNET | FF | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
8.333 | 0.000 | active clock edge time | ||
8.333 | 0.000 | clk_120 | ||
8.333 | 0.000 | tCL | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT |
8.563 | 0.230 | tNET | RR | u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/i_tx_phy/u_fifo_8to4/fifo_8to4_sub_inst/reset_r_1_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
2799 | PHY_RESET | 6.360 | 2.157 |
2356 | PHY_CLKOUT | 0.212 | 0.534 |
1127 | clk_48 | 0.399 | 0.534 |
319 | jtag_tck_Z | 23.542 | 1.307 |
163 | sclk | 0.753 | 0.327 |
153 | div_cmpl | 13.292 | 1.934 |
118 | RESET_IN | 7.306 | 2.733 |
85 | rd_cfg_cnt[0] | 11.518 | 2.158 |
83 | endpt_sel[0] | 0.821 | 2.372 |
77 | spi_transfmt[3] | 12.880 | 1.457 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R29C41 | 91.67% |
R22C12 | 90.28% |
R14C12 | 90.28% |
R23C30 | 90.28% |
R18C47 | 88.89% |
R22C14 | 88.89% |
R41C42 | 88.89% |
R22C16 | 88.89% |
R14C5 | 88.89% |
R35C31 | 87.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name peripheral_clk -period 20.833 -waveform {0 10.416} [get_pins {rpll_peripheral/rpll_inst/CLKOUT}] |
TC_CLOCK | Actived | create_clock -name jtag_tck -period 33.333 -waveform {0 16.666} [get_nets {jtag_tck_Z}] |
TC_CLOCK | Actived | create_clock -name clk_in -period 83.333 -waveform {0 41.67} [get_ports {clkin}] |
TC_CLOCK | Actived | create_clock -name clk_480 -period 2.083 -waveform {0 1.042} [get_pins {u_pll/rpll_inst/CLKOUT}] |
TC_CLOCK | Actived | create_clock -name clk_60 -period 16.667 -waveform {0 8.33} [get_pins {u_pll/rpll_inst/CLKOUTD}] |
TC_CLOCK | Actived | create_clock -name clk_120 -period 8.333 -waveform {0 4.17} [get_pins {u_USB_SoftPHY_Top/u_usb2_0_softphy/u_usb_phy_hs/clkdiv_inst/CLKOUT}] |
TC_CLOCK | Actived | create_clock -name spi1_clk -period 20.833 -waveform {0 10.416} [get_ports {spi1_clk_o}] |
TC_CLOCK | Actived | create_clock -name jtag_clk -period 33.333 -waveform {0 16.666} [get_ports {jtag_clk}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk_120}] -to [get_clocks {clk_60}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_120}] -group [get_clocks {clk_60}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_60}] -group [get_clocks {clk_480}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_60}] -group [get_clocks {clk_120}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_60}] -group [get_clocks {jtag_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_60}] -group [get_clocks {peripheral_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {peripheral_clk}] -group [get_clocks {clk_60}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk_60}] -group [get_clocks {jtag_tck}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {jtag_clk}] -group [get_clocks {jtag_tck}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {spi1_clk}] -group [get_clocks {peripheral_clk}] |