Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v C:\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-2 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Mon Jun 19 16:43:12 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Uart_to_Bus_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.389s, Peak memory usage = 48.223MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 48.223MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 48.223MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 48.223MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 48.223MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 48.223MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 48.223MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 48.223MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 48.223MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 48.223MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 48.223MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 48.223MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 59.543MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 59.543MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 59.543MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 59.543MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 214 |
I/O Buf | 214 |
    IBUF | 69 |
    OBUF | 145 |
Register | 658 |
    DFFRE | 11 |
    DFFPE | 9 |
    DFFCE | 638 |
LUT | 555 |
    LUT2 | 91 |
    LUT3 | 210 |
    LUT4 | 254 |
ALU | 40 |
    ALU | 40 |
SSRAM | 25 |
    RAM16SDP4 | 25 |
INV | 11 |
    INV | 11 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 756(566 LUTs, 40 ALUs, 25 SSRAMs) / 138240 | <1% |
Register | 658 / 139140 | <1% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 658 / 139140 | <1% |
BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk_i | 100.0(MHz) | 194.5(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.858 |
Data Arrival Time | 5.970 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s59/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s59/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s54/I1 |
2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s54/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s49/I0 |
3.433 | 0.517 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s49/F |
3.670 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s45/I1 |
4.225 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s45/F |
4.462 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/I0 |
4.979 | 0.517 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/F |
5.216 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/I0 |
5.733 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n259_s43/F |
5.970 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.216, 62.972%; route: 1.659, 32.485%; tC2Q: 0.232, 4.543% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 4.858 |
Data Arrival Time | 5.970 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_14_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s59/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s59/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s54/I1 |
2.679 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s54/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s49/I0 |
3.433 | 0.517 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n262_s49/F |
3.670 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s45/I1 |
4.225 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n264_s45/F |
4.462 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/I0 |
4.979 | 0.517 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s48/F |
5.216 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s46/I0 |
5.733 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n258_s46/F |
5.970 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.216, 62.972%; route: 1.659, 32.485%; tC2Q: 0.232, 4.543% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 4.922 |
Data Arrival Time | 5.905 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_13_s0 |
To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_13_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_13_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s64/I1 |
1.887 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s64/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s55/I0 |
2.641 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s55/F |
2.878 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s49/I1 |
3.433 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n261_s49/F |
3.670 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s48/I0 |
4.187 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s48/F |
4.424 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s47/I2 |
4.877 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s47/F |
5.114 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/I1 |
5.668 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n263_s45/F |
5.905 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.152, 62.503%; route: 1.659, 32.897%; tC2Q: 0.232, 4.600% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 4.928 |
Data Arrival Time | 5.899 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0 |
To | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_14_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n121_s3/I1 |
1.887 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n121_s3/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n120_s3/I1 |
2.679 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n120_s3/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n117_s4/I3 |
3.287 | 0.371 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n117_s4/F |
3.524 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n114_s4/I1 |
4.079 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n114_s4/F |
4.316 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s4/I1 |
4.871 | 0.555 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s4/F |
5.108 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s5/I1 |
5.662 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s5/F |
5.899 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_14_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_14_s0/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_14_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.146, 62.458%; route: 1.659, 32.936%; tC2Q: 0.232, 4.606% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 4.928 |
Data Arrival Time | 5.899 |
Data Required Time | 10.828 |
From | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0 |
To | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_15_s0 |
Launch Clk | clk_i[R] |
Latch Clk | clk_i[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk_i | |||
0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
0.683 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 5 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n121_s3/I1 |
1.887 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n121_s3/F |
2.124 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n120_s3/I1 |
2.679 | 0.555 | tINS | FF | 3 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n120_s3/F |
2.916 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n117_s4/I3 |
3.287 | 0.371 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n117_s4/F |
3.524 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n114_s4/I1 |
4.079 | 0.555 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n114_s4/F |
4.316 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s4/I1 |
4.871 | 0.555 | tINS | FF | 2 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n111_s4/F |
5.108 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n110_s2/I1 |
5.662 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/n110_s2/F |
5.899 | 0.237 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_15_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk_i | |||
10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
10.682 | 0.683 | tINS | RR | 683 | clk_i_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_15_s0/CLK |
10.828 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_15_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.146, 62.458%; route: 1.659, 32.936%; tC2Q: 0.232, 4.606% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |