Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\HYPERRAM_EMB\data\HPRAM_TOP.v D:\Gowin\Gowin_V1.9.9Beta-6\IDE\ipcore\HYPERRAM_EMB\data\hpram_code_166.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-6 |
Part Number | GW1NSR-LV4CQN48PC7/I6 |
Device | GW1NSR-4C |
Created Time | Tue Oct 24 14:28:14 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | HyperRAM_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.689s, Peak memory usage = 38.523MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 38.523MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 38.523MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 38.523MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 38.523MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 38.523MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.523MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 38.523MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.523MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 38.523MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 38.523MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 38.523MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 53.758MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 53.758MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 53.758MB |
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 53.758MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 99 |
Embedded Port | 13 |
I/O Buf | 112 |
    IBUF | 64 |
    OBUF | 39 |
    IOBUF | 9 |
Register | 407 |
    DFF | 1 |
    DFFP | 3 |
    DFFPE | 3 |
    DFFC | 243 |
    DFFCE | 157 |
LUT | 563 |
    LUT2 | 157 |
    LUT3 | 173 |
    LUT4 | 233 |
ALU | 31 |
    ALU | 31 |
INV | 6 |
    INV | 6 |
IOLOGIC | 30 |
    IDES4 | 8 |
    OSER4 | 12 |
    IODELAY | 10 |
BSRAM | 1 |
    SDPX9B | 1 |
CLOCK | 2 |
    CLKDIV | 1 |
    DHCEN | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 600(569 LUT, 31 ALU) / 4608 | 14% |
Register | 407 / 3609 | 12% |
  --Register as Latch | 0 / 3609 | 0% |
  --Register as FF | 407 / 3609 | 12% |
BSRAM | 1 / 10 | 10% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
memory_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | ||
clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
u_hpram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | u_hpram_top/clkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.0(MHz) | 186.3(MHz) | 5 | TOP |
2 | u_hpram_top/clkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 187.9(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 9.175 |
Data Arrival Time | 1.692 |
Data Required Time | 10.867 |
From | u_hpram_top/u_hpram_sync/cs_memsync_4_s0 |
To | u_hpram_top/u_dqce_clk_x2p |
Launch Clk | clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_hpram_top/u_dqce_clk_x2p/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | memory_clk | |||
10.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
10.729 | 0.729 | tINS | FF | 1 | memory_clk_ibuf/O |
11.085 | 0.356 | tNET | FF | 3 | u_hpram_top/u_dqce_clk_x2p/CLKIN |
11.055 | -0.030 | tUnc | u_hpram_top/u_dqce_clk_x2p | ||
10.867 | -0.188 | tSu | 1 | u_hpram_top/u_dqce_clk_x2p |
Clock Skew: | 0.089 |
Setup Relationship: | 10.000 |
Logic Level: | 1 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:Slack | 14.633 |
Data Arrival Time | 6.067 |
Data Required Time | 20.700 |
From | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
To | u_hpram_top/u_hpram_sync/cs_memsync_3_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s11/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n348_s11/F |
2.862 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n293_s15/I0 |
3.627 | 0.765 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n293_s15/F |
3.982 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n293_s12/I2 |
4.591 | 0.609 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n293_s12/F |
4.947 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n304_s12/I0 |
5.712 | 0.765 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n304_s12/F |
6.067 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/cs_memsync_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/cs_memsync_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.953, 58.231%; route: 1.778, 35.071%; tC2Q: 0.340, 6.698% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:Slack | 14.679 |
Data Arrival Time | 6.022 |
Data Required Time | 20.700 |
From | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
To | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s11/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n348_s11/F |
2.862 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s7/I1 |
3.676 | 0.814 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n348_s7/F |
4.032 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n337_s15/I1 |
4.846 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n337_s15/F |
5.202 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n337_s12/I3 |
5.666 | 0.464 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n337_s12/F |
6.022 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.907, 57.850%; route: 1.778, 35.391%; tC2Q: 0.340, 6.759% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:Slack | 14.728 |
Data Arrival Time | 5.972 |
Data Required Time | 20.700 |
From | u_hpram_top/u_hpram_sync/cs_memsync_0_s0 |
To | u_hpram_top/u_hpram_sync/flag_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK |
1.336 | 0.340 | tC2Q | RF | 7 | u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q |
1.692 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s11/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n348_s11/F |
2.862 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n359_s11/I1 |
3.676 | 0.814 | tINS | FF | 2 | u_hpram_top/u_hpram_sync/n359_s11/F |
4.032 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s6/I3 |
4.496 | 0.464 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n348_s6/F |
4.851 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n348_s5/I0 |
5.616 | 0.765 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n348_s5/F |
5.972 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/flag_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/flag_1_s0/CLK |
20.700 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/flag_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.857, 57.430%; route: 1.778, 35.744%; tC2Q: 0.340, 6.826% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 5
Path Summary:Slack | 14.739 |
Data Arrival Time | 5.962 |
Data Required Time | 20.700 |
From | u_hpram_top/u_hpram_sync/lock_cnt_1_s3 |
To | u_hpram_top/u_hpram_sync/lock_cnt_12_s3 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
0.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK |
1.336 | 0.340 | tC2Q | RF | 5 | u_hpram_top/u_hpram_sync/lock_cnt_1_s3/Q |
1.692 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n47_s2/I1 |
2.506 | 0.814 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n47_s2/F |
2.862 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n43_s2/I2 |
3.471 | 0.609 | tINS | FF | 5 | u_hpram_top/u_hpram_sync/n43_s2/F |
3.827 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n39_s2/I2 |
4.436 | 0.609 | tINS | FF | 4 | u_hpram_top/u_hpram_sync/n39_s2/F |
4.791 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/n39_s5/I1 |
5.606 | 0.814 | tINS | FF | 1 | u_hpram_top/u_hpram_sync/n39_s5/F |
5.961 | 0.356 | tNET | FF | 1 | u_hpram_top/u_hpram_sync/lock_cnt_12_s3/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.728 | 0.728 | tINS | RR | 31 | clk_ibuf/O |
20.997 | 0.269 | tNET | RR | 1 | u_hpram_top/u_hpram_sync/lock_cnt_12_s3/CLK |
20.700 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_sync/lock_cnt_12_s3 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Arrival Data Path Delay: | cell: 2.847, 57.341%; route: 1.778, 35.819%; tC2Q: 0.340, 6.840% |
Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |