Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\src\dk_video.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Wed Jan 10 10:51:41 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 12275
Numbers of Endpoints Analyzed 12443
Numbers of Falling Endpoints 8
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
I_clk Base 20.000 50.000 0.000 10.000 I_clk
dma_clk Base 13.333 75.002 0.000 6.667 dma_clk
memory_clk Base 3.333 300.030 0.000 1.667 memory_clk
O_adv7513_clk Base 13.468 74.250 0.000 6.734 O_adv7513_clk O_adv7513_clk_d
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 13.333 75.000 1.667 8.333 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTP
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 26.667 37.500 0.000 13.333 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 40.000 25.000 0.000 20.000 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD3
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 3.333 300.000 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTP
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 6.667 150.000 0.000 3.333 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 10.000 100.000 0.000 5.000 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 50.000(MHz) 177.733(MHz) 6 TOP
2 dma_clk 75.002(MHz) 95.268(MHz) 9 TOP
3 memory_clk 300.030(MHz) 2016.129(MHz) 1 TOP
4 O_adv7513_clk 74.250(MHz) 136.548(MHz) 5 TOP

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
I_clk Setup 0.000 0
I_clk Hold 0.000 0
dma_clk Setup 0.000 0
dma_clk Hold 0.000 0
memory_clk Setup 0.000 0
memory_clk Hold 0.000 0
O_adv7513_clk Setup 0.000 0
O_adv7513_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.836 DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/full_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D dma_clk:[R] dma_clk:[R] 13.333 0.000 10.462
2 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
3 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
4 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
5 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
6 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
7 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
8 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
9 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
10 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
11 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
12 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
13 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
14 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
15 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
16 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
17 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
18 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
19 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
20 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
21 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
22 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
23 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
24 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496
25 2.837 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0] memory_clk:[R] memory_clk:[R] 3.333 0.000 0.496

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_64_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[8] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
2 0.198 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_25_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/DI[13] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.447
3 0.202 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[6] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.451
4 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_18_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[21] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
5 0.213 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_48_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[7] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.462
6 0.215 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/ADA[4] I_clk:[R] I_clk:[R] 0.000 0.000 0.333
7 0.225 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_105_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/DI[18] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.474
8 0.228 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_42_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/D2 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
9 0.230 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbin_7_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/ADA[12] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.348
10 0.234 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D4 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
11 0.234 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D6 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
12 0.234 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D2 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
13 0.234 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/D2 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
14 0.240 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_55_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/D7 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
15 0.240 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_69_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/D5 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
16 0.246 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D5 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
17 0.246 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D7 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
18 0.246 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D3 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
19 0.246 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/D3 dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
20 0.307 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/D dma_clk:[F] dma_clk:[F] 0.000 0.000 0.318
21 0.311 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
22 0.311 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.323
23 0.318 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_1_s0/CE dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
24 0.318 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_2_s0/CE dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329
25 0.318 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CE dma_clk:[R] dma_clk:[R] 0.000 0.000 0.329

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.097 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/RESETB dma_clk:[F] dma_clk:[R] 6.666 0.018 2.113
2 4.097 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/RESETB dma_clk:[F] dma_clk:[R] 6.666 0.018 2.113
3 4.097 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/RESETB dma_clk:[F] dma_clk:[R] 6.666 0.018 2.113
4 4.097 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/RESETB dma_clk:[F] dma_clk:[R] 6.666 0.018 2.113
5 4.286 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 6.734 0.018 1.992
6 4.286 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 6.734 0.018 1.992
7 4.286 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 6.734 0.018 1.992
8 4.286 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB O_adv7513_clk:[F] O_adv7513_clk:[R] 6.734 0.018 1.992
9 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
10 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
11 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
12 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
13 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
14 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
15 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
16 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
17 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_0_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
18 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_1_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
19 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_2_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
20 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_5_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
21 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
22 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_7_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
23 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
24 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_2_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129
25 4.484 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1/CLEAR dma_clk:[F] dma_clk:[R] 6.666 0.018 2.129

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.387 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.398
2 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
3 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
4 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
5 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
6 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
7 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
8 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
9 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
10 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
11 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
12 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
13 1.519 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 1.530
14 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
15 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
16 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
17 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
18 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
19 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
20 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
21 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/dll_rst_s0/PRESET I_clk:[R] I_clk:[R] 0.000 0.000 1.776
22 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
23 1.765 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.776
24 1.770 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.781
25 1.770 key_debounceN_inst1/key_n_out2_s1/Q DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.781

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 5.589 6.589 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
2 5.589 6.589 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_19_s1
3 5.589 6.589 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1
4 5.589 6.589 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_falling_r_s0
5 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_54_s0
6 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_38_s0
7 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_30_s0
8 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_26_s0
9 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_24_s0
10 5.589 6.589 1.000 Low Pulse Width dma_clk DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_23_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.836
Data Arrival Time 10.705
Data Required Time 13.541
From DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/full_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.243 0.243 tNET RR 1 R14C37[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/full_s0/CLK
0.475 0.232 tC2Q RF 12 R14C37[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/full_s0/Q
2.682 2.207 tNET FF 1 R33C42[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/I0
3.053 0.371 tINS FF 6 R33C42[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/cmd_ready_d_s0/F
3.756 0.703 tNET FF 1 R33C48[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/I2
4.273 0.517 tINS FF 24 R33C48[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma0_wr_data_end_s/F
4.822 0.549 tNET FF 1 R31C44[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I2
5.377 0.555 tINS FF 7 R31C44[3][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F
5.961 0.584 tNET FF 1 R33C45[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s4/I3
6.414 0.453 tINS FF 5 R33C45[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s4/F
6.840 0.426 tNET FF 1 R31C44[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/I1
7.395 0.555 tINS FF 3 R31C44[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/F
7.964 0.569 tNET FF 1 R32C45[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s1/I0
8.513 0.549 tINS FR 2 R32C45[3][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s1/F
8.658 0.146 tNET RR 2 R32C45[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/I0
9.175 0.517 tINS RF 1 R32C45[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n708_s0/COUT
10.135 0.960 tNET FF 1 R32C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
10.705 0.570 tINS FR 1 R32C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
10.705 0.000 tNET RR 1 R32C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
13.541 -0.035 tSu 1 R32C41[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.333
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 4.087, 39.066%; route: 6.143, 58.716%; tC2Q: 0.232, 2.218%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path3

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path4

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL18[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path5

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path6

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path7

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path8

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path9

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path10

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path11

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path12

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path13

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL21[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path14

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path15

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path16

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL20[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path17

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path18

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path19

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL26[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path20

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path21

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path22

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL23[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path23

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[2]
0.803 0.000 tNET FF 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path24

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[1]
0.803 0.000 tNET FF 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Path25

Path Summary:

Slack 2.837
Data Arrival Time 0.803
Data Required Time 3.640
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk memory_clk:[R]
Latch Clk memory_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 memory_clk
0.000 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
0.000 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.182 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.307 0.125 tNET RR 5 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
0.803 0.496 tC2Q RF 8 R18C0 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RPOINT[0]
0.803 0.000 tNET FF 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/RADDR[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
3.333 3.333 active clock edge time
3.333 0.000 memory_clk
3.333 0.000 tCL RR 1 PLL_R[1] ddr3_rpll_inst/rpll_inst/CLKOUT
3.333 0.000 tNET RR 3 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.515 0.182 tINS RR 64 - DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.640 0.125 tNET RR 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
3.640 0.000 tSu 1 IOL27[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew 0.000
Setup Relationship 3.333
Logic Level 1
Arrival Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.496, 100.000%
Required Clock Path Delay cell: 0.182, 59.219%; route: 0.125, 40.781%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_64_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C17[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_64_s0/CLK
0.386 0.202 tC2Q RR 1 R42C17[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_64_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
0.433 0.249 tHld 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 0.198
Data Arrival Time 0.631
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_25_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R26C17[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_25_s0/CLK
0.386 0.202 tC2Q RR 1 R26C17[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_25_s0/Q
0.631 0.245 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/DI[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 0.202
Data Arrival Time 0.635
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R44C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/CLK
0.386 0.202 tC2Q RR 1 R44C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_32_s0/Q
0.635 0.249 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
0.433 0.249 tHld 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_18_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R45C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_18_s0/CLK
0.386 0.202 tC2Q RR 1 R45C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_18_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[21]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
0.433 0.249 tHld 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 0.213
Data Arrival Time 0.647
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_48_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R43C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_48_s0/CLK
0.386 0.202 tC2Q RR 1 R43C17[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_48_s0/Q
0.647 0.260 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/DI[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKA
0.433 0.249 tHld 1 BSRAM_R46[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack 0.215
Data Arrival Time 1.192
Data Required Time 0.978
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R27C48[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/CLK
1.061 0.201 tC2Q RF 6 R27C48[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/Q
1.192 0.132 tNET FF 1 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/CLKA
0.978 0.118 tHld 1 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.132, 39.591%; tC2Q: 0.201, 60.409%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack 0.225
Data Arrival Time 0.659
Data Required Time 0.433
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_105_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R29C23[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_105_s0/CLK
0.386 0.202 tC2Q RR 1 R29C23[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/mux_wrdata_105_s0/Q
0.659 0.272 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/DI[18]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKA
0.433 0.249 tHld 1 BSRAM_R28[4] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 0.228
Data Arrival Time 0.507
Data Required Time 0.279
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_42_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R17C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_42_s0/CLK
0.385 0.201 tC2Q RF 1 R17C2[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_42_s0/Q
0.507 0.122 tNET FF 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK
0.279 0.095 tHld 1 IOL17[A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 0.230
Data Arrival Time 0.532
Data Required Time 0.302
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbin_7_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C45[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbin_7_s0/CLK
0.386 0.202 tC2Q RR 12 R47C45[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbin_7_s0/Q
0.532 0.146 tNET RR 1 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKA
0.302 0.118 tHld 1 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.146, 41.880%; tC2Q: 0.202, 58.120%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 0.234
Data Arrival Time 0.513
Data Required Time 0.279
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R2C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/CLK
0.385 0.201 tC2Q RF 2 R2C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/Q
0.513 0.128 tNET FF 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D4

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK
0.279 0.095 tHld 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack 0.234
Data Arrival Time 0.513
Data Required Time 0.279
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R6C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/CLK
0.385 0.201 tC2Q RF 2 R6C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/Q
0.513 0.128 tNET FF 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/PCLK
0.279 0.095 tHld 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack 0.234
Data Arrival Time 0.513
Data Required Time 0.279
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R6C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/CLK
0.385 0.201 tC2Q RF 2 R6C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/Q
0.513 0.128 tNET FF 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/PCLK
0.279 0.095 tHld 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack 0.234
Data Arrival Time 0.513
Data Required Time 0.279
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R5C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/CLK
0.385 0.201 tC2Q RF 2 R5C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/Q
0.513 0.128 tNET FF 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/PCLK
0.279 0.095 tHld 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack 0.240
Data Arrival Time 0.507
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_55_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R25C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_55_s0/CLK
0.385 0.201 tC2Q RF 1 R25C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_55_s0/Q
0.507 0.122 tNET FF 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/D7

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.267 0.083 tHld 1 IOL25[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack 0.240
Data Arrival Time 0.507
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_69_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R35C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_69_s0/CLK
0.385 0.201 tC2Q RF 1 R35C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_dq_rr_69_s0/Q
0.507 0.122 tNET FF 1 IOL35[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL35[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.267 0.083 tHld 1 IOL35[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack 0.246
Data Arrival Time 0.513
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R2C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/CLK
0.385 0.201 tC2Q RF 2 R2C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_38_s0/Q
0.513 0.128 tNET FF 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/D5

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK
0.267 0.083 tHld 1 IOL2[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 0.246
Data Arrival Time 0.513
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R6C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/CLK
0.385 0.201 tC2Q RF 2 R6C2[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_19_s0/Q
0.513 0.128 tNET FF 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D7

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/PCLK
0.267 0.083 tHld 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 0.246
Data Arrival Time 0.513
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R6C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/CLK
0.385 0.201 tC2Q RF 2 R6C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_17_s0/Q
0.513 0.128 tNET FF 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/PCLK
0.267 0.083 tHld 1 IOL6[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 0.246
Data Arrival Time 0.513
Data Required Time 0.267
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R5C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/CLK
0.385 0.201 tC2Q RF 2 R5C2[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/oserdes_d_rr_9_s0/Q
0.513 0.128 tNET FF 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/D3

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/PCLK
0.267 0.083 tHld 1 IOL5[B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.128, 38.816%; tC2Q: 0.201, 61.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack 0.307
Data Arrival Time 7.179
Data Required Time 6.873
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.862 0.195 tNET FF 1 R32C44[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/CLK
7.063 0.201 tC2Q FF 1 R32C44[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/Q
7.179 0.117 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.862 0.195 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
6.873 0.011 tHld 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.195, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.195, 100.000%

Path21

Path Summary:

Slack 0.311
Data Arrival Time 0.507
Data Required Time 0.196
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/CLK
0.385 0.201 tC2Q RF 1 R32C7[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_3_s0/Q
0.507 0.122 tNET FF 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
0.196 0.012 tHld 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack 0.311
Data Arrival Time 0.507
Data Required Time 0.196
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C7[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/CLK
0.385 0.201 tC2Q RF 1 R32C7[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_1_s0/Q
0.507 0.122 tNET FF 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLK
0.196 0.012 tHld 1 R32C8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 0.318
Data Arrival Time 0.514
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/CLK
0.386 0.202 tC2Q RR 4 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q
0.514 0.127 tNET RR 1 R13C19[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R13C19[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_1_s0/CLK
0.195 0.011 tHld 1 R13C19[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 38.685%; tC2Q: 0.202, 61.315%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 0.318
Data Arrival Time 0.514
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/CLK
0.386 0.202 tC2Q RR 4 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q
0.514 0.127 tNET RR 1 R13C19[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R13C19[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_2_s0/CLK
0.195 0.011 tHld 1 R13C19[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 38.685%; tC2Q: 0.202, 61.315%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack 0.318
Data Arrival Time 0.514
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/CLK
0.386 0.202 tC2Q RR 4 R14C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_adj_s0/Q
0.514 0.127 tNET RR 1 R13C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R13C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0/CLK
0.195 0.011 tHld 1 R13C19[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/read_calibration_logic_gen[1].read_i_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.127, 38.685%; tC2Q: 0.202, 61.315%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.097
Data Arrival Time 9.042
Data Required Time 13.138
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.042 1.881 tNET FF 32 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s/CLKB
13.138 -0.438 tSu 1 BSRAM_R28[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_3_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.881, 89.021%; tC2Q: 0.232, 10.979%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 4.097
Data Arrival Time 9.042
Data Required Time 13.138
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.042 1.881 tNET FF 32 BSRAM_R28[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 BSRAM_R28[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s/CLKB
13.138 -0.438 tSu 1 BSRAM_R28[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_2_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.881, 89.021%; tC2Q: 0.232, 10.979%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 4.097
Data Arrival Time 9.042
Data Required Time 13.138
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.042 1.881 tNET FF 32 BSRAM_R28[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 BSRAM_R28[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKB
13.138 -0.438 tSu 1 BSRAM_R28[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.881, 89.021%; tC2Q: 0.232, 10.979%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 4.097
Data Arrival Time 9.042
Data Required Time 13.138
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.042 1.881 tNET FF 32 BSRAM_R28[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 BSRAM_R28[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKB
13.138 -0.438 tSu 1 BSRAM_R28[10] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.881, 89.021%; tC2Q: 0.232, 10.979%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 4.286
Data Arrival Time 8.988
Data Required Time 13.273
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
6.995 0.261 tNET FF 1 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.227 0.232 tC2Q FF 55 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.988 1.760 tNET FF 32 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 O_adv7513_clk
13.468 0.000 tCL RR 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
13.711 0.243 tNET RR 1 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s/CLKB
13.273 -0.438 tSu 1 BSRAM_R46[14] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_3_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.760, 88.354%; tC2Q: 0.232, 11.646%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 4.286
Data Arrival Time 8.988
Data Required Time 13.273
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
6.995 0.261 tNET FF 1 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.227 0.232 tC2Q FF 55 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.988 1.760 tNET FF 32 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 O_adv7513_clk
13.468 0.000 tCL RR 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
13.711 0.243 tNET RR 1 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s/CLKB
13.273 -0.438 tSu 1 BSRAM_R46[13] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_2_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.760, 88.354%; tC2Q: 0.232, 11.646%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 4.286
Data Arrival Time 8.988
Data Required Time 13.273
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
6.995 0.261 tNET FF 1 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.227 0.232 tC2Q FF 55 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.988 1.760 tNET FF 32 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 O_adv7513_clk
13.468 0.000 tCL RR 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
13.711 0.243 tNET RR 1 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
13.273 -0.438 tSu 1 BSRAM_R46[12] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.760, 88.354%; tC2Q: 0.232, 11.646%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 4.286
Data Arrival Time 8.988
Data Required Time 13.273
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk O_adv7513_clk:[F]
Latch Clk O_adv7513_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 O_adv7513_clk
6.734 0.000 tCL FF 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
6.995 0.261 tNET FF 1 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.227 0.232 tC2Q FF 55 R44C46[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
8.988 1.760 tNET FF 32 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 O_adv7513_clk
13.468 0.000 tCL RR 169 PLL_R[0] pix_rpll_inst/rpll_inst/CLKOUT
13.711 0.243 tNET RR 1 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
13.273 -0.438 tSu 1 BSRAM_R46[11] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.760, 88.354%; tC2Q: 0.232, 11.646%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLK
13.541 -0.035 tSu 1 R33C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLK
13.541 -0.035 tSu 1 R33C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLK
13.541 -0.035 tSu 1 R33C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLK
13.541 -0.035 tSu 1 R33C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLK
13.541 -0.035 tSu 1 R33C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R33C40[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R33C40[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLK
13.541 -0.035 tSu 1 R33C40[2][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C47[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C47[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/CLK
13.541 -0.035 tSu 1 R32C47[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C47[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C47[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s1/CLK
13.541 -0.035 tSu 1 R32C47[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_2_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_0_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R30C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R30C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_0_s1/CLK
13.541 -0.035 tSu 1 R30C40[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_1_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R30C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R30C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_1_s1/CLK
13.541 -0.035 tSu 1 R30C40[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_1_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_2_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C42[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C42[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_2_s1/CLK
13.541 -0.035 tSu 1 R32C42[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_2_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_5_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C42[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C42[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_5_s1/CLK
13.541 -0.035 tSu 1 R32C42[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_5_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R30C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R30C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1/CLK
13.541 -0.035 tSu 1 R30C40[0][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_6_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_7_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C47[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C47[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_7_s1/CLK
13.541 -0.035 tSu 1 R32C47[1][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq2_wptr_7_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R30C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R30C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s1/CLK
13.541 -0.035 tSu 1 R30C40[1][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_0_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_2_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R32C42[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R32C42[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_2_s1/CLK
13.541 -0.035 tSu 1 R32C42[2][A] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_2_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 4.484
Data Arrival Time 9.057
Data Required Time 13.541
From Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.667 6.667 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF 1 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
7.160 0.232 tC2Q FF 63 R32C44[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
9.057 1.897 tNET FF 1 R30C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.333 13.333 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.576 0.243 tNET RR 1 R30C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1/CLK
13.541 -0.035 tSu 1 R30C40[0][B] Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.666
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.102%; tC2Q: 0.232, 10.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.387
Data Arrival Time 1.583
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.583 0.254 tNET RR 1 R33C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0/CLK
0.195 0.011 tHld 1 R33C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 27.460%; route: 0.812, 58.095%; tC2Q: 0.202, 14.445%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0/CLK
0.195 0.011 tHld 1 R33C15[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0/CLK
0.195 0.011 tHld 1 R33C15[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0/CLK
0.195 0.011 tHld 1 R33C14[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0/CLK
0.195 0.011 tHld 1 R33C14[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0/CLK
0.195 0.011 tHld 1 R33C15[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0/CLK
0.195 0.011 tHld 1 R33C14[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0/CLK
0.195 0.011 tHld 1 R33C15[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0/CLK
0.195 0.011 tHld 1 R33C14[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0/CLK
0.195 0.011 tHld 1 R33C15[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq2_wptr_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0/CLK
0.195 0.011 tHld 1 R33C14[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0/CLK
0.195 0.011 tHld 1 R33C15[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack 1.519
Data Arrival Time 1.715
Data Required Time 0.195
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/CLK
0.386 0.202 tC2Q RR 1 R47C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_eye_calib_rmove_mod/if_fifo_rst_s0/Q
0.945 0.559 tNET RR 1 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/I1
1.329 0.384 tINS RR 40 R34C16[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_reset_gen/if_wrreset_Z_s/F
1.715 0.385 tNET RR 1 R33C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 4046 LEFTSIDE[0] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.184 0.184 tNET RR 1 R33C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0/CLK
0.195 0.011 tHld 1 R33C14[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/fifo_ctrl_gen[1].fifo_ctrl/if_rq1_wptr_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.384, 25.092%; route: 0.944, 61.708%; tC2Q: 0.202, 13.200%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R31C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R31C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1/CLK
0.871 0.011 tHld 1 R31C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R31C18[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R31C18[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1/CLK
0.871 0.011 tHld 1 R31C18[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R31C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R31C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1/CLK
0.871 0.011 tHld 1 R31C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R31C20[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R31C20[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1/CLK
0.871 0.011 tHld 1 R31C20[2][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R34C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R34C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0/CLK
0.871 0.011 tHld 1 R34C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/ddr_init_st_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R33C19[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R33C19[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLK
0.871 0.011 tHld 1 R33C19[1][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R33C20[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R33C20[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0/CLK
0.871 0.011 tHld 1 R33C20[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/dll_rst_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R27C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/dll_rst_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R27C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/dll_rst_s0/CLK
0.871 0.011 tHld 1 R27C18[0][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/dll_rst_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R33C20[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R33C20[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLK
0.871 0.011 tHld 1 R33C20[0][B] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack 1.765
Data Arrival Time 2.636
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.636 1.067 tNET RR 1 R33C19[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R33C19[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK
0.871 0.011 tHld 1 R33C19[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 22.011%; route: 1.184, 66.674%; tC2Q: 0.201, 11.315%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack 1.770
Data Arrival Time 2.641
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.641 1.072 tNET RR 1 R32C20[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R32C20[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4/CLK
0.871 0.011 tHld 1 R32C20[1][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_0_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 21.949%; route: 1.189, 66.767%; tC2Q: 0.201, 11.283%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack 1.770
Data Arrival Time 2.641
Data Required Time 0.871
From key_debounceN_inst1/key_n_out2_s1
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/CLK
1.061 0.201 tC2Q RF 1 R25C39[0][A] key_debounceN_inst1/key_n_out2_s1/Q
1.178 0.117 tNET FF 1 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/I0
1.569 0.391 tINS FR 41 R25C39[3][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/n7_s2/F
2.641 1.072 tNET RR 1 R30C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR27[A] I_clk_ibuf/I
0.675 0.675 tINS RR 581 IOR27[A] I_clk_ibuf/O
0.860 0.184 tNET RR 1 R30C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLK
0.871 0.011 tHld 1 R30C20[2][A] DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay cell: 0.391, 21.949%; route: 1.189, 66.767%; tC2Q: 0.201, 11.283%
Required Clock Path Delay cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK

MPW2

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_19_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_19_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_19_s1/CLK

MPW3

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1/CLK

MPW4

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_falling_r_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_falling_r_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_falling_r_s0/CLK

MPW5

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_54_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_54_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_54_s0/CLK

MPW6

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_38_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_38_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_38_s0/CLK

MPW7

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_30_s0/CLK

MPW8

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_26_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_26_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_26_s0/CLK

MPW9

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_24_s0/CLK

MPW10

MPW Summary:

Slack: 5.589
Actual Width: 6.589
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.667 0.000 active clock edge time
6.667 0.000 dma_clk
6.667 0.000 tCL FF DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
6.928 0.261 tNET FF DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
13.333 0.000 active clock edge time
13.333 0.000 dma_clk
13.333 0.000 tCL RR DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.517 0.184 tNET RR DDR3_Memory_Interface_Top_inst/gw3_top/gwmc_app_wdf_wdata_23_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
4046 dma_clk 2.836 0.261
581 I_clk_d 9.114 0.261
382 n16_6 17.205 2.247
266 n14_11 9.546 1.854
180 eye_calib_start_rr[0] 9.498 3.106
169 O_adv7513_clk_d 5.569 0.427
155 next_state.ST_IFF0_WRITE_DDR 6.335 1.538
149 dqsts1 10.643 1.874
148 dqs_reg 10.580 1.916
144 n28_3 9.889 1.599

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R30C45 91.67%
R30C46 91.67%
R30C19 86.11%
R35C37 84.72%
R40C36 84.72%
R38C36 84.72%
R33C40 84.72%
R22C20 84.72%
R24C18 83.33%
R16C9 83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK Actived create_clock -name dma_clk -period 13.333 -waveform {0 6.667} [get_nets {dma_clk}] -add
TC_CLOCK Actived create_clock -name memory_clk -period 3.333 -waveform {0 1.667} [get_nets {memory_clk}] -add
TC_CLOCK Actived create_clock -name O_adv7513_clk -period 13.468 -waveform {0 6.734} [get_ports {O_adv7513_clk}] -add
TC_FALSE_PATH Actived set_false_path -from [get_clocks {dma_clk}] -to [get_clocks {O_adv7513_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {O_adv7513_clk}] -to [get_clocks {dma_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {dma_clk}] -group [get_clocks {I_clk}] -group [get_clocks {memory_clk}] -group [get_clocks {O_adv7513_clk}]