PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\src\dk_video.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign_\Gowin_VFB_DDR3_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Wed Jan 10 10:51:41 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Placement Phase 1: CPU time = 0h 0m 0.517s, Elapsed time = 0h 0m 0.516s Placement Phase 2: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s Placement Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Total Placement: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s Running routing: Routing Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s Routing Phase 1: CPU time = 0h 0m 0.538s, Elapsed time = 0h 0m 0.538s Routing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Generate output files: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Time and Memory Usage CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 631MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 5016/20736 25%
    --LUT,ALU,ROM16 4194(3947 LUT, 247 ALU, 0 ROM16) -
    --SSRAM(RAM16) 137 -
Register 4570/16509 28%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 4563/15552 30%
    --I/O Register as Latch 0/957 0%
    --I/O Register as FF 7/957 <1%
CLS 4017/10368 39%
I/O Port 85 -
I/O Buf 82 -
    --Input Buf 3 -
    --Output Buf 59 -
    --Inout Buf 20 -
IOLOGIC 16 IDES8_MEM
24 OSER8
20 OSER8_MEM
16 IODELAY
38%
BSRAM 8 SDPB
4 SDPX9B
27%
DSP 00%
PLL 2/4 50%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 1/8 13%
DLLDLY 0/8 0%
DQS 2/16 13%
DHCEN 1/16 7%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/40(0%)
bank 1 2/39(5%)
bank 2 30/46(65%)
bank 3 10/34(29%)
bank 4 1/40(2%)
bank 5 0/40(0%)
bank 6 18/34(52%)
bank 7 24/46(52%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 3/8(38%)
LW 6/8(75%)
GCLK_PIN 2/8(25%)
PLL 2/4(50%)
CLKDIV 1/8(13%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
I_clk_d PRIMARY TR TL BR BL
O_adv7513_clk_d PRIMARY TR BR
dma_clk PRIMARY TR TL BR BL
n14_11 LW -
n16_6 LW -
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r[1] LW -
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r[1] LW -
DDR3_Memory_Interface_Top_inst/gw3_top/ddr_rst LW -
DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/n28_3 LW -
memory_clk HCLK BOTTOM[0] LEFT[0] RIGHT[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
I_clk M19/2 Y in IOR27[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
I_rst_n L22/2 Y in IOR21[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
I_key1 AB21/3 Y in IOR50[B] LVCMOS15 NA UP ON NONE NA NA OFF NA 1.5
O_led[0] W20/3 Y out IOR48[A] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
O_led[1] W22/3 Y out IOR36[B] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
O_led[2] V22/3 Y out IOR36[A] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
O_led[3] U20/3 Y out IOR38[B] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
O_adv7513_clk H21/2 Y out IOR15[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_vs L19/2 Y out IOR22[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_hs K22/2 Y out IOR21[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_de K20/2 Y out IOR23[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[0] K18/2 Y out IOR9[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[1] K19/2 Y out IOR22[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[2] J22/2 Y out IOR20[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[3] J19/2 Y out IOR16[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[4] J18/2 Y out IOR9[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[5] J20/2 Y out IOR16[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[6] H22/2 Y out IOR20[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[7] H19/2 Y out IOR5[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[8] H18/2 Y out IOR5[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[9] H20/2 Y out IOR15[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[10] G18/2 Y out IOR4[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[11] G19/2 Y out IOR11[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[12] G20/2 Y out IOR11[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[13] G22/2 Y out IOR18[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[14] F18/2 Y out IOR2[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[15] G21/2 Y out IOR18[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[16] F19/2 Y out IOR2[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[17] F20/2 Y out IOR12[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[18] F22/2 Y out IOR17[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[19] F21/2 Y out IOR12[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[20] E20/2 Y out IOR3[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[21] E22/2 Y out IOR17[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[22] E19/2 Y out IOR3[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_adv7513_data[23] D20/2 Y out IOR6[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_ddr_addr[0] G1/7 Y out IOL15[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[1] U5/6 Y out IOL53[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[2] G5/7 Y out IOL4[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[3] F5/7 Y out IOL2[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[4] V3/6 Y out IOL44[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[5] G2/7 Y out IOL14[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[6] AA22/3 Y out IOR44[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[7] H5/7 Y out IOL9[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[8] AB22/3 Y out IOR50[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[9] J4/7 Y out IOL16[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[10] R5/6 Y out IOL47[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[11] AA21/3 Y out IOR47[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[12] T5/6 Y out IOL54[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_addr[13] AA1/6 Y out IOL45[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_ba[0] F4/7 Y out IOL7[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_ba[1] U4/6 Y out IOL48[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_ba[2] F3/7 Y out IOL8[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_cs_n W19/4 N out IOB55[A] SSTL15 8 NA NA NA NA NA NA NA 1.5
O_ddr_ras_n D1/7 Y out IOL12[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_cas_n C3/7 Y out IOL5[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_we_n C1/7 Y out IOL11[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_clk O_ddr_clk_n P22,R22/3 Y out IOR29 SSTL15D 8 NA NA NA NA NA OFF NA 1.5
O_ddr_cke E3/7 Y out IOL6[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_odt B2/7 Y out IOL3[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_reset_n W4/6 Y out IOL50[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_dqm[0] R3/6 Y out IOL35[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
O_ddr_dqm[1] K4/7 Y out IOL24[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
IO_adv7513_scl A20/1 Y io IOT43[A] LVCMOS25 8 UP NA NONE OFF NA NA NA 2.5
IO_adv7513_sda A21/1 Y io IOT43[B] LVCMOS25 8 UP NA NONE OFF NA NA NA 2.5
IO_ddr_dq[0] M5/6 Y io IOL32[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[1] T3/6 Y io IOL39[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[2] M3/6 Y io IOL29[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[3] T2/6 Y io IOL33[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[4] Y1/6 Y io IOL38[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[5] U1/6 Y io IOL30[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[6] N3/6 Y io IOL31[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[7] V1/6 Y io IOL34[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[8] T1/7 Y io IOL27[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[9] K3/7 Y io IOL23[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[10] P1/7 Y io IOL26[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[11] J1/7 Y io IOL20[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[12] L5/7 Y io IOL21[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[13] H3/7 Y io IOL17[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[14] M1/7 Y io IOL25[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dq[15] H1/7 Y io IOL18[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
IO_ddr_dqs[0] IO_ddr_dqs_n[0] P4,R4/6 Y io IOL36 SSTL15D 8 UP NA NA NA NA OFF NA 1.5
IO_ddr_dqs[1] IO_ddr_dqs_n[1] L2,L1/7 Y io IOL22 SSTL15D 8 UP NA NA NA NA OFF NA 1.5

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
D5/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D6/0 - in IOT2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E6/0 - in IOT3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E7/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D4/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C4/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F6/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F7/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C5/0 - in IOT7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C6/0 - in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B1/0 - in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A1/0 - in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D7/0 - in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D8/0 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A2/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A3/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C7/0 - in IOT16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/0 - in IOT16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A4/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A5/0 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B6/0 - in IOT18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A6/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E8/0 - in IOT19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E9/0 - in IOT19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D9/0 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D10/0 - in IOT20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B7/0 - in IOT21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A7/0 - in IOT21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C9/0 - in IOT22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C10/0 - in IOT22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B8/0 - in IOT23[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A8/0 - in IOT23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A9/0 - in IOT24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A10/0 - in IOT24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E10/0 - in IOT25[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E11/0 - in IOT25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A11/0 - in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A12/0 - in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B11/0 - in IOT27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B12/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D11/1 - in IOT30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D12/1 - in IOT30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C11/1 - in IOT31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C12/1 - in IOT31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E12/1 - in IOT32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E13/1 - in IOT32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A13/1 - in IOT33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A14/1 - in IOT33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A15/1 - in IOT34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
B15/1 - in IOT34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C13/1 - in IOT35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D13/1 - in IOT35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C14/1 - in IOT36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C15/1 - in IOT36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A16/1 - in IOT37[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
B16/1 - in IOT37[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A17/1 - in IOT38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
B17/1 - in IOT38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D14/1 - in IOT39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D15/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A18/1 - in IOT40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A19/1 - in IOT40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C16/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C17/1 - in IOT41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A20/1 IO_adv7513_scl io IOT43[A] LVCMOS25 8 UP NA NONE OFF NA NA NA 2.5
A21/1 IO_adv7513_sda io IOT43[B] LVCMOS25 8 UP NA NONE OFF NA NA NA 2.5
C18/1 - in IOT44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
C19/1 - in IOT44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D16/1 - in IOT48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E16/1 - in IOT48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E14/1 - in IOT50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E15/1 - in IOT50[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D17/1 - in IOT51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
D18/1 - in IOT51[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
F16/1 - in IOT53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
F17/1 - in IOT53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
A22/1 - in IOT54[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
B22/1 - in IOT54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E17/1 - in IOT55[A] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
E18/1 - in IOT55[B] LVCMOS18 NA UP ON NONE NA NA NA NA 2.5
U6/5 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
U7/5 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W5/5 - in IOB3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W6/5 - in IOB3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V6/5 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V7/5 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y4/5 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y5/5 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V8/5 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V9/5 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y3/5 - in IOB9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AA3/5 - in IOB9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB1/5 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB2/5 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y6/5 - in IOB14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AA6/5 - in IOB14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W7/5 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W8/5 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB3/5 - in IOB17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB4/5 - in IOB17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y7/5 - in IOB18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y8/5 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V10/5 - in IOB19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
V11/5 - in IOB19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W9/5 - in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y9/5 - in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB5/5 - in IOB21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB6/5 - in IOB21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AA7/5 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB7/5 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AA8/5 - in IOB23[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB8/5 - in IOB23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W10/5 - in IOB24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
W11/5 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AA11/5 - in IOB25[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB11/5 - in IOB25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y10/5 - in IOB26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
Y11/5 - in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB9/5 - in IOB27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB10/5 - in IOB27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
AB12/4 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA12/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y12/4 - in IOB31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y13/4 - in IOB31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W12/4 - in IOB32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W13/4 - in IOB32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB13/4 - in IOB33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB14/4 - in IOB33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB15/4 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA15/4 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V12/4 - in IOB35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V13/4 - in IOB35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB16/4 - in IOB36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA16/4 - in IOB36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y14/4 - in IOB37[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y15/4 - in IOB37[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V14/4 - in IOB38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V15/4 - in IOB38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB17/4 - in IOB39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB18/4 - in IOB39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA17/4 - in IOB40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y17/4 - in IOB40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W14/4 - in IOB41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W15/4 - in IOB41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB19/4 - in IOB43[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB20/4 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y16/4 - in IOB44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W16/4 - in IOB44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y19/4 - in IOB48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y18/4 - in IOB48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V16/4 - in IOB50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U16/4 - in IOB50[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W17/4 - in IOB51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W18/4 - in IOB51[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA20/4 - in IOB53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y20/4 - in IOB53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V17/4 - in IOB54[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V18/4 - in IOB54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W19/4 O_ddr_cs_n out IOB55[A] SSTL15 8 NA NA NA NA NA NA NA 1.5
V19/4 - in IOB55[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E5/7 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F5/7 O_ddr_addr[3] out IOL2[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
B3/7 - in IOL3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B2/7 O_ddr_odt out IOL3[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
G6/7 - in IOL4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G5/7 O_ddr_addr[2] out IOL4[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
D3/7 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C3/7 O_ddr_cas_n out IOL5[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
E4/7 - in IOL6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E3/7 O_ddr_cke out IOL6[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
F4/7 O_ddr_ba[0] out IOL7[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
G4/7 - in IOL7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F3/7 O_ddr_ba[2] out IOL8[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
G3/7 - in IOL8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H5/7 O_ddr_addr[7] out IOL9[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
J5/7 - in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C2/7 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C1/7 O_ddr_we_n out IOL11[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
D1/7 O_ddr_ras_n out IOL12[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
E1/7 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F2/7 - in IOL14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G2/7 O_ddr_addr[5] out IOL14[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
F1/7 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G1/7 O_ddr_addr[0] out IOL15[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
H4/7 - in IOL16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J4/7 O_ddr_addr[9] out IOL16[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
H3/7 IO_ddr_dq[13] io IOL17[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
J3/7 - in IOL17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H2/7 - in IOL18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H1/7 IO_ddr_dq[15] io IOL18[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
J1/7 IO_ddr_dq[11] io IOL20[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
K1/7 - in IOL20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K5/7 - in IOL21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
L5/7 IO_ddr_dq[12] io IOL21[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
L2/7 IO_ddr_dqs[1] io IOL22[A] SSTL15D 8 UP NA NA NA NA OFF NA 1.5
L1/7 IO_ddr_dqs_n[1] io IOL22[B] SSTL15D 8 UP NA NA NA NA OFF NA 1.5
K3/7 IO_ddr_dq[9] io IOL23[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
L3/7 - in IOL23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K4/7 O_ddr_dqm[1] out IOL24[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
L4/7 - in IOL24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M2/7 - in IOL25[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M1/7 IO_ddr_dq[14] io IOL25[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
P1/7 IO_ddr_dq[10] io IOL26[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
N1/7 - in IOL26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R1/7 - in IOL27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T1/7 IO_ddr_dq[8] io IOL27[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
M4/6 - in IOL29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M3/6 IO_ddr_dq[2] io IOL29[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
U1/6 IO_ddr_dq[5] io IOL30[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
U2/6 - in IOL30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
N4/6 - in IOL31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
N3/6 IO_ddr_dq[6] io IOL31[B] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
M5/6 IO_ddr_dq[0] io IOL32[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
N5/6 - in IOL32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T2/6 IO_ddr_dq[3] io IOL33[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
R2/6 - in IOL33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V1/6 IO_ddr_dq[7] io IOL34[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
W1/6 - in IOL34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P3/6 - in IOL35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R3/6 O_ddr_dqm[0] out IOL35[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
P4/6 IO_ddr_dqs[0] io IOL36[A] SSTL15D 8 UP NA NA NA NA OFF NA 1.5
R4/6 IO_ddr_dqs_n[0] io IOL36[B] SSTL15D 8 UP NA NA NA NA OFF NA 1.5
Y1/6 IO_ddr_dq[4] io IOL38[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
Y2/6 - in IOL38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T3/6 IO_ddr_dq[1] io IOL39[A] SSTL15 8 UP NA NA NA INTERNAL OFF NA 1.5
U3/6 - in IOL39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V3/6 O_ddr_addr[4] out IOL44[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
W3/6 - in IOL44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA1/6 O_ddr_addr[13] out IOL45[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
AA2/6 - in IOL45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P5/6 - in IOL47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R5/6 O_ddr_addr[10] out IOL47[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
T4/6 - in IOL48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U4/6 O_ddr_ba[1] out IOL48[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
V4/6 - in IOL50[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
W4/6 O_ddr_reset_n out IOL50[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
V5/6 - in IOL53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U5/6 O_ddr_addr[1] out IOL53[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
T5/6 O_ddr_addr[12] out IOL54[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
T6/6 - in IOL54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F18/2 O_adv7513_data[14] out IOR2[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
F19/2 O_adv7513_data[16] out IOR2[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
E19/2 O_adv7513_data[22] out IOR3[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
E20/2 O_adv7513_data[20] out IOR3[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
G17/2 - in IOR4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
G18/2 O_adv7513_data[10] out IOR4[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
H19/2 O_adv7513_data[7] out IOR5[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
H18/2 O_adv7513_data[8] out IOR5[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
D19/2 - in IOR6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
D20/2 O_adv7513_data[23] out IOR6[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
B20/2 - in IOR7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C20/2 - in IOR7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
B21/2 - in IOR8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C21/2 - in IOR8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
J18/2 O_adv7513_data[4] out IOR9[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
K18/2 O_adv7513_data[0] out IOR9[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
G19/2 O_adv7513_data[11] out IOR11[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
G20/2 O_adv7513_data[12] out IOR11[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
F20/2 O_adv7513_data[17] out IOR12[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
F21/2 O_adv7513_data[19] out IOR12[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
C22/2 - in IOR14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
D22/2 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
H20/2 O_adv7513_data[9] out IOR15[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
H21/2 O_adv7513_clk out IOR15[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
J19/2 O_adv7513_data[3] out IOR16[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
J20/2 O_adv7513_data[5] out IOR16[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
F22/2 O_adv7513_data[18] out IOR17[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
E22/2 O_adv7513_data[21] out IOR17[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
G21/2 O_adv7513_data[15] out IOR18[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
G22/2 O_adv7513_data[13] out IOR18[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
H22/2 O_adv7513_data[6] out IOR20[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
J22/2 O_adv7513_data[2] out IOR20[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
K22/2 O_adv7513_hs out IOR21[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
L22/2 I_rst_n in IOR21[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
K19/2 O_adv7513_data[1] out IOR22[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
L19/2 O_adv7513_vs out IOR22[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
K20/2 O_adv7513_de out IOR23[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
L20/2 - in IOR23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L21/2 - in IOR24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M21/2 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M22/2 - out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 3.3
N22/2 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N20/2 - in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M20/2 - in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M19/2 I_clk in IOR27[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
N19/2 - in IOR27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P22/3 O_ddr_clk out IOR29[A] SSTL15D 8 NA NA NA NA NA OFF NA 1.5
R22/3 O_ddr_clk_n out IOR29[B] SSTL15D 8 NA NA NA NA NA OFF NA 1.5
T22/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U22/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U21/3 - in IOR31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T21/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
L18/3 - in IOR32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M18/3 - in IOR32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P19/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P20/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
N18/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P18/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R20/3 - in IOR35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R21/3 - in IOR35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
V22/3 O_led[2] out IOR36[A] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
W22/3 O_led[1] out IOR36[B] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
T20/3 - in IOR38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U20/3 O_led[3] out IOR38[B] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
T19/3 - in IOR39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R19/3 - in IOR39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y22/3 - in IOR44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA22/3 O_ddr_addr[6] out IOR44[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
R18/3 - in IOR45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T18/3 - in IOR45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
Y21/3 - in IOR47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AA21/3 O_ddr_addr[11] out IOR47[B] SSTL15 8 NA NA NA NA NA OFF NA 1.5
W20/3 O_led[0] out IOR48[A] LVCMOS15 8 UP NA NA OFF NA OFF NA 1.5
V20/3 - in IOR48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
AB22/3 O_ddr_addr[8] out IOR50[A] SSTL15 8 NA NA NA NA NA OFF NA 1.5
AB21/3 I_key1 in IOR50[B] LVCMOS15 NA UP ON NONE NA NA OFF NA 1.5
T17/3 - in IOR53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U17/3 - in IOR53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U19/3 - in IOR54[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
U18/3 - in IOR54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5