PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\dk_video.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18EQ144C8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 09:25:22 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.355s, Elapsed time = 0h 0m 0.355s Placement Phase 1: CPU time = 0h 0m 0.294s, Elapsed time = 0h 0m 0.294s Placement Phase 2: CPU time = 0h 0m 0.34s, Elapsed time = 0h 0m 0.339s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.175s, Elapsed time = 0h 0m 0.175s Routing Phase 2: CPU time = 0h 0m 0.959s, Elapsed time = 0h 0m 0.959s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 641MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1555/20736 8%
    --LUT,ALU,ROM16 1501(1380 LUT, 121 ALU, 0 ROM16) -
    --SSRAM(RAM16) 9 -
Register 1087/16077 7%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 980/15552 7%
    --I/O Register as Latch 0/525 0%
    --I/O Register as FF 107/525 21%
CLS 1095/10368 11%
I/O Port 35 -
I/O Buf 35 -
    --Input Buf 2 -
    --Output Buf 33 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 8 SDPB
1 SDPX9B
20%
DSP 00%
PLL 2/4 50%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DQS 0/7 0%
DHCEN 0/16 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 9/19(47%)
bank 1 8/12(66%)
bank 2 7/12(58%)
bank 3 10/24(41%)
bank 4 0/17(0%)
bank 5 0/16(0%)
bank 6 0/12(0%)
bank 7 1/8(12%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 4/8(50%)
LW 6/8(75%)
GCLK_PIN 2/6(34%)
PLL 2/4(50%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
I_clk_d PRIMARY TR BR BL
O_clk_d PRIMARY TR TL BR
O_sdram_clk_d PRIMARY TR
sdrc_clk PRIMARY TR TL BR BL
I_rst_n_d LW -
n316_6 LW -
O_led_d_0[0] LW -
Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r[1] LW -
Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r[1] LW -
SDRAM_controller_top_SIP_inst/sdrc_top_inst/U0/Ctrl_wr_data_valid LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
I_clk 6/7 Y in IOL7[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
I_rst_n 79/3 Y in IOR49[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
O_led[0] 129/0 Y out IOT17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_led[1] 128/0 Y out IOT19[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_led[2] 126/0 Y out IOT23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_led[3] 125/0 Y out IOT22[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_r[0] 76/3 Y out IOR50[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[1] 78/3 Y out IOR50[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[2] 80/3 Y out IOR49[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[3] 83/3 Y out IOR42[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[4] 84/3 Y out IOR42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[5] 85/3 Y out IOR38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[6] 86/3 Y out IOR38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_r[7] 87/3 Y out IOR36[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[0] 92/3 Y out IOR35[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[1] 97/2 Y out IOR27[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[2] 98/2 Y out IOR27[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[3] 99/2 Y out IOR22[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[4] 100/2 Y out IOR22[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[5] 101/2 Y out IOR20[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[6] 102/2 Y out IOR20[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_g[7] 105/2 Y out IOR7[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
O_data_b[0] 111/1 Y out IOT50[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[1] 112/1 Y out IOT48[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[2] 113/1 Y out IOT48[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[3] 114/1 Y out IOT42[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[4] 115/1 Y out IOT42[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[5] 116/1 Y out IOT40[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[6] 117/1 Y out IOT40[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_data_b[7] 118/1 Y out IOT38[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_vs 133/0 Y out IOT12[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_hs 132/0 Y out IOT14[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_clk 135/0 Y out IOT7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_sync_n 137/0 Y out IOT6[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
O_blank_n 136/0 Y out IOT7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
141/0 - in IOT2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
140/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
139/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
138/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
137/0 O_sync_n out IOT6[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
136/0 O_blank_n out IOT7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
135/0 O_clk out IOT7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
134/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
133/0 O_vs out IOT12[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
132/0 O_hs out IOT14[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
131/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
130/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
129/0 O_led[0] out IOT17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
128/0 O_led[1] out IOT19[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
125/0 O_led[3] out IOT22[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
126/0 O_led[2] out IOT23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
124/0 - in IOT23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
123/0 - in IOT27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
122/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
121/1 - in IOT30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
120/1 - in IOT30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
119/1 - in IOT38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
118/1 O_data_b[7] out IOT38[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
117/1 O_data_b[6] out IOT40[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
116/1 O_data_b[5] out IOT40[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
115/1 O_data_b[4] out IOT42[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
114/1 O_data_b[3] out IOT42[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
113/1 O_data_b[2] out IOT48[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
112/1 O_data_b[1] out IOT48[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
111/1 O_data_b[0] out IOT50[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
110/1 - in IOT50[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
38/5 - in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/5 - in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/5 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/5 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/5 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/5 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/5 - in IOB12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/5 - in IOB12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
46/5 - in IOB14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/5 - in IOB14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/5 - in IOB17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/5 - in IOB17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/5 - in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
51/5 - in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/5 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/5 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/4 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
58/4 - in IOB33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/4 - in IOB33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/4 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/4 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/4 - in IOB38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/4 - in IOB38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
64/4 - in IOB40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
65/4 - in IOB40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
66/4 - in IOB42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
67/4 - in IOB42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
68/4 - in IOB48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/4 - in IOB48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/4 - in IOB53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/4 - in IOB53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
72/4 - in IOB55[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/7 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
4/7 - in IOL2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
6/7 I_clk in IOL7[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
7/7 - in IOL7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
9/7 - in IOL22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
10/7 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
11/7 - in IOL27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
12/7 - in IOL27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
25/6 - in IOL29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
26/6 - in IOL29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
23/6 - in IOL32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
24/6 - in IOL32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
27/6 - in IOL33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
28/6 - in IOL33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
29/6 - in IOL36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
30/6 - in IOL36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
32/6 - in IOL42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
33/6 - in IOL42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
34/6 - in IOL45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
35/6 - in IOL45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
106/2 - in IOR7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
105/2 O_data_g[7] out IOR7[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
102/2 O_data_g[6] out IOR20[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
101/2 O_data_g[5] out IOR20[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
100/2 O_data_g[4] out IOR22[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
99/2 O_data_g[3] out IOR22[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
18/2 - out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 3.3
13/2 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
14/2 - in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
16/2 - in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
98/2 O_data_g[2] out IOR27[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
97/2 O_data_g[1] out IOR27[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
144/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
142/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
143/3 - in IOR31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
20/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
22/3 - in IOR32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
21/3 - in IOR32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
96/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
95/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
94/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
93/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
92/3 O_data_g[0] out IOR35[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
90/3 - in IOR35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
88/3 - in IOR36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
87/3 O_data_r[7] out IOR36[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
86/3 O_data_r[6] out IOR38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
85/3 O_data_r[5] out IOR38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
15/3 - in IOR39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
84/3 O_data_r[4] out IOR42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
83/3 O_data_r[3] out IOR42[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
82/3 - in IOR45[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
80/3 O_data_r[2] out IOR49[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
79/3 I_rst_n in IOR49[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
78/3 O_data_r[1] out IOR50[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
76/3 O_data_r[0] out IOR50[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3