Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\SDRAM_controller_top_SIP\temp\SDRC_EMBEDDED\sdrc_defines.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\SDRAM_controller_top_SIP.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\sdrc_control_fsm.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\sdrc_user_interface.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\sdrc_autorefresh.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\sdrc_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\SDRC_EMB\data\GENERAL\top_defines.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2AR-LV18EQ144C8/I7 |
Device | GW2AR-18 |
Device Version | C |
Created Time | Wed Jan 10 09:24:50 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | SDRAM_controller_top_SIP |
Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.213s, Peak memory usage = 41.148MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 41.148MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 41.148MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 41.148MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 41.148MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 41.148MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.148MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 41.148MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.148MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 41.148MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 41.148MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 41.148MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.906s, Elapsed time = 0h 0m 0.941s, Peak memory usage = 70.879MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 70.879MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 70.879MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 70.879MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 108 |
Embedded Port | 55 |
I/O Buf | 163 |
    IBUF | 72 |
    OBUF | 59 |
    IOBUF | 32 |
Register | 362 |
    DFF | 38 |
    DFFE | 159 |
    DFFS | 14 |
    DFFR | 39 |
    DFFP | 4 |
    DFFPE | 3 |
    DFFC | 57 |
    DFFCE | 48 |
LUT | 359 |
    LUT2 | 46 |
    LUT3 | 84 |
    LUT4 | 229 |
ALU | 50 |
    ALU | 50 |
SSRAM | 9 |
    RAM16S4 | 9 |
INV | 17 |
    INV | 17 |
BSRAM | 1 |
    SDPX9B | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 480(376 LUT, 50 ALU, 9 RAM16) / 20736 | 3% |
Register | 362 / 16077 | 3% |
  --Register as Latch | 0 / 16077 | 0% |
  --Register as FF | 362 / 16077 | 3% |
BSRAM | 1 / 46 | 3% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
I_sdrc_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_sdrc_clk_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | I_sdrc_clk | 100.0(MHz) | 192.2(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.798 |
Data Arrival Time | 6.030 |
Data Required Time | 10.828 |
From | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4 |
To | sdrc_top_inst/U1/Count_data_len_0_wr_5_s4 |
Launch Clk | I_sdrc_clk[R] |
Latch Clk | I_sdrc_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_sdrc_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/Q |
1.332 | 0.237 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s16/I1 |
1.901 | 0.570 | tINS | FR | 1 | sdrc_top_inst/U1/n435_s16/COUT |
1.901 | 0.000 | tNET | RR | 2 | sdrc_top_inst/U1/n435_s17/CIN |
1.937 | 0.035 | tINS | RF | 1 | sdrc_top_inst/U1/n435_s17/COUT |
1.937 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s18/CIN |
1.972 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s18/COUT |
1.972 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s19/CIN |
2.007 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s19/COUT |
2.007 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s20/CIN |
2.042 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s20/COUT |
2.042 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s21/CIN |
2.078 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s21/COUT |
2.078 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s22/CIN |
2.113 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s22/COUT |
2.350 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/I2 |
2.803 | 0.453 | tINS | FF | 2 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/F |
3.040 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/I0 |
3.557 | 0.517 | tINS | FF | 7 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/F |
3.794 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n657_s14/I0 |
4.311 | 0.517 | tINS | FF | 3 | sdrc_top_inst/U1/n657_s14/F |
4.548 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n654_s11/I2 |
5.001 | 0.453 | tINS | FF | 1 | sdrc_top_inst/U1/n654_s11/F |
5.238 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n654_s10/I1 |
5.793 | 0.555 | tINS | FF | 1 | sdrc_top_inst/U1/n654_s10/F |
6.030 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_5_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_sdrc_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_5_s4/CLK |
10.828 | -0.035 | tSu | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_5_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 9 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 3.276, 63.404%; route: 1.659, 32.106%; tC2Q: 0.232, 4.490% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | 5.526 |
Data Arrival Time | 5.302 |
Data Required Time | 10.828 |
From | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4 |
To | sdrc_top_inst/U1/Count_data_len_0_wr_3_s4 |
Launch Clk | I_sdrc_clk[R] |
Latch Clk | I_sdrc_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_sdrc_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/Q |
1.332 | 0.237 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s16/I1 |
1.901 | 0.570 | tINS | FR | 1 | sdrc_top_inst/U1/n435_s16/COUT |
1.901 | 0.000 | tNET | RR | 2 | sdrc_top_inst/U1/n435_s17/CIN |
1.937 | 0.035 | tINS | RF | 1 | sdrc_top_inst/U1/n435_s17/COUT |
1.937 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s18/CIN |
1.972 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s18/COUT |
1.972 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s19/CIN |
2.007 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s19/COUT |
2.007 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s20/CIN |
2.042 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s20/COUT |
2.042 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s21/CIN |
2.078 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s21/COUT |
2.078 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s22/CIN |
2.113 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s22/COUT |
2.350 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/I2 |
2.803 | 0.453 | tINS | FF | 2 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/F |
3.040 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/I0 |
3.557 | 0.517 | tINS | FF | 7 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/F |
3.794 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n657_s14/I0 |
4.311 | 0.517 | tINS | FF | 3 | sdrc_top_inst/U1/n657_s14/F |
4.548 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n660_s10/I0 |
5.065 | 0.517 | tINS | FF | 1 | sdrc_top_inst/U1/n660_s10/F |
5.302 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_3_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_sdrc_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_3_s4/CLK |
10.828 | -0.035 | tSu | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_3_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.785, 62.741%; route: 1.422, 32.033%; tC2Q: 0.232, 5.226% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | 5.590 |
Data Arrival Time | 5.238 |
Data Required Time | 10.828 |
From | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4 |
To | sdrc_top_inst/U1/Count_data_len_0_wr_4_s4 |
Launch Clk | I_sdrc_clk[R] |
Latch Clk | I_sdrc_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_sdrc_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/Q |
1.332 | 0.237 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s16/I1 |
1.901 | 0.570 | tINS | FR | 1 | sdrc_top_inst/U1/n435_s16/COUT |
1.901 | 0.000 | tNET | RR | 2 | sdrc_top_inst/U1/n435_s17/CIN |
1.937 | 0.035 | tINS | RF | 1 | sdrc_top_inst/U1/n435_s17/COUT |
1.937 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s18/CIN |
1.972 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s18/COUT |
1.972 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s19/CIN |
2.007 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s19/COUT |
2.007 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s20/CIN |
2.042 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s20/COUT |
2.042 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s21/CIN |
2.078 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s21/COUT |
2.078 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s22/CIN |
2.113 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s22/COUT |
2.350 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/I2 |
2.803 | 0.453 | tINS | FF | 2 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/F |
3.040 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/I0 |
3.557 | 0.517 | tINS | FF | 7 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/F |
3.794 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n657_s14/I0 |
4.311 | 0.517 | tINS | FF | 3 | sdrc_top_inst/U1/n657_s14/F |
4.548 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n657_s10/I2 |
5.001 | 0.453 | tINS | FF | 1 | sdrc_top_inst/U1/n657_s10/F |
5.238 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_4_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_sdrc_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_4_s4/CLK |
10.828 | -0.035 | tSu | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_4_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.721, 62.196%; route: 1.422, 32.501%; tC2Q: 0.232, 5.303% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | 5.590 |
Data Arrival Time | 5.238 |
Data Required Time | 10.828 |
From | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4 |
To | sdrc_top_inst/U1/Count_data_len_0_wr_7_s4 |
Launch Clk | I_sdrc_clk[R] |
Latch Clk | I_sdrc_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_sdrc_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/CLK |
1.095 | 0.232 | tC2Q | RF | 7 | sdrc_top_inst/U1/Count_data_len_0_wr_0_s4/Q |
1.332 | 0.237 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s16/I1 |
1.901 | 0.570 | tINS | FR | 1 | sdrc_top_inst/U1/n435_s16/COUT |
1.901 | 0.000 | tNET | RR | 2 | sdrc_top_inst/U1/n435_s17/CIN |
1.937 | 0.035 | tINS | RF | 1 | sdrc_top_inst/U1/n435_s17/COUT |
1.937 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s18/CIN |
1.972 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s18/COUT |
1.972 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s19/CIN |
2.007 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s19/COUT |
2.007 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s20/CIN |
2.042 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s20/COUT |
2.042 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s21/CIN |
2.078 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s21/COUT |
2.078 | 0.000 | tNET | FF | 2 | sdrc_top_inst/U1/n435_s22/CIN |
2.113 | 0.035 | tINS | FF | 1 | sdrc_top_inst/U1/n435_s22/COUT |
2.350 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/I2 |
2.803 | 0.453 | tINS | FF | 2 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s7/F |
3.040 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/I0 |
3.557 | 0.517 | tINS | FF | 7 | sdrc_top_inst/U1/O_ctrl_fsm_data_31_s6/F |
3.794 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n648_s13/I0 |
4.311 | 0.517 | tINS | FF | 1 | sdrc_top_inst/U1/n648_s13/F |
4.548 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/n648_s11/I2 |
5.001 | 0.453 | tINS | FF | 1 | sdrc_top_inst/U1/n648_s11/F |
5.238 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_7_s4/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_sdrc_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_7_s4/CLK |
10.828 | -0.035 | tSu | 1 | sdrc_top_inst/U1/Count_data_len_0_wr_7_s4 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.721, 62.196%; route: 1.422, 32.501%; tC2Q: 0.232, 5.303% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | 5.720 |
Data Arrival Time | 5.108 |
Data Required Time | 10.828 |
From | sdrc_top_inst/U0/Count_cmd_delay_2_s0 |
To | sdrc_top_inst/U0/Cmd_fsm_state.SDRC_STATE_WRITE_WITHOUT_AUTOPRE_s0 |
Launch Clk | I_sdrc_clk[R] |
Latch Clk | I_sdrc_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | I_sdrc_clk | |||
0.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
0.683 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U0/Count_cmd_delay_2_s0/CLK |
1.095 | 0.232 | tC2Q | RF | 4 | sdrc_top_inst/U0/Count_cmd_delay_2_s0/Q |
1.332 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/O_ctrl_fsm_wrd_done_s4/I1 |
1.887 | 0.555 | tINS | FF | 7 | sdrc_top_inst/U0/O_ctrl_fsm_wrd_done_s4/F |
2.124 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/n596_s23/I1 |
2.679 | 0.555 | tINS | FF | 2 | sdrc_top_inst/U0/n596_s23/F |
2.916 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/n596_s20/I3 |
3.287 | 0.371 | tINS | FF | 9 | sdrc_top_inst/U0/n596_s20/F |
3.524 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/n600_s19/I1 |
4.079 | 0.555 | tINS | FF | 3 | sdrc_top_inst/U0/n600_s19/F |
4.316 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/n608_s19/I1 |
4.871 | 0.555 | tINS | FF | 1 | sdrc_top_inst/U0/n608_s19/F |
5.108 | 0.237 | tNET | FF | 1 | sdrc_top_inst/U0/Cmd_fsm_state.SDRC_STATE_WRITE_WITHOUT_AUTOPRE_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | I_sdrc_clk | |||
10.000 | 0.000 | tCL | RR | 1 | I_sdrc_clk_ibuf/I |
10.682 | 0.683 | tINS | RR | 373 | I_sdrc_clk_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | sdrc_top_inst/U0/Cmd_fsm_state.SDRC_STATE_WRITE_WITHOUT_AUTOPRE_s0/CLK |
10.828 | -0.035 | tSu | 1 | sdrc_top_inst/U0/Cmd_fsm_state.SDRC_STATE_WRITE_WITHOUT_AUTOPRE_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 2.591, 61.037%; route: 1.422, 33.498%; tC2Q: 0.232, 5.465% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |