Report Title |
Power Analysis Report |
Design File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\impl\gwsynthesis\dk_video.vg |
Physical Constraints File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.cst |
Timing Constraints File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.sdc |
Tool Version |
V1.9.9.01 (64-bit) |
Part Number |
GW2AR-LV18QN88PC8/I7 |
Device |
GW2AR-18 |
Device Version |
C |
Created Time |
Wed Jan 10 10:16:27 2024
|
Legal Announcement |
Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
292.231 |
Quiescent Power (mW) |
91.896 |
Dynamic Power (mW) |
200.335 |
Psram Power (mW) |
86.000 |
Junction Temperature |
31.268 |
Theta JA |
21.450 |
Max Allowed Ambient Temperature |
78.732 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.000 |
167.532 |
61.497 |
229.029 |
VCCX |
2.500 |
3.406 |
11.364 |
36.924 |
VCCIO18 |
1.800 |
1.971 |
0.706 |
4.819 |
VCCIO25 |
2.500 |
7.769 |
0.123 |
19.730 |
VCCIO33 |
3.300 |
0.399 |
0.125 |
1.730 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
2.498 |
NA |
8.443 |
IO |
42.754
| 6.131
| 22.123
|
BSRAM |
68.033
| NA |
NA |
PLL |
55.779
| NA |
NA |
DLL |
37.324
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
video_top |
163.634 |
163.634(163.584) |
video_top/DVI_TX_Top_inst/ |
0.547 |
0.547(0.547) |
video_top/DVI_TX_Top_inst/rgb2dvi_inst/ |
0.547 |
0.547(0.547) |
video_top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/ |
0.182 |
0.182(0.000) |
video_top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/ |
0.182 |
0.182(0.000) |
video_top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/ |
0.183 |
0.183(0.000) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/ |
64.947 |
64.947(64.947) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/ |
64.947 |
64.947(27.416) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/ |
0.531 |
0.531(0.000) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_sync/ |
0.023 |
0.023(0.000) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/ |
26.863 |
26.863(26.779) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/ |
13.420 |
13.420(0.000) |
video_top/PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/ |
13.360 |
13.360(0.000) |
video_top/Video_Frame_Buffer_Top_inst/ |
42.136 |
42.136(42.136) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/ |
42.136 |
42.136(42.136) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/ |
42.010 |
42.010(42.010) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/ |
25.016 |
25.016(24.928) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/ |
24.928 |
24.928(0.000) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/ |
16.994 |
16.994(16.934) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/ |
16.934 |
16.934(0.000) |
video_top/Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/ |
0.127 |
0.127(0.000) |
video_top/gowin_rpll_inst/ |
16.946 |
16.946(0.000) |
video_top/syn_gen_inst/ |
0.074 |
0.074(0.000) |
video_top/testpattern_inst/ |
0.101 |
0.101(0.000) |
video_top/u_tmds_pll/ |
38.834 |
38.834(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
I_clk |
27.000 |
59.826 |
dma_clk |
80.998 |
53.938 |
u_clkdiv/CLKOUT.default_gen_clk |
74.250 |
12.570 |
NO CLOCK DOMAIN |
0.000 |
0.000 |
memory_clk |
161.996 |
37.352 |
u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk |
371.250 |
0.025 |