Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\adv7513_iic_init.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\ddr3_memory_interface\ddr3_memory_interface.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\gowin_rpll\ddr3_rpll.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\gowin_rpll\pix_rpll.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\i2c_master\i2c_master.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\key_debounceN.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\syn_code\syn_gen.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\testpattern.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\video_frame_buffer\video_frame_buffer.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_DDR3_RefDesign\project\src\video_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Wed Jan 10 10:27:15 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 643.262MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 643.262MB
    Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.175s, Peak memory usage = 643.262MB
    Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.33s, Peak memory usage = 643.262MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 643.262MB
    Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 643.262MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 643.262MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 643.262MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.258s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.39s, Peak memory usage = 643.262MB
Generate output files:
    CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.493s, Peak memory usage = 643.262MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 643.262MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 85
I/O Buf 82
    IBUF 3
    OBUF 56
    TBUF 2
    IOBUF 18
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 4570
    DFF 235
    DFFE 247
    DFFS 9
    DFFR 67
    DFFP 111
    DFFPE 11
    DFFC 3101
    DFFCE 789
LUT 3915
    LUT2 852
    LUT3 1295
    LUT4 1768
ALU 203
    ALU 203
SSRAM 137
    RAM16S4 44
    RAM16SDP4 93
INV 38
    INV 38
IOLOGIC 76
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    IODELAY 16
BSRAM 12
    SDPB 8
    SDPX9B 4
CLOCK 6
    CLKDIV 1
    DQS 2
    DHCEN 1
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 4978(3953 LUT, 203 ALU, 137 RAM16) / 20736 25%
Register 4570 / 16509 28%
  --Register as Latch 0 / 16509 0%
  --Register as FF 4570 / 16509 28%
BSRAM 12 / 46 27%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 20.000 50.0 0.000 10.000 I_clk_ibuf/I
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O
DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1984_6 Base 10.000 100.0 0.000 5.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1984_s2/O
pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Generated 13.333 75.0 0.000 6.667 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUT
pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 13.333 75.0 1.667 8.333 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTP
pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 26.667 37.5 0.000 13.333 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD
pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 40.000 25.0 0.000 20.000 I_clk_ibuf/I I_clk pix_rpll_inst/rpll_inst/CLKOUTD3
ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Generated 3.333 300.0 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUT
ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 3.333 300.0 0.000 1.667 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTP
ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 6.667 150.0 0.000 3.333 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD
ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 10.000 100.0 0.000 5.000 I_clk_ibuf/I I_clk ddr3_rpll_inst/rpll_inst/CLKOUTD3
DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 13.333 75.0 0.000 6.667 ddr3_rpll_inst/rpll_inst/CLKOUT ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 50.0(MHz) 224.0(MHz) 6 TOP
2 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 100.0(MHz) 1984.1(MHz) 1 TOP
3 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 100.0(MHz) 1984.1(MHz) 1 TOP
4 Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 100.0(MHz) 1984.1(MHz) 1 TOP
5 pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk 75.0(MHz) 190.2(MHz) 9 TOP
6 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk 300.0(MHz) 1364.3(MHz) 1 TOP
7 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 75.0(MHz) 771.6(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.088
Data Arrival Time 14.701
Data Required Time 13.614
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk
11.029 1.029 tCL RR 1 ddr3_rpll_inst/rpll_inst/CLKOUT
11.209 0.180 tNET RR 3 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
11.391 0.182 tINS RR 64 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
11.571 0.180 tNET RR 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/CLKIN
11.964 0.393 tINS RF 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.201 0.237 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
12.771 0.570 tINS FR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
12.771 0.000 tNET RR 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
12.806 0.035 tINS RF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
12.806 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
12.842 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
12.842 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
12.877 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
12.877 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
12.912 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
12.912 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
12.947 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
12.947 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
12.982 0.035 tINS FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
13.219 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
13.774 0.555 tINS FF 9 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
14.011 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2
14.464 0.453 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
14.701 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.333 0.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
13.504 0.170 tCL RR 4042 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.684 0.180 tNET RR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
13.649 -0.035 tUnc DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
13.614 -0.035 tSu 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 2.182, 65.923%; route: 0.948, 28.639%; tC2Q: 0.180, 5.438%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 2

Path Summary:
Slack -1.088
Data Arrival Time 14.701
Data Required Time 13.614
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk
11.029 1.029 tCL RR 1 ddr3_rpll_inst/rpll_inst/CLKOUT
11.209 0.180 tNET RR 3 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
11.391 0.182 tINS RR 64 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
11.571 0.180 tNET RR 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/CLKIN
11.964 0.393 tINS RF 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.201 0.237 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
12.771 0.570 tINS FR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
12.771 0.000 tNET RR 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
12.806 0.035 tINS RF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
12.806 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
12.842 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
12.842 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
12.877 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
12.877 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
12.912 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
12.912 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
12.947 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
12.947 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
12.982 0.035 tINS FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
13.219 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
13.774 0.555 tINS FF 9 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
14.011 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2
14.464 0.453 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
14.701 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.333 0.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
13.504 0.170 tCL RR 4042 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.684 0.180 tNET RR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
13.649 -0.035 tUnc DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
13.614 -0.035 tSu 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 2.182, 65.923%; route: 0.948, 28.639%; tC2Q: 0.180, 5.438%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 3

Path Summary:
Slack -1.088
Data Arrival Time 14.701
Data Required Time 13.614
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk
11.029 1.029 tCL RR 1 ddr3_rpll_inst/rpll_inst/CLKOUT
11.209 0.180 tNET RR 3 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
11.391 0.182 tINS RR 64 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
11.571 0.180 tNET RR 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/CLKIN
11.964 0.393 tINS RF 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.201 0.237 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
12.771 0.570 tINS FR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
12.771 0.000 tNET RR 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
12.806 0.035 tINS RF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
12.806 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
12.842 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
12.842 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
12.877 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
12.877 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
12.912 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
12.912 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
12.947 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
12.947 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
12.982 0.035 tINS FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
13.219 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
13.774 0.555 tINS FF 9 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
14.011 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2
14.464 0.453 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
14.701 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.333 0.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
13.504 0.170 tCL RR 4042 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.684 0.180 tNET RR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
13.649 -0.035 tUnc DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
13.614 -0.035 tSu 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 2.182, 65.923%; route: 0.948, 28.639%; tC2Q: 0.180, 5.438%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 4

Path Summary:
Slack -1.088
Data Arrival Time 14.701
Data Required Time 13.614
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk
11.029 1.029 tCL RR 1 ddr3_rpll_inst/rpll_inst/CLKOUT
11.209 0.180 tNET RR 3 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
11.391 0.182 tINS RR 64 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
11.571 0.180 tNET RR 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/CLKIN
11.964 0.393 tINS RF 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.201 0.237 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
12.771 0.570 tINS FR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
12.771 0.000 tNET RR 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
12.806 0.035 tINS RF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
12.806 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
12.842 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
12.842 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
12.877 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
12.877 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
12.912 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
12.912 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
12.947 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
12.947 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
12.982 0.035 tINS FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
13.219 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
13.774 0.555 tINS FF 9 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
14.011 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I2
14.464 0.453 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
14.701 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.333 0.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
13.504 0.170 tCL RR 4042 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.684 0.180 tNET RR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
13.649 -0.035 tUnc DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
13.614 -0.035 tSu 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 2.182, 65.923%; route: 0.948, 28.639%; tC2Q: 0.180, 5.438%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%

Path 5

Path Summary:
Slack -1.088
Data Arrival Time 14.701
Data Required Time 13.614
From DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll
To DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk
11.029 1.029 tCL RR 1 ddr3_rpll_inst/rpll_inst/CLKOUT
11.209 0.180 tNET RR 3 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
11.391 0.182 tINS RR 64 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
11.571 0.180 tNET RR 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/CLKIN
11.964 0.393 tINS RF 8 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
12.201 0.237 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
12.771 0.570 tINS FR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
12.771 0.000 tNET RR 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
12.806 0.035 tINS RF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
12.806 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
12.842 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
12.842 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
12.877 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
12.877 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
12.912 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
12.912 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
12.947 0.035 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
12.947 0.000 tNET FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
12.982 0.035 tINS FF 2 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
13.219 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
13.774 0.555 tINS FF 9 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
14.011 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I2
14.464 0.453 tINS FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
14.701 0.237 tNET FF 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.333 0.000 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
13.504 0.170 tCL RR 4042 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
13.684 0.180 tNET RR 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
13.649 -0.035 tUnc DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
13.614 -0.035 tSu 1 DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Path Statistics:
Clock Skew: -1.041
Setup Relationship: 3.333
Logic Level: 6
Arrival Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%
Arrival Data Path Delay: cell: 2.182, 65.923%; route: 0.948, 28.639%; tC2Q: 0.180, 5.438%
Required Clock Path Delay: cell: 0.182, 50.276%; route: 0.180, 49.724%