Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dvi_tx_top\dvi_tx_top.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\gowin_rpll\gowin_rpll.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\gowin_rpll\TMDS_PLL.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\psram_memory_interface_hs\psram_memory_interface_hs.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\syn_code\syn_gen.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\testpattern.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\video_frame_buffer\video_frame_buffer.v
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\video_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 10:16:20 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.518s, Peak memory usage = 643.262MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 643.262MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 643.262MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 643.262MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 643.262MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 643.262MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 643.262MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 643.262MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 643.262MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 643.262MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 643.262MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 643.262MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 12
Embedded Port 26
I/O Buf 32
    IBUF 2
    OBUF 6
    IOBUF 18
    TLVDS_OBUF 4
    ELVDS_OBUF 2
Register 1141
    DFF 3
    DFFP 47
    DFFPE 8
    DFFC 697
    DFFCE 386
LUT 2020
    LUT2 361
    LUT3 690
    LUT4 969
ALU 156
    ALU 156
INV 21
    INV 21
IOLOGIC 60
    IDES4 16
    OSER4 22
    OSER10 4
    IODELAY 18
BSRAM 6
    SDPB 4
    SDPX9B 2
CLOCK 5
    CLKDIV 2
    DHCEN 1
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 2197(2041 LUT, 156 ALU) / 20736 11%
Register 1141 / 15828 8%
  --Register as Latch 0 / 15828 0%
  --Register as FF 1141 / 15828 8%
BSRAM 6 / 46 14%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 37.037 27.0 0.000 18.519 I_clk_ibuf/I
Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O
Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O
Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 Base 10.000 100.0 0.000 5.000 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O
gowin_rpll_inst/rpll_inst/CLKOUT.default_gen_clk Generated 6.173 162.0 0.000 3.086 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUT
gowin_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 6.173 162.0 0.000 3.086 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTP
gowin_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 12.346 81.0 0.000 6.173 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTD
gowin_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 18.519 54.0 0.000 9.259 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTD3
u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk Generated 2.694 371.3 0.000 1.347 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUT
u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.694 371.3 0.000 1.347 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTP
u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.387 185.6 0.000 2.694 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTD
u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.8 0.000 4.040 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTD3
u_clkdiv/CLKOUT.default_gen_clk Generated 13.468 74.3 0.000 6.734 u_tmds_pll/rpll_inst/CLKOUT u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk u_clkdiv/CLKOUT
PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk Generated 12.346 81.0 0.000 6.173 gowin_rpll_inst/rpll_inst/CLKOUT gowin_rpll_inst/rpll_inst/CLKOUT.default_gen_clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 27.0(MHz) 224.0(MHz) 6 TOP
2 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 100.0(MHz) 1984.1(MHz) 1 TOP
3 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 100.0(MHz) 1984.1(MHz) 1 TOP
4 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 100.0(MHz) 1984.1(MHz) 1 TOP
5 u_clkdiv/CLKOUT.default_gen_clk 74.3(MHz) 128.9(MHz) 11 TOP
6 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk 81.0(MHz) 174.5(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.583
Data Arrival Time 13.165
Data Required Time 13.749
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_0_s1
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1
Launch Clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
12.346 0.000 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk
12.516 0.170 tCL RR 728 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.696 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_0_s1/CLK
12.928 0.232 tC2Q RF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_0_s1/Q
13.165 0.237 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.639 0.170 tCL RR 177 u_clkdiv/CLKOUT
13.819 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1/CLK
13.784 -0.035 tUnc Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1
13.749 -0.035 tSu 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 1.122
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 0.583
Data Arrival Time 13.165
Data Required Time 13.749
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_1_s1
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1
Launch Clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
12.346 0.000 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk
12.516 0.170 tCL RR 728 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.696 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_1_s1/CLK
12.928 0.232 tC2Q RF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_1_s1/Q
13.165 0.237 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.639 0.170 tCL RR 177 u_clkdiv/CLKOUT
13.819 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1/CLK
13.784 -0.035 tUnc Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1
13.749 -0.035 tSu 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 1.122
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 3

Path Summary:
Slack 0.583
Data Arrival Time 13.165
Data Required Time 13.749
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_2_s1
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1
Launch Clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
12.346 0.000 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk
12.516 0.170 tCL RR 728 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.696 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_2_s1/CLK
12.928 0.232 tC2Q RF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_2_s1/Q
13.165 0.237 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.639 0.170 tCL RR 177 u_clkdiv/CLKOUT
13.819 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1/CLK
13.784 -0.035 tUnc Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1
13.749 -0.035 tSu 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 1.122
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 4

Path Summary:
Slack 0.583
Data Arrival Time 13.165
Data Required Time 13.749
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_3_s1
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1
Launch Clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
12.346 0.000 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk
12.516 0.170 tCL RR 728 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.696 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_3_s1/CLK
12.928 0.232 tC2Q RF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_3_s1/Q
13.165 0.237 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.639 0.170 tCL RR 177 u_clkdiv/CLKOUT
13.819 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1/CLK
13.784 -0.035 tUnc Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1
13.749 -0.035 tSu 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 1.122
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 5

Path Summary:
Slack 0.583
Data Arrival Time 13.165
Data Required Time 13.749
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_4_s1
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1
Launch Clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
12.346 0.000 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT.default_gen_clk
12.516 0.170 tCL RR 728 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.696 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_4_s1/CLK
12.928 0.232 tC2Q RF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wptr_4_s1/Q
13.165 0.237 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.639 0.170 tCL RR 177 u_clkdiv/CLKOUT
13.819 0.180 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1/CLK
13.784 -0.035 tUnc Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1
13.749 -0.035 tSu 1 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rq1_wptr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 1.122
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%