Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_PSRAM_RefDesign\project\src\dk_video.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 10:16:27 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C C8/I7
Hold Delay Model Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed 3613
Numbers of Endpoints Analyzed 3282
Numbers of Falling Endpoints 8
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
I_clk Base 37.037 27.000 0.000 18.518 I_clk
dma_clk Base 12.346 80.998 0.000 6.173 dma_clk
memory_clk Base 6.173 161.996 0.000 3.087 memory_clk
gowin_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Generated 6.173 162.000 0.000 3.086 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTP
gowin_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Generated 12.346 81.000 0.000 6.173 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTD
gowin_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Generated 18.519 54.000 0.000 9.259 I_clk_ibuf/I I_clk gowin_rpll_inst/rpll_inst/CLKOUTD3
u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk Generated 2.694 371.250 0.000 1.347 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUT
u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.694 371.250 0.000 1.347 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTP
u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.387 185.625 0.000 2.694 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTD
u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.750 0.000 4.040 I_clk_ibuf/I I_clk u_tmds_pll/rpll_inst/CLKOUTD3
u_clkdiv/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 u_tmds_pll/rpll_inst/CLKOUT u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk u_clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 27.000(MHz) 192.188(MHz) 6 TOP
2 dma_clk 80.998(MHz) 102.285(MHz) 8 TOP
3 u_clkdiv/CLKOUT.default_gen_clk 74.250(MHz) 104.348(MHz) 10 TOP

No timing paths to get frequency of memory_clk!

No timing paths to get frequency of gowin_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of gowin_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of gowin_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
I_clk Setup 0.000 0
I_clk Hold 0.000 0
dma_clk Setup 0.000 0
dma_clk Hold 0.000 0
memory_clk Setup 0.000 0
memory_clk Hold 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
gowin_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk Setup 0.000 0
u_tmds_pll/rpll_inst/CLKOUT.default_gen_clk Hold 0.000 0
u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
u_tmds_pll/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
u_tmds_pll/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
u_tmds_pll/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
u_clkdiv/CLKOUT.default_gen_clk Setup 0.000 0
u_clkdiv/CLKOUT.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.569 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.742
2 2.569 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.742
3 2.598 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_1_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.713
4 2.735 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_0_s5/D dma_clk:[R] dma_clk:[R] 12.346 0.000 9.576
5 2.796 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.515
6 2.796 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.515
7 2.796 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 9.515
8 2.927 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s7/D dma_clk:[R] dma_clk:[R] 12.346 0.000 9.384
9 3.082 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CEA dma_clk:[R] dma_clk:[R] 12.346 0.000 9.177
10 3.298 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_data_mem_data_0_0_s/CEA dma_clk:[R] dma_clk:[R] 12.346 0.000 8.961
11 3.405 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 8.906
12 3.405 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/CE dma_clk:[R] dma_clk:[R] 12.346 0.000 8.906
13 3.446 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_0_s5/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.865
14 3.446 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s7/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.865
15 3.534 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.777
16 3.551 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_0_s5/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.760
17 3.555 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.756
18 3.584 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.727
19 3.584 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_63_s1/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.727
20 3.687 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_3_s5/D dma_clk:[R] dma_clk:[R] 12.346 0.000 8.624
21 3.885 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/DO[1] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/D u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 13.468 0.000 9.548
22 4.540 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_0_s0/D dma_clk:[R] dma_clk:[R] 12.346 0.000 7.771
23 4.567 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/DO[28] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/D u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 13.468 0.000 8.866
24 4.860 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/DO[21] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/D u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 13.468 0.000 8.573
25 5.016 Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D dma_clk:[R] dma_clk:[R] 12.346 0.000 7.295

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.215 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[4] I_clk:[R] I_clk:[R] 0.000 0.000 0.333
2 0.217 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[3] I_clk:[R] I_clk:[R] 0.000 0.000 0.335
3 0.225 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[3] I_clk:[R] I_clk:[R] 0.000 0.000 0.474
4 0.335 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[10] I_clk:[R] I_clk:[R] 0.000 0.000 0.453
5 0.335 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[0] I_clk:[R] I_clk:[R] 0.000 0.000 0.584
6 0.347 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[5] I_clk:[R] I_clk:[R] 0.000 0.000 0.596
7 0.349 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[6] I_clk:[R] I_clk:[R] 0.000 0.000 0.467
8 0.349 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[6] I_clk:[R] I_clk:[R] 0.000 0.000 0.467
9 0.349 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[13] I_clk:[R] I_clk:[R] 0.000 0.000 0.467
10 0.350 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[8] I_clk:[R] I_clk:[R] 0.000 0.000 0.468
11 0.350 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[8] I_clk:[R] I_clk:[R] 0.000 0.000 0.468
12 0.350 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[13] I_clk:[R] I_clk:[R] 0.000 0.000 0.468
13 0.350 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[10] I_clk:[R] I_clk:[R] 0.000 0.000 0.469
14 0.352 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[12] I_clk:[R] I_clk:[R] 0.000 0.000 0.470
15 0.352 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[12] I_clk:[R] I_clk:[R] 0.000 0.000 0.470
16 0.352 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D8 u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.447
17 0.359 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADA[8] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.477
18 0.360 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/Q PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADA[7] dma_clk:[R] dma_clk:[R] 0.000 0.000 0.478
19 0.363 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[1] I_clk:[R] I_clk:[R] 0.000 0.000 0.612
20 0.363 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[6] I_clk:[R] I_clk:[R] 0.000 0.000 0.612
21 0.363 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[2] I_clk:[R] I_clk:[R] 0.000 0.000 0.612
22 0.379 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D6 u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.474
23 0.379 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D2 u_clkdiv/CLKOUT.default_gen_clk:[R] u_clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.474
24 0.424 cnt_vs_2_s0/Q cnt_vs_2_s0/D I_clk:[R] I_clk:[R] 0.000 0.000 0.435
25 0.425 testpattern_inst/Sqr_v_trig_s1/Q testpattern_inst/Sqr_v_trig_s1/D I_clk:[R] I_clk:[R] 0.000 0.000 0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.174 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/RESETB dma_clk:[F] dma_clk:[R] 6.173 0.018 1.543
2 4.174 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/RESETB dma_clk:[F] dma_clk:[R] 6.173 0.018 1.543
3 4.540 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB u_clkdiv/CLKOUT.default_gen_clk:[F] u_clkdiv/CLKOUT.default_gen_clk:[R] 6.734 0.018 1.737
4 4.540 Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB u_clkdiv/CLKOUT.default_gen_clk:[F] u_clkdiv/CLKOUT.default_gen_clk:[R] 6.734 0.018 1.737
5 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
6 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
7 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
8 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
9 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
10 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
11 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
12 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
13 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
14 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
15 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
16 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
17 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
18 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
19 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
20 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
21 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
22 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
23 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
24 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634
25 8.677 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLEAR dma_clk:[R] dma_clk:[R] 12.346 0.000 3.634

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
2 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
3 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
4 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
5 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
6 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
7 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
8 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
9 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
10 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
11 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
12 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
13 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
14 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
15 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
16 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
17 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
18 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
19 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
20 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
21 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
22 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
23 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_13_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
24 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_14_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207
25 2.196 PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_15_s1/CLEAR dma_clk:[R] dma_clk:[R] 0.000 0.000 2.207

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0
2 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0
3 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d3_s0
4 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_11_s1
5 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_6_s0
6 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_8_s0
7 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_4_s0
8 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_2_s0
9 5.096 6.096 1.000 Low Pulse Width dma_clk Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_1_s0
10 5.096 6.096 1.000 Low Pulse Width dma_clk PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/timer_cnt_5_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.569
Data Arrival Time 9.985
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.165 0.550 tNET FF 1 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/I0
9.627 0.462 tINS FR 3 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/F
9.985 0.357 tNET RR 1 R39C44[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C44[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/CLK
12.554 -0.035 tSu 1 R39C44[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 36.441%; route: 5.960, 61.177%; tC2Q: 0.232, 2.382%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 2.569
Data Arrival Time 9.985
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.165 0.550 tNET FF 1 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/I0
9.627 0.462 tINS FR 3 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/F
9.985 0.357 tNET RR 1 R39C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/CLK
12.554 -0.035 tSu 1 R39C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 36.441%; route: 5.960, 61.177%; tC2Q: 0.232, 2.382%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 2.598
Data Arrival Time 9.957
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_1_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.165 0.550 tNET FF 1 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/I0
9.627 0.462 tINS FR 3 R39C45[3][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s8/F
9.957 0.329 tNET RR 1 R39C43[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C43[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_1_s1/CLK
12.554 -0.035 tSu 1 R39C43[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 36.548%; route: 5.931, 61.064%; tC2Q: 0.232, 2.388%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 2.735
Data Arrival Time 9.819
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_0_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.249 0.634 tNET FF 1 R40C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n143_s5/I0
9.819 0.570 tINS FR 1 R40C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n143_s5/F
9.819 0.000 tNET RR 1 R40C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_0_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R40C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_0_s5/CLK
12.554 -0.035 tSu 1 R40C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_0_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.658, 38.201%; route: 5.686, 59.377%; tC2Q: 0.232, 2.423%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 2.796
Data Arrival Time 9.759
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.039 0.423 tNET FF 1 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
9.609 0.570 tINS FR 3 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
9.759 0.150 tNET RR 1 R39C50[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C50[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CLK
12.554 -0.035 tSu 1 R39C50[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.658, 38.443%; route: 5.625, 59.119%; tC2Q: 0.232, 2.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 2.796
Data Arrival Time 9.759
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.039 0.423 tNET FF 1 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
9.609 0.570 tINS FR 3 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
9.759 0.150 tNET RR 1 R39C50[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C50[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CLK
12.554 -0.035 tSu 1 R39C50[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.658, 38.443%; route: 5.625, 59.119%; tC2Q: 0.232, 2.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 2.796
Data Arrival Time 9.759
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.039 0.423 tNET FF 1 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/I2
9.609 0.570 tINS FR 3 R39C50[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s8/F
9.759 0.150 tNET RR 1 R39C50[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C50[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CLK
12.554 -0.035 tSu 1 R39C50[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.658, 38.443%; route: 5.625, 59.119%; tC2Q: 0.232, 2.438%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 2.927
Data Arrival Time 9.627
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s7
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.165 0.550 tNET FF 1 R39C45[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n139_s4/I0
9.627 0.462 tINS FR 1 R39C45[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n139_s4/F
9.627 0.000 tNET RR 1 R39C45[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s7/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C45[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s7/CLK
12.554 -0.035 tSu 1 R39C45[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_4_s7

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 37.830%; route: 5.602, 59.698%; tC2Q: 0.232, 2.472%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 3.082
Data Arrival Time 9.420
Data Required Time 12.502
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.624 0.462 tINS FR 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.420 0.796 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CLKA
12.502 -0.087 tSu 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.097, 33.748%; route: 5.848, 63.723%; tC2Q: 0.232, 2.528%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 3.298
Data Arrival Time 9.204
Data Required Time 12.502
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_data_mem_data_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.624 0.462 tINS FR 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
9.204 0.580 tNET RR 1 BSRAM_R46[15] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_data_mem_data_0_0_s/CEA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 BSRAM_R46[15] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_data_mem_data_0_0_s/CLKA
12.502 -0.087 tSu 1 BSRAM_R46[15] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.097, 34.561%; route: 5.632, 62.850%; tC2Q: 0.232, 2.589%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 3.405
Data Arrival Time 9.150
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.451 0.553 tNET FF 1 R40C45[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s6/I0
9.000 0.549 tINS FR 2 R40C45[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s6/F
9.150 0.150 tNET RR 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/CLK
12.554 -0.035 tSu 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.184, 35.750%; route: 5.490, 61.645%; tC2Q: 0.232, 2.605%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 3.405
Data Arrival Time 9.150
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.451 0.553 tNET FF 1 R40C45[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s6/I0
9.000 0.549 tINS FR 2 R40C45[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s6/F
9.150 0.150 tNET RR 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/CLK
12.554 -0.035 tSu 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.184, 35.750%; route: 5.490, 61.645%; tC2Q: 0.232, 2.605%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 3.446
Data Arrival Time 9.108
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_0_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
8.646 0.031 tNET FF 1 R39C51[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n143_s5/I2
9.108 0.462 tINS FR 1 R39C51[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n143_s5/F
9.108 0.000 tNET RR 1 R39C51[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_0_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C51[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_0_s5/CLK
12.554 -0.035 tSu 1 R39C51[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_0_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 40.046%; route: 5.083, 57.337%; tC2Q: 0.232, 2.617%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 3.446
Data Arrival Time 9.108
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s7
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.162 0.265 tNET FF 1 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
8.615 0.453 tINS FF 8 R39C51[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
8.646 0.031 tNET FF 1 R39C51[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n139_s4/I2
9.108 0.462 tINS FR 1 R39C51[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n139_s4/F
9.108 0.000 tNET RR 1 R39C51[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s7/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C51[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s7/CLK
12.554 -0.035 tSu 1 R39C51[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s7

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.550, 40.046%; route: 5.083, 57.337%; tC2Q: 0.232, 2.617%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 3.534
Data Arrival Time 9.021
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.451 0.553 tNET FF 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n170_s2/I3
9.021 0.570 tINS FR 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n170_s2/F
9.021 0.000 tNET RR 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1/CLK
12.554 -0.035 tSu 1 R40C45[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.205, 36.515%; route: 5.340, 60.842%; tC2Q: 0.232, 2.643%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 3.551
Data Arrival Time 9.003
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_0_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.433 0.536 tNET FF 1 R39C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n172_s4/I0
9.003 0.570 tINS FR 1 R39C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n172_s4/F
9.003 0.000 tNET RR 1 R39C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_0_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_0_s5/CLK
12.554 -0.035 tSu 1 R39C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_0_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.205, 36.587%; route: 5.323, 60.765%; tC2Q: 0.232, 2.648%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 3.555
Data Arrival Time 9.000
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.451 0.553 tNET FF 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n168_s2/I3
9.000 0.549 tINS FR 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n168_s2/F
9.000 0.000 tNET RR 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1/CLK
12.554 -0.035 tSu 1 R40C45[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.184, 36.363%; route: 5.340, 60.987%; tC2Q: 0.232, 2.650%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 3.584
Data Arrival Time 8.970
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.599 0.702 tNET FF 1 R42C45[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n171_s4/I0
8.970 0.371 tINS FF 1 R42C45[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n171_s4/F
8.970 0.000 tNET FF 1 R42C45[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R42C45[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5/CLK
12.554 -0.035 tSu 1 R42C45[0][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_1_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.006, 34.445%; route: 5.489, 62.897%; tC2Q: 0.232, 2.658%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 3.584
Data Arrival Time 8.970
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_63_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.970 1.073 tNET FF 1 R44C47[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_63_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R44C47[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_63_s1/CLK
12.554 -0.035 tSu 1 R44C47[1][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_63_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 2.635, 30.194%; route: 5.860, 67.148%; tC2Q: 0.232, 2.658%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 3.687
Data Arrival Time 8.867
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_3_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
7.898 0.453 tINS FF 8 R39C49[3][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
8.405 0.507 tNET FF 1 R39C45[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n169_s5/I2
8.867 0.462 tINS FR 1 R39C45[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/n169_s5/F
8.867 0.000 tNET RR 1 R39C45[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_3_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C45[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_3_s5/CLK
12.554 -0.035 tSu 1 R39C45[1][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/rd_ptr_3_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.097, 35.912%; route: 5.295, 61.398%; tC2Q: 0.232, 2.690%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 3.885
Data Arrival Time 10.121
Data Required Time 14.006
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.573 0.243 tNET RR 32 BSRAM_R46[4] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
2.833 2.260 tC2Q RF 1 BSRAM_R46[4] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/DO[1]
3.489 0.656 tNET FF 1 R48C20[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s0/I1
3.951 0.462 tINS FR 1 R48C20[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s0/F
3.952 0.001 tNET RR 1 R48C20[3][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s/I3
4.507 0.555 tINS RF 1 R48C20[3][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s/F
5.191 0.684 tNET FF 1 R48C9[3][B] rgb_data_4_s2/I0
5.708 0.517 tINS FF 4 R48C9[3][B] rgb_data_4_s2/F
6.373 0.665 tNET FF 1 R45C8[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9/I3
6.943 0.570 tINS FR 2 R45C8[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9/F
6.945 0.003 tNET RR 1 R45C8[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6/I1
7.407 0.462 tINS RR 2 R45C8[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6/F
7.410 0.003 tNET RR 1 R45C8[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10/I0
7.980 0.570 tINS RR 1 R45C8[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10/F
7.981 0.001 tNET RR 1 R45C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1/I1
8.536 0.555 tINS RF 2 R45C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1/F
9.197 0.660 tNET FF 1 R50C8[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3/I3
9.568 0.371 tINS FF 1 R50C8[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3/F
9.572 0.004 tNET FF 1 R50C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0/I3
10.121 0.549 tINS FR 1 R50C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0/F
10.121 0.000 tNET RR 1 R50C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.797 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
14.041 0.243 tNET RR 1 R50C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
14.006 -0.035 tSu 1 R50C8[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 4.611, 48.291%; route: 2.677, 28.039%; tC2Q: 2.260, 23.669%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 4.540
Data Arrival Time 8.015
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_0_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/CLK
0.475 0.232 tC2Q RF 2 R48C26[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_end_o_s1/Q
1.435 0.960 tNET FF 1 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/I2
1.990 0.555 tINS FF 79 R43C32[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wbinnext_2_s4/F
3.302 1.312 tNET FF 1 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0
3.857 0.555 tINS FF 17 R43C28[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F
4.600 0.743 tNET FF 1 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/I2
5.117 0.517 tINS FF 2 R44C32[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/O_cmd_en_d_s/F
6.242 1.125 tNET FF 1 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
6.797 0.555 tINS FF 2 R41C47[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
7.445 0.648 tNET FF 1 R39C49[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s1/I2
8.015 0.570 tINS FR 1 R39C49[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_en_s1/F
8.015 0.000 tNET RR 1 R39C49[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R39C49[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_0_s0/CLK
12.554 -0.035 tSu 1 R39C49[0][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_w_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 2.752, 35.412%; route: 4.787, 61.603%; tC2Q: 0.232, 2.985%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 4.567
Data Arrival Time 9.439
Data Required Time 14.006
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.573 0.243 tNET RR 32 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
2.833 2.260 tC2Q RF 1 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/DO[28]
3.487 0.655 tNET FF 1 R45C18[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s0/I0
3.949 0.462 tINS FR 1 R45C18[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s0/F
3.951 0.001 tNET RR 1 R45C18[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s/I3
4.506 0.555 tINS RF 1 R45C18[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s/F
4.903 0.397 tNET FF 1 R45C16[1][A] rgb_data_20_s1/I1
5.420 0.517 tINS FF 4 R45C16[1][A] rgb_data_20_s1/F
5.677 0.257 tNET FF 1 R47C16[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9/I3
6.130 0.453 tINS FF 2 R47C16[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9/F
6.292 0.162 tNET FF 1 R47C16[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6/I1
6.663 0.371 tINS FF 2 R47C16[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6/F
6.822 0.159 tNET FF 1 R47C16[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10/I0
7.275 0.453 tINS FF 1 R47C16[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10/F
7.429 0.154 tNET FF 1 R47C16[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1/I1
7.978 0.549 tINS FR 2 R47C16[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1/F
8.154 0.176 tNET RR 1 R47C15[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3/I3
8.671 0.517 tINS RF 1 R47C15[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3/F
9.068 0.397 tNET FF 1 R49C15[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0/I3
9.439 0.371 tINS FF 1 R49C15[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0/F
9.439 0.000 tNET FF 1 R49C15[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.797 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
14.041 0.243 tNET RR 1 R49C15[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK
14.006 -0.035 tSu 1 R49C15[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 4.248, 47.914%; route: 2.358, 26.595%; tC2Q: 2.260, 25.491%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 4.860
Data Arrival Time 9.146
Data Required Time 14.006
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.573 0.243 tNET RR 32 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
2.833 2.260 tC2Q RF 1 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/DO[21]
3.487 0.655 tNET FF 1 R45C17[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s0/I0
3.940 0.453 tINS FF 1 R45C17[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s0/F
4.354 0.413 tNET FF 1 R47C17[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s/I3
4.725 0.371 tINS FF 1 R47C17[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s/F
5.381 0.656 tNET FF 1 R47C12[3][B] rgb_data_10_s1/I1
5.930 0.549 tINS FR 4 R47C12[3][B] rgb_data_10_s1/F
5.934 0.004 tNET RR 1 R47C12[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9/I2
6.483 0.549 tINS RR 2 R47C12[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9/F
6.485 0.003 tNET RR 1 R47C12[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6/I1
6.856 0.371 tINS RF 2 R47C12[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6/F
7.274 0.418 tNET FF 1 R45C11[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10/I0
7.823 0.549 tINS FR 1 R45C11[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10/F
7.824 0.001 tNET RR 1 R45C11[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1/I1
8.195 0.371 tINS RF 2 R45C11[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1/F
8.204 0.009 tNET FF 1 R45C11[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3/I3
8.774 0.570 tINS FR 1 R45C11[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3/F
8.775 0.001 tNET RR 1 R45C11[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0/I3
9.146 0.371 tINS RF 1 R45C11[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0/F
9.146 0.000 tNET FF 1 R45C11[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.797 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
14.041 0.243 tNET RR 1 R45C11[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/CLK
14.006 -0.035 tSu 1 R45C11[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 13.468
Logic Level 10
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 4.154, 48.452%; route: 2.159, 25.188%; tC2Q: 2.260, 26.360%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 5.016
Data Arrival Time 7.538
Data Required Time 12.554
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK
0.475 0.232 tC2Q RF 32 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q
1.732 1.257 tNET FF 1 R47C28[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/I2
2.249 0.517 tINS FF 8 R47C28[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/F
2.786 0.537 tNET FF 1 R43C27[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I3
3.303 0.517 tINS FF 9 R43C27[3][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F
3.746 0.442 tNET FF 1 R42C29[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s1/I3
4.301 0.555 tINS FF 6 R42C29[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_8_s1/F
4.733 0.432 tNET FF 1 R41C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/I2
5.250 0.517 tINS FF 2 R41C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/F
5.667 0.418 tNET FF 2 R40C28[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n451_s0/I0
6.216 0.549 tINS FR 1 R40C28[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n451_s0/COUT
6.216 0.000 tNET RR 2 R40C28[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n452_s0/CIN
6.251 0.035 tINS RF 1 R40C28[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n452_s0/COUT
6.968 0.717 tNET FF 1 R42C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
7.538 0.570 tINS FR 1 R42C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
7.538 0.000 tNET RR 1 R42C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R42C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
12.554 -0.035 tSu 1 R42C28[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 8
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 3.260, 44.690%; route: 3.803, 52.130%; tC2Q: 0.232, 3.180%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.215
Data Arrival Time 1.739
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C30[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/CLK
1.607 0.201 tC2Q RF 4 R47C30[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_1_s0/Q
1.739 0.132 tNET FF 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.132, 39.591%; tC2Q: 0.201, 60.409%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path2

Path Summary:

Slack 0.217
Data Arrival Time 1.741
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C30[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/CLK
1.607 0.201 tC2Q RF 5 R47C30[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_0_s0/Q
1.741 0.134 tNET FF 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.134, 40.013%; tC2Q: 0.201, 59.987%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path3

Path Summary:

Slack 0.225
Data Arrival Time 1.881
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C21[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/CLK
1.608 0.202 tC2Q RR 1 R44C21[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/Q
1.881 0.272 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[3]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path4

Path Summary:

Slack 0.335
Data Arrival Time 1.860
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/CLK
1.608 0.202 tC2Q RR 8 R47C31[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/Q
1.860 0.251 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.251, 55.441%; tC2Q: 0.202, 44.559%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path5

Path Summary:

Slack 0.335
Data Arrival Time 1.991
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R43C31[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/CLK
1.608 0.202 tC2Q RR 1 R43C31[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/Q
1.991 0.382 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path6

Path Summary:

Slack 0.347
Data Arrival Time 2.003
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R43C28[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/CLK
1.608 0.202 tC2Q RR 1 R43C28[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/Q
2.003 0.394 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path7

Path Summary:

Slack 0.349
Data Arrival Time 1.873
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R45C30[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/CLK
1.608 0.202 tC2Q RR 10 R45C30[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/Q
1.873 0.265 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.265, 56.766%; tC2Q: 0.202, 43.234%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path8

Path Summary:

Slack 0.349
Data Arrival Time 1.873
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R45C30[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/CLK
1.608 0.202 tC2Q RR 10 R45C30[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_3_s0/Q
1.873 0.265 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.265, 56.766%; tC2Q: 0.202, 43.234%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path9

Path Summary:

Slack 0.349
Data Arrival Time 1.874
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/CLK
1.608 0.202 tC2Q RR 8 R47C31[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/Q
1.874 0.265 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.265, 56.771%; tC2Q: 0.202, 43.229%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path10

Path Summary:

Slack 0.350
Data Arrival Time 1.875
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R45C30[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/CLK
1.608 0.202 tC2Q RR 8 R45C30[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/Q
1.875 0.266 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 56.873%; tC2Q: 0.202, 43.127%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path11

Path Summary:

Slack 0.350
Data Arrival Time 1.875
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R45C30[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/CLK
1.608 0.202 tC2Q RR 8 R45C30[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_5_s0/Q
1.875 0.266 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 56.873%; tC2Q: 0.202, 43.127%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path12

Path Summary:

Slack 0.350
Data Arrival Time 1.875
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/CLK
1.608 0.202 tC2Q RR 8 R47C31[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_10_s0/Q
1.875 0.266 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[13]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 56.879%; tC2Q: 0.202, 43.121%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path13

Path Summary:

Slack 0.350
Data Arrival Time 1.875
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/CLK
1.608 0.202 tC2Q RR 8 R47C31[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_7_s0/Q
1.875 0.266 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path14

Path Summary:

Slack 0.352
Data Arrival Time 1.876
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/CLK
1.608 0.202 tC2Q RR 10 R47C31[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/Q
1.876 0.268 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path15

Path Summary:

Slack 0.352
Data Arrival Time 1.876
Data Required Time 1.524
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R47C31[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/CLK
1.608 0.202 tC2Q RR 10 R47C31[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_9_s0/Q
1.876 0.268 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/ADA[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.524 0.118 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path16

Path Summary:

Slack 0.352
Data Arrival Time 0.961
Data Required Time 0.609
From DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 R51C8[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLK
0.716 0.202 tC2Q RR 1 R51C8[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/Q
0.961 0.245 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D8

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/PCLK
0.609 0.095 tHld 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 0.359
Data Arrival Time 0.661
Data Required Time 0.302
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R39C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/CLK
0.386 0.202 tC2Q RR 3 R39C44[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_3_s1/Q
0.661 0.275 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADA[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CLKA
0.302 0.118 tHld 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 0.360
Data Arrival Time 0.662
Data Required Time 0.302
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1
To PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R39C44[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/CLK
0.386 0.202 tC2Q RR 4 R39C44[2][B] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/wr_ptr_2_s1/Q
0.662 0.276 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/ADA[7]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s/CLKA
0.302 0.118 tHld 1 BSRAM_R46[13] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.276, 57.753%; tC2Q: 0.202, 42.247%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 0.363
Data Arrival Time 2.018
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R43C28[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/CLK
1.608 0.202 tC2Q RR 1 R43C28[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/Q
2.018 0.410 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path20

Path Summary:

Slack 0.363
Data Arrival Time 2.018
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C24[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/CLK
1.608 0.202 tC2Q RR 1 R44C24[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/Q
2.018 0.410 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path21

Path Summary:

Slack 0.363
Data Arrival Time 2.018
Data Required Time 1.655
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C21[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/CLK
1.608 0.202 tC2Q RR 1 R44C21[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/Q
2.018 0.410 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/DI[2]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKA
1.655 0.249 tHld 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path22

Path Summary:

Slack 0.379
Data Arrival Time 0.988
Data Required Time 0.609
From DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 R51C7[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLK
0.716 0.202 tC2Q RR 1 R51C7[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/Q
0.988 0.272 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D6

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/PCLK
0.609 0.095 tHld 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 0.379
Data Arrival Time 0.988
Data Required Time 0.609
From DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 R51C7[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLK
0.716 0.202 tC2Q RR 1 R51C7[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/Q
0.988 0.272 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/D2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_clkdiv/CLKOUT.default_gen_clk
0.329 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
0.514 0.184 tNET RR 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/PCLK
0.609 0.095 tHld 1 IOB8[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 0.424
Data Arrival Time 1.841
Data Required Time 1.417
From cnt_vs_2_s0
To cnt_vs_2_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C19[1][A] cnt_vs_2_s0/CLK
1.608 0.202 tC2Q RR 1 R44C19[1][A] cnt_vs_2_s0/Q
1.609 0.001 tNET RR 2 R44C19[1][A] n151_s/I1
1.841 0.232 tINS RF 1 R44C19[1][A] n151_s/SUM
1.841 0.000 tNET FF 1 R44C19[1][A] cnt_vs_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C19[1][A] cnt_vs_2_s0/CLK
1.417 0.011 tHld 1 R44C19[1][A] cnt_vs_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Path25

Path Summary:

Slack 0.425
Data Arrival Time 1.843
Data Required Time 1.417
From testpattern_inst/Sqr_v_trig_s1
To testpattern_inst/Sqr_v_trig_s1
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C15[1][A] testpattern_inst/Sqr_v_trig_s1/CLK
1.608 0.202 tC2Q RR 2 R44C15[1][A] testpattern_inst/Sqr_v_trig_s1/Q
1.611 0.002 tNET RR 1 R44C15[1][A] testpattern_inst/n1320_s12/I0
1.843 0.232 tINS RF 1 R44C15[1][A] testpattern_inst/n1320_s12/F
1.843 0.000 tNET FF 1 R44C15[1][A] testpattern_inst/Sqr_v_trig_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOR45[A] I_clk_ibuf/I
0.675 0.675 tINS RR 288 IOR45[A] I_clk_ibuf/O
1.406 0.731 tNET RR 1 R44C15[1][A] testpattern_inst/Sqr_v_trig_s1/CLK
1.417 0.011 tHld 1 R44C15[1][A] testpattern_inst/Sqr_v_trig_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%
Arrival Data Path Delay cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay cell: 0.675, 48.036%; route: 0.731, 51.964%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.174
Data Arrival Time 7.978
Data Required Time 12.151
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF 1 R44C29[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
6.666 0.232 tC2Q FF 61 R44C29[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
7.978 1.311 tNET FF 32 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s/CLKB
12.151 -0.438 tSu 1 BSRAM_R46[9] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.173
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.311, 84.967%; tC2Q: 0.232, 15.033%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack 4.174
Data Arrival Time 7.978
Data Required Time 12.151
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s
Launch Clk dma_clk:[F]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.173 6.173 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF 1 R44C29[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
6.666 0.232 tC2Q FF 61 R44C29[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q
7.978 1.311 tNET FF 32 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s/CLKB
12.151 -0.438 tSu 1 BSRAM_R46[8] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.mem_Big.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.173
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.311, 84.967%; tC2Q: 0.232, 15.033%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack 4.540
Data Arrival Time 9.062
Data Required Time 13.603
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 u_clkdiv/CLKOUT.default_gen_clk
7.063 0.329 tCL FF 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
7.325 0.261 tNET FF 1 R40C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.557 0.232 tC2Q FF 53 R40C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
9.062 1.505 tNET FF 32 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.797 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
14.041 0.243 tNET RR 1 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s/CLKB
13.603 -0.438 tSu 1 BSRAM_R46[5] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_1_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.505, 86.647%; tC2Q: 0.232, 13.353%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack 4.540
Data Arrival Time 9.062
Data Required Time 13.603
From Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s
Launch Clk u_clkdiv/CLKOUT.default_gen_clk:[F]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.734 6.734 active clock edge time
6.734 0.000 u_clkdiv/CLKOUT.default_gen_clk
7.063 0.329 tCL FF 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
7.325 0.261 tNET FF 1 R40C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/CLK
7.557 0.232 tC2Q FF 53 R40C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r_1_s0/Q
9.062 1.505 tNET FF 32 BSRAM_R46[4] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
13.468 13.468 active clock edge time
13.468 0.000 u_clkdiv/CLKOUT.default_gen_clk
13.797 0.329 tCL RR 178 BOTTOMSIDE[0] u_clkdiv/CLKOUT
14.041 0.243 tNET RR 1 BSRAM_R46[4] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB
13.603 -0.438 tSu 1 BSRAM_R46[4] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s

Path Statistics:

Clock Skew -0.018
Setup Relationship 6.734
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.261, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.505, 86.647%; tC2Q: 0.232, 13.353%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/CLK
12.554 -0.035 tSu 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK
12.554 -0.035 tSu 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLK
12.554 -0.035 tSu 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK
12.554 -0.035 tSu 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLK
12.554 -0.035 tSu 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLK
12.554 -0.035 tSu 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLK
12.554 -0.035 tSu 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLK
12.554 -0.035 tSu 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLK
12.554 -0.035 tSu 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLK
12.554 -0.035 tSu 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK
12.554 -0.035 tSu 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLK
12.554 -0.035 tSu 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLK
12.554 -0.035 tSu 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLK
12.554 -0.035 tSu 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLK
12.554 -0.035 tSu 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLK
12.554 -0.035 tSu 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLK
12.554 -0.035 tSu 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLK
12.554 -0.035 tSu 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLK
12.554 -0.035 tSu 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLK
12.554 -0.035 tSu 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack 8.677
Data Arrival Time 3.877
Data Required Time 12.554
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.243 0.243 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.475 0.232 tC2Q RF 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
2.402 1.927 tNET FF 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
2.957 0.555 tINS FF 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
3.877 0.920 tNET FF 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.346 12.346 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.589 0.243 tNET RR 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLK
12.554 -0.035 tSu 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 12.346
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay cell: 0.555, 15.274%; route: 2.847, 78.341%; tC2Q: 0.232, 6.385%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/CLK
0.195 0.011 tHld 1 R42C35[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK
0.195 0.011 tHld 1 R43C32[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLK
0.195 0.011 tHld 1 R43C32[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK
0.195 0.011 tHld 1 R43C32[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3/CLK
0.195 0.011 tHld 1 R51C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6/CLK
0.195 0.011 tHld 1 R51C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_5_s6

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3/CLK
0.195 0.011 tHld 1 R49C22[2][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3/CLK
0.195 0.011 tHld 1 R49C21[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3/CLK
0.195 0.011 tHld 1 R49C22[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4/CLK
0.195 0.011 tHld 1 R49C22[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_cnt_5_s4

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK
0.195 0.011 tHld 1 R48C26[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLK
0.195 0.011 tHld 1 R49C23[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLK
0.195 0.011 tHld 1 R50C23[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLK
0.195 0.011 tHld 1 R50C23[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1/CLK
0.195 0.011 tHld 1 R49C23[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLK
0.195 0.011 tHld 1 R50C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLK
0.195 0.011 tHld 1 R50C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLK
0.195 0.011 tHld 1 R50C25[1][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1/CLK
0.195 0.011 tHld 1 R50C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1/CLK
0.195 0.011 tHld 1 R50C24[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1/CLK
0.195 0.011 tHld 1 R50C26[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R50C26[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R50C26[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1/CLK
0.195 0.011 tHld 1 R50C26[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_13_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_13_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_13_s1/CLK
0.195 0.011 tHld 1 R49C25[0][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_13_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_14_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_14_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_14_s1/CLK
0.195 0.011 tHld 1 R49C25[1][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack 2.196
Data Arrival Time 2.391
Data Required Time 0.195
From PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0
To Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_15_s1
Launch Clk dma_clk:[R]
Latch Clk dma_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/CLK
0.386 0.202 tC2Q RR 308 R42C41[2][A] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/init_calib_s0/Q
1.404 1.017 tNET RR 1 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/I0
1.795 0.391 tINS RR 119 R48C30[2][A] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n14_s5/F
2.391 0.597 tNET RR 1 R49C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_15_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 dma_clk
0.000 0.000 tCL RR 731 RIGHTSIDE[0] PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
0.184 0.184 tNET RR 1 R49C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_15_s1/CLK
0.195 0.011 tHld 1 R49C25[0][B] Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_15_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay cell: 0.391, 17.716%; route: 1.614, 73.132%; tC2Q: 0.202, 9.152%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

MPW2

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

MPW3

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d3_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d3_s0/CLK

MPW4

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_11_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_11_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_11_s1/CLK

MPW5

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_6_s0/CLK

MPW6

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_8_s0/CLK

MPW7

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_4_s0/CLK

MPW8

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_2_s0/CLK

MPW9

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR Video_Frame_Buffer_Top_inst/vfb_top_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_1_s0/CLK

MPW10

MPW Summary:

Slack: 5.096
Actual Width: 6.096
Required Width: 1.000
Type: Low Pulse Width
Clock: dma_clk
Objects: PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/timer_cnt_5_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.173 0.000 active clock edge time
6.173 0.000 dma_clk
6.173 0.000 tCL FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
6.434 0.261 tNET FF PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/timer_cnt_5_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.346 0.000 active clock edge time
12.346 0.000 dma_clk
12.346 0.000 tCL RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/clkdiv/CLKOUT
12.530 0.184 tNET RR PSRAM_Memory_Interface_HS_Top_inst/u_psram_top/u_psram_init/timer_cnt_5_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
731 dma_clk 2.569 0.261
308 init_calib 2.755 2.175
288 I_clk_d 17.764 1.196
178 pix_clk 3.885 0.261
119 n14_11 8.677 1.312
79 Small.wbinnext_2_8 2.569 1.659
66 O_cmd_en_d_4 4.506 0.772
65 rd_data_valid_d1[0] 9.970 1.593
65 rd_data_valid_d1_0[1] 10.062 1.646
64 wr_dq_29_8 5.714 1.294

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R40C23 84.72%
R47C31 84.72%
R39C49 83.33%
R41C16 83.33%
R42C28 81.94%
R44C50 81.94%
R42C47 81.94%
R43C13 81.94%
R40C6 81.94%
R41C31 81.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name I_clk -period 37.037 -waveform {0 18.518} [get_ports {I_clk}] -add
TC_CLOCK Actived create_clock -name dma_clk -period 12.346 -waveform {0 6.173} [get_nets {dma_clk}] -add
TC_CLOCK Actived create_clock -name memory_clk -period 6.173 -waveform {0 3.087} [get_nets {memory_clk}] -add
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {I_clk}] -group [get_clocks {dma_clk}] -group [get_clocks {memory_clk}]