Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\DVI_TX\data\dvi_tx_top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\DVI_TX\data\rgb2dvi.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18QN88PC8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 10:16:15 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DVI_TX_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 38.422MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.422MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 38.422MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.422MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 38.422MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.422MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 38.422MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 38.422MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 38.422MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 38.422MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 38.422MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 38.422MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 70.020MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 70.020MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 70.020MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 70.020MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 38
I/O Buf 34
    IBUF 30
    TLVDS_OBUF 4
Register 73
    DFFP 3
    DFFC 70
LUT 216
    LUT2 35
    LUT3 50
    LUT4 131
ALU 69
    ALU 69
INV 4
    INV 4
IOLOGIC 4
    OSER10 4

Resource Utilization Summary

Resource Usage Utilization
Logic 289(220 LUT, 69 ALU) / 20736 2%
Register 73 / 15750 <1%
  --Register as Latch 0 / 15750 0%
  --Register as FF 73 / 15750 <1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_rgb_clk Base 10.000 100.0 0.000 5.000 I_rgb_clk_ibuf/I
I_serial_clk Base 10.000 100.0 0.000 5.000 I_serial_clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_rgb_clk 100.0(MHz) 128.9(MHz) 11 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.245
Data Arrival Time 8.583
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0
To rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/CLK
1.095 0.232 tC2Q RF 7 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1
1.887 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1
2.679 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1
3.471 0.555 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
3.708 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
4.161 0.453 tINS FF 3 rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
4.398 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
4.915 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
5.152 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1
5.722 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/COUT
5.722 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/CIN
6.192 0.470 tINS RF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/SUM
6.429 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3
6.799 0.371 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F
7.036 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0
7.554 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F
7.791 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1
8.345 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F
8.583 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.118, 66.296%; route: 2.370, 30.699%; tC2Q: 0.232, 3.005%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 2.891
Data Arrival Time 7.937
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
To rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
1.095 0.232 tC2Q RF 20 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/I1
1.887 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I1
2.679 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2
3.369 0.453 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.606 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0
4.123 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
4.360 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1
4.930 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/COUT
4.930 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/CIN
5.400 0.470 tINS RF 2 rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM
5.637 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/I0
6.154 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/F
6.391 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0
6.908 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F
7.145 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1
7.700 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F
7.937 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.709, 66.567%; route: 2.133, 30.153%; tC2Q: 0.232, 3.280%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 2.897
Data Arrival Time 7.931
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0
To rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK
1.095 0.232 tC2Q RF 5 rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/I1
1.887 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18/I1
2.679 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17/I1
3.471 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17/F
3.708 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I1
4.263 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
4.500 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1
5.070 0.570 tINS FR 1 rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT
5.070 0.000 tNET RR 2 rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN
5.540 0.470 tINS RF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM
5.777 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/I3
6.148 0.371 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/F
6.385 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0
6.902 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F
7.139 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1
7.694 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F
7.931 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.703, 66.540%; route: 2.133, 30.178%; tC2Q: 0.232, 3.282%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 3.300
Data Arrival Time 7.527
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0
To rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/CLK
1.095 0.232 tC2Q RF 7 rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1
1.887 0.555 tINS FF 5 rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1
2.679 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1
3.471 0.555 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
3.708 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
4.161 0.453 tINS FF 3 rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
4.398 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
4.915 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
5.152 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1
5.707 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM
5.944 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/I1
6.498 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/F
6.735 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I1
7.290 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F
7.527 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.300, 64.516%; route: 2.133, 32.003%; tC2Q: 0.232, 3.481%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 3.440
Data Arrival Time 7.388
Data Required Time 10.828
From rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
To rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Launch Clk I_rgb_clk[R]
Latch Clk I_rgb_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_rgb_clk
0.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
0.683 0.683 tINS RR 77 I_rgb_clk_ibuf/O
0.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
1.095 0.232 tC2Q RF 20 rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q
1.332 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/I1
1.887 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/F
2.124 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I1
2.679 0.555 tINS FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F
2.916 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2
3.369 0.453 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F
3.606 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0
4.123 0.517 tINS FF 4 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
4.360 0.237 tNET FF 2 rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1
4.915 0.555 tINS FF 3 rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/SUM
5.152 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/I0
5.669 0.517 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/F
5.906 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/I2
6.359 0.453 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/F
6.596 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/I1
7.151 0.555 tINS FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/F
7.388 0.237 tNET FF 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_rgb_clk
10.000 0.000 tCL RR 1 I_rgb_clk_ibuf/I
10.682 0.683 tINS RR 77 I_rgb_clk_ibuf/O
10.863 0.180 tNET RR 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK
10.828 -0.035 tSu 1 rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.160, 63.754%; route: 2.133, 32.690%; tC2Q: 0.232, 3.556%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%