Timing Messages

Report Title Timing Analysis Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\I2C_IP\v2.0_ref\mode1\goConfig_I2C_GoConfig_Mode1\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2024\I2C_IP\v2.0_ref\mode1\goConfig_I2C_GoConfig_Mode1\fpga_project\src\fpga_project.cst
Timing Constraint File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Tue Oct 22 16:52:00 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C7/I6
Hold Delay Model Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed 1538
Numbers of Endpoints Analyzed 738
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk Base 40.000 25.000 0.000 20.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk 25.000(MHz) 116.429(MHz) 9 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk Setup 0.000 0
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 31.411 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CEB u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 8.450
2 31.491 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 8.477
3 31.761 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 8.207
4 31.850 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 8.118
5 32.037 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.666
6 32.068 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.636
7 32.115 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.589
8 32.165 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.803
9 32.218 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.486
10 32.272 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.696
11 32.276 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.427
12 32.363 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.605
13 32.403 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.565
14 32.495 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.473
15 32.615 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_0_s2/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.088
16 32.662 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.306
17 32.763 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.940
18 32.818 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.150
19 32.818 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.150
20 32.855 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.849
21 32.855 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.849
22 32.858 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.846
23 32.883 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_1_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.085
24 32.883 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.085
25 32.933 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_7_s2/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_0_s0/CE u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.035

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
2 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
3 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
4 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
5 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
6 0.524 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
7 0.524 led_cnt_2_s0/Q led_cnt_2_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
8 0.524 led_cnt_3_s0/Q led_cnt_3_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
9 0.524 led_cnt_11_s0/Q led_cnt_11_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
10 0.524 led_cnt_17_s0/Q led_cnt_17_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
11 0.524 led_cnt_21_s0/Q led_cnt_21_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
12 0.524 led_cnt_28_s0/Q led_cnt_28_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
13 0.525 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
14 0.525 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
15 0.525 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
16 0.525 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
17 0.525 led_cnt_0_s0/Q led_cnt_0_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
18 0.525 led_cnt_7_s0/Q led_cnt_7_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
19 0.525 led_cnt_8_s0/Q led_cnt_8_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
20 0.525 led_cnt_10_s0/Q led_cnt_10_s0/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
21 0.526 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
22 0.526 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
23 0.526 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
24 0.526 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
25 0.526 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/D u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 37.807 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
2 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
3 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
4 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
5 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
6 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
7 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
8 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
9 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
10 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
11 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
12 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
13 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
14 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
15 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
16 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
17 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
18 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
19 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
20 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
21 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
22 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
23 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
24 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041
25 37.927 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 2.041

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
2 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
3 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
4 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
5 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
6 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
7 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
8 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
9 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
10 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
11 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
12 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
13 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
14 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
15 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
16 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
17 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
18 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
19 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
20 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
21 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
22 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
23 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
24 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391
25 1.382 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.391

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk led_cnt_30_s0
2 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk led_cnt_28_s0
3 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk led_cnt_24_s0
4 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk led_cnt_16_s0
5 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk led_cnt_0_s0
6 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0
7 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0
8 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0
9 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0
10 19.017 19.943 0.926 Low Pulse Width u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 31.411
Data Arrival Time 8.631
Data Required Time 40.042
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R8C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/CLK
0.520 0.340 tC2Q RF 1 R8C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/Q
1.486 0.966 tNET FF 1 R8C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/I0
2.251 0.765 tINS FF 6 R8C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/F
2.859 0.608 tNET FF 1 R9C9[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/I1
3.323 0.464 tINS FF 1 R9C9[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/F
3.931 0.608 tNET FF 2 R11C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1
4.339 0.408 tINS FR 1 R11C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.339 0.000 tNET RR 2 R11C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.381 0.042 tINS RF 1 R11C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.381 0.000 tNET FF 2 R11C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.423 0.042 tINS FF 1 R11C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.423 0.000 tNET FF 2 R11C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.466 0.042 tINS FF 1 R11C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.466 0.000 tNET FF 2 R11C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.508 0.042 tINS FF 1 R11C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.508 0.000 tNET FF 2 R11C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.550 0.042 tINS FF 1 R11C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.550 0.000 tNET FF 2 R11C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.592 0.042 tINS FF 1 R11C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.592 0.000 tNET FF 2 R11C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/CIN
4.635 0.042 tINS FF 1 R11C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/COUT
4.635 0.000 tNET FF 2 R11C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/CIN
4.677 0.042 tINS FF 1 R11C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/COUT
4.677 0.000 tNET FF 2 R11C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/CIN
4.719 0.042 tINS FF 1 R11C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/COUT
4.719 0.000 tNET FF 2 R11C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/CIN
5.136 0.417 tINS FF 3 R11C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/SUM
5.753 0.616 tNET FF 2 R9C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/I0
6.463 0.710 tINS FF 1 R9C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/COUT
6.463 0.000 tNET FF 2 R9C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/CIN
6.503 0.040 tINS FR 2 R9C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/COUT
7.207 0.705 tNET RR 1 R9C10[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n13_s0/I2
7.801 0.594 tINS RR 1 R9C10[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n13_s0/F
8.631 0.829 tNET RR 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.042 -0.139 tSu 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.778, 44.704%; route: 4.333, 51.277%; tC2Q: 0.340, 4.019%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path2

Path Summary:

Slack 31.491
Data Arrival Time 8.657
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.622 0.971 tNET FF 1 R5C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s5/I3
8.408 0.786 tINS FR 1 R5C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s5/F
8.657 0.249 tNET RR 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CLK
40.148 -0.032 tSu 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.383, 51.706%; route: 3.754, 44.288%; tC2Q: 0.340, 4.006%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path3

Path Summary:

Slack 31.761
Data Arrival Time 8.387
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.271 0.621 tNET FF 1 R6C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s5/I3
7.866 0.594 tINS FR 1 R6C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s5/F
8.387 0.522 tNET RR 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/CLK
40.148 -0.032 tSu 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.191, 51.070%; route: 3.676, 44.792%; tC2Q: 0.340, 4.138%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path4

Path Summary:

Slack 31.850
Data Arrival Time 8.298
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.263 0.612 tNET FF 1 R6C12[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s5/I3
8.049 0.786 tINS FR 1 R6C12[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s5/F
8.298 0.249 tNET RR 1 R6C12[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C12[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CLK
40.148 -0.032 tSu 1 R6C12[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.383, 53.993%; route: 3.395, 41.824%; tC2Q: 0.340, 4.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path5

Path Summary:

Slack 32.037
Data Arrival Time 7.847
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/CLK
0.520 0.340 tC2Q RF 2 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q
1.962 1.442 tNET FF 2 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/I1
2.737 0.774 tINS FF 1 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/COUT
2.737 0.000 tNET FF 2 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/CIN
2.779 0.042 tINS FF 1 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/COUT
2.779 0.000 tNET FF 2 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/CIN
2.821 0.042 tINS FF 1 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/COUT
2.821 0.000 tNET FF 2 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/CIN
2.863 0.042 tINS FF 1 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/COUT
2.863 0.000 tNET FF 2 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/CIN
2.906 0.042 tINS FF 1 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/COUT
2.906 0.000 tNET FF 2 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/CIN
2.948 0.042 tINS FF 1 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/COUT
2.948 0.000 tNET FF 2 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/CIN
2.990 0.042 tINS FF 1 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/COUT
2.990 0.000 tNET FF 2 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/CIN
3.032 0.042 tINS FF 1 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/COUT
3.032 0.000 tNET FF 2 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/CIN
3.075 0.042 tINS FF 1 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/COUT
3.075 0.000 tNET FF 2 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/CIN
3.117 0.042 tINS FF 1 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/COUT
3.117 0.000 tNET FF 2 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/CIN
3.159 0.042 tINS FF 1 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/COUT
3.159 0.000 tNET FF 2 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/CIN
3.201 0.042 tINS FF 1 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/COUT
3.201 0.000 tNET FF 2 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/CIN
3.244 0.042 tINS FF 1 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/COUT
3.244 0.000 tNET FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/CIN
3.286 0.042 tINS FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/COUT
4.796 1.510 tNET FF 1 R14C11[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/I0
5.610 0.814 tINS FF 2 R14C11[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/F
5.618 0.008 tNET FF 1 R14C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/I2
6.432 0.814 tINS FF 2 R14C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/F
7.033 0.600 tNET FF 1 R14C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s17/I1
7.847 0.814 tINS FF 1 R14C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s17/F
7.847 0.000 tNET FF 1 R14C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R14C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/CLK
39.884 -0.296 tSu 1 R14C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.767, 49.130%; route: 3.560, 46.440%; tC2Q: 0.340, 4.430%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path6

Path Summary:

Slack 32.068
Data Arrival Time 7.816
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R8C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/CLK
0.520 0.340 tC2Q RF 1 R8C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_rden_s1/Q
1.486 0.966 tNET FF 1 R8C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/I0
2.251 0.765 tINS FF 6 R8C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/F
2.859 0.608 tNET FF 1 R9C9[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/I1
3.323 0.464 tINS FF 1 R9C9[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/F
3.931 0.608 tNET FF 2 R11C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1
4.339 0.408 tINS FR 1 R11C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.339 0.000 tNET RR 2 R11C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.381 0.042 tINS RF 1 R11C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.381 0.000 tNET FF 2 R11C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.423 0.042 tINS FF 1 R11C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.423 0.000 tNET FF 2 R11C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.466 0.042 tINS FF 1 R11C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.466 0.000 tNET FF 2 R11C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.508 0.042 tINS FF 1 R11C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.508 0.000 tNET FF 2 R11C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.550 0.042 tINS FF 1 R11C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.550 0.000 tNET FF 2 R11C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.592 0.042 tINS FF 1 R11C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.592 0.000 tNET FF 2 R11C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/CIN
4.635 0.042 tINS FF 1 R11C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/COUT
4.635 0.000 tNET FF 2 R11C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/CIN
4.677 0.042 tINS FF 1 R11C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/COUT
4.677 0.000 tNET FF 2 R11C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/CIN
4.719 0.042 tINS FF 1 R11C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/COUT
4.719 0.000 tNET FF 2 R11C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/CIN
5.136 0.417 tINS FF 3 R11C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/SUM
5.753 0.616 tNET FF 2 R9C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/I0
6.463 0.710 tINS FF 1 R9C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/COUT
6.463 0.000 tNET FF 2 R9C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/CIN
6.503 0.040 tINS FR 2 R9C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/COUT
7.207 0.705 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rempty_val_s1/I0
7.816 0.609 tINS RF 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rempty_val_s1/F
7.816 0.000 tNET FF 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
39.884 -0.296 tSu 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.792, 49.667%; route: 3.504, 45.885%; tC2Q: 0.340, 4.448%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path7

Path Summary:

Slack 32.115
Data Arrival Time 7.769
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
6.137 1.232 tNET FF 1 R5C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s4/I2
6.951 0.814 tINS FF 1 R5C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s4/F
6.955 0.004 tNET FF 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s3/I0
7.769 0.814 tINS FF 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s3/F
7.769 0.000 tNET FF 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CLK
39.884 -0.296 tSu 1 R5C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.817, 50.296%; route: 3.432, 45.229%; tC2Q: 0.340, 4.475%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path8

Path Summary:

Slack 32.165
Data Arrival Time 7.984
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.271 0.621 tNET FF 1 R6C13[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s5/I3
7.734 0.463 tINS FR 1 R6C13[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s5/F
7.984 0.249 tNET RR 1 R6C13[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C13[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s0/CLK
40.148 -0.032 tSu 1 R6C13[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.060, 52.030%; route: 3.404, 43.618%; tC2Q: 0.340, 4.352%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path9

Path Summary:

Slack 32.218
Data Arrival Time 7.666
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
6.128 1.223 tNET FF 1 R5C12[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1593_s4/I2
6.591 0.463 tINS FR 1 R5C12[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1593_s4/F
6.901 0.310 tNET RR 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1593_s3/I0
7.666 0.765 tINS RF 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1593_s3/F
7.666 0.000 tNET FF 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CLK
39.884 -0.296 tSu 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.416, 45.635%; route: 3.730, 49.828%; tC2Q: 0.340, 4.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path10

Path Summary:

Slack 32.272
Data Arrival Time 7.877
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.033 0.383 tNET FF 1 R6C12[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s5/I3
7.628 0.594 tINS FR 1 R6C12[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s5/F
7.877 0.249 tNET RR 1 R6C12[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C12[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CLK
40.148 -0.032 tSu 1 R6C12[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.191, 54.456%; route: 3.166, 41.132%; tC2Q: 0.340, 4.413%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path11

Path Summary:

Slack 32.276
Data Arrival Time 7.608
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.019 0.860 tNET FF 1 R9C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s50/I2
4.613 0.594 tINS FR 1 R9C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s50/F
4.923 0.310 tNET RR 1 R9C5[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s44/I2
5.709 0.786 tINS RR 1 R9C5[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s44/F
6.020 0.310 tNET RR 1 R8C5[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s38/I3
6.483 0.463 tINS RR 1 R8C5[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s38/F
6.793 0.310 tNET RR 1 R9C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s34/I3
7.608 0.814 tINS RF 1 R9C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s34/F
7.608 0.000 tNET FF 1 R9C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/CLK
39.884 -0.296 tSu 1 R9C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.081, 54.952%; route: 3.006, 40.475%; tC2Q: 0.340, 4.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path12

Path Summary:

Slack 32.363
Data Arrival Time 7.785
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.622 0.786 tINS RR 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
6.942 0.319 tNET RR 1 R8C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s5/I3
7.536 0.594 tINS RR 1 R8C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s5/F
7.785 0.249 tNET RR 1 R8C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R8C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s0/CLK
40.148 -0.032 tSu 1 R8C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.163, 54.743%; route: 3.102, 40.791%; tC2Q: 0.340, 4.466%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path13

Path Summary:

Slack 32.403
Data Arrival Time 7.746
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.651 0.814 tINS RF 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
7.033 0.383 tNET FF 1 R6C12[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s5/I3
7.496 0.463 tINS FR 1 R6C12[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s5/F
7.746 0.249 tNET RR 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CLK
40.148 -0.032 tSu 1 R6C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.060, 53.666%; route: 3.166, 41.845%; tC2Q: 0.340, 4.489%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path14

Path Summary:

Slack 32.495
Data Arrival Time 7.654
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
4.929 0.024 tNET FF 1 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3
5.523 0.594 tINS FR 3 R8C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F
5.836 0.313 tNET RR 1 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0
6.622 0.786 tINS RR 8 R8C12[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F
6.942 0.319 tNET RR 1 R8C13[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s5/I3
7.405 0.463 tINS RR 1 R8C13[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s5/F
7.654 0.249 tNET RR 1 R8C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R8C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CLK
40.148 -0.032 tSu 1 R8C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 4.032, 53.949%; route: 3.102, 41.507%; tC2Q: 0.340, 4.544%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path15

Path Summary:

Slack 32.615
Data Arrival Time 7.269
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_0_s2
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/CLK
0.520 0.340 tC2Q RF 2 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q
1.962 1.442 tNET FF 2 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/I1
2.737 0.774 tINS FF 1 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/COUT
2.737 0.000 tNET FF 2 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/CIN
2.779 0.042 tINS FF 1 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/COUT
2.779 0.000 tNET FF 2 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/CIN
2.821 0.042 tINS FF 1 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/COUT
2.821 0.000 tNET FF 2 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/CIN
2.863 0.042 tINS FF 1 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/COUT
2.863 0.000 tNET FF 2 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/CIN
2.906 0.042 tINS FF 1 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/COUT
2.906 0.000 tNET FF 2 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/CIN
2.948 0.042 tINS FF 1 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/COUT
2.948 0.000 tNET FF 2 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/CIN
2.990 0.042 tINS FF 1 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/COUT
2.990 0.000 tNET FF 2 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/CIN
3.032 0.042 tINS FF 1 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/COUT
3.032 0.000 tNET FF 2 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/CIN
3.075 0.042 tINS FF 1 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/COUT
3.075 0.000 tNET FF 2 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/CIN
3.117 0.042 tINS FF 1 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/COUT
3.117 0.000 tNET FF 2 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/CIN
3.159 0.042 tINS FF 1 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/COUT
3.159 0.000 tNET FF 2 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/CIN
3.201 0.042 tINS FF 1 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/COUT
3.201 0.000 tNET FF 2 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/CIN
3.244 0.042 tINS FF 1 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/COUT
3.244 0.000 tNET FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/CIN
3.286 0.042 tINS FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/COUT
4.551 1.265 tNET FF 1 R14C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s26/I0
5.315 0.765 tINS FF 1 R14C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s26/F
5.319 0.004 tNET FF 1 R14C11[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s18/I3
6.134 0.814 tINS FF 3 R14C11[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s18/F
6.504 0.371 tNET FF 1 R14C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s12/I0
7.269 0.765 tINS FF 1 R14C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s12/F
7.269 0.000 tNET FF 1 R14C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_0_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R14C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_0_s2/CLK
39.884 -0.296 tSu 1 R14C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_0_s2

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.667, 51.735%; route: 3.082, 43.474%; tC2Q: 0.340, 4.791%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path16

Path Summary:

Slack 32.662
Data Arrival Time 7.487
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/CLK
0.520 0.340 tC2Q RF 2 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q
1.962 1.442 tNET FF 2 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/I1
2.737 0.774 tINS FF 1 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/COUT
2.737 0.000 tNET FF 2 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/CIN
2.779 0.042 tINS FF 1 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/COUT
2.779 0.000 tNET FF 2 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/CIN
2.821 0.042 tINS FF 1 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/COUT
2.821 0.000 tNET FF 2 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/CIN
2.863 0.042 tINS FF 1 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/COUT
2.863 0.000 tNET FF 2 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/CIN
2.906 0.042 tINS FF 1 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/COUT
2.906 0.000 tNET FF 2 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/CIN
2.948 0.042 tINS FF 1 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/COUT
2.948 0.000 tNET FF 2 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/CIN
2.990 0.042 tINS FF 1 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/COUT
2.990 0.000 tNET FF 2 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/CIN
3.032 0.042 tINS FF 1 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/COUT
3.032 0.000 tNET FF 2 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/CIN
3.075 0.042 tINS FF 1 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/COUT
3.075 0.000 tNET FF 2 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/CIN
3.117 0.042 tINS FF 1 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/COUT
3.117 0.000 tNET FF 2 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/CIN
3.159 0.042 tINS FF 1 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/COUT
3.159 0.000 tNET FF 2 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/CIN
3.201 0.042 tINS FF 1 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/COUT
3.201 0.000 tNET FF 2 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/CIN
3.244 0.042 tINS FF 1 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/COUT
3.244 0.000 tNET FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/CIN
3.286 0.042 tINS FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/COUT
4.796 1.510 tNET FF 1 R14C11[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/I0
5.610 0.814 tINS FF 2 R14C11[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/F
5.618 0.008 tNET FF 1 R14C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/I2
6.432 0.814 tINS FF 2 R14C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/F
6.441 0.008 tNET FF 1 R14C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s4/I1
6.904 0.463 tINS FR 1 R14C11[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s4/F
7.487 0.583 tNET RR 1 R14C12[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R14C12[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s0/CLK
40.148 -0.032 tSu 1 R14C12[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/CLK_RXRDY_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.415, 46.746%; route: 3.551, 48.606%; tC2Q: 0.340, 4.649%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path17

Path Summary:

Slack 32.763
Data Arrival Time 7.121
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.520 0.340 tC2Q RF 2 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/Q
0.776 0.255 tNET FF 1 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/I2
1.590 0.814 tINS FF 2 R4C9[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s3/F
2.549 0.959 tNET FF 1 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I2
3.158 0.609 tINS FF 28 R7C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F
4.140 0.981 tNET FF 1 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0
4.904 0.765 tINS FF 9 R8C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F
5.888 0.984 tNET FF 1 R7C11[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1596_s4/I2
6.352 0.464 tINS FF 1 R7C11[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1596_s4/F
6.356 0.004 tNET FF 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1596_s3/I0
7.121 0.765 tINS FF 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1596_s3/F
7.121 0.000 tNET FF 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0/CLK
39.884 -0.296 tSu 1 R7C11[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.417, 49.231%; route: 3.184, 45.876%; tC2Q: 0.340, 4.894%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path18

Path Summary:

Slack 32.818
Data Arrival Time 7.330
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
0.520 0.340 tC2Q RF 10 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q
1.738 1.218 tNET FF 1 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/I1
2.498 0.760 tINS FR 3 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/F
2.813 0.315 tNET RR 1 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/I1
3.578 0.765 tINS RF 2 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/F
4.549 0.971 tNET FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/I3
5.363 0.814 tINS FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/F
5.971 0.608 tNET FF 1 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/I0
6.435 0.463 tINS FR 4 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/F
7.330 0.895 tNET RR 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/CLK
40.148 -0.032 tSu 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.802, 39.198%; route: 4.007, 56.052%; tC2Q: 0.340, 4.750%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path19

Path Summary:

Slack 32.818
Data Arrival Time 7.330
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
0.520 0.340 tC2Q RF 10 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q
1.738 1.218 tNET FF 1 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/I1
2.498 0.760 tINS FR 3 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/F
2.813 0.315 tNET RR 1 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/I1
3.578 0.765 tINS RF 2 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/F
4.549 0.971 tNET FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/I3
5.363 0.814 tINS FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/F
5.971 0.608 tNET FF 1 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/I0
6.435 0.463 tINS FR 4 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/F
7.330 0.895 tNET RR 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/CLK
40.148 -0.032 tSu 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.802, 39.198%; route: 4.007, 56.052%; tC2Q: 0.340, 4.750%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path20

Path Summary:

Slack 32.855
Data Arrival Time 7.029
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/CLK
0.520 0.340 tC2Q RF 22 R12C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/Q
1.148 0.628 tNET FF 1 R14C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n792_s1/I1
1.962 0.814 tINS FF 11 R14C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n792_s1/F
3.059 1.097 tNET FF 1 R9C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/int_reg_s5/I3
3.824 0.765 tINS FF 2 R9C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/int_reg_s5/F
5.142 1.318 tNET FF 1 R12C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n838_s59/I1
5.606 0.464 tINS FF 4 R12C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n838_s59/F
6.215 0.608 tNET FF 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n844_s42/I1
7.029 0.814 tINS FF 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n844_s42/F
7.029 0.000 tNET FF 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0/CLK
39.884 -0.296 tSu 1 R9C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.857, 41.721%; route: 3.652, 53.320%; tC2Q: 0.340, 4.959%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path21

Path Summary:

Slack 32.855
Data Arrival Time 7.029
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/CLK
0.520 0.340 tC2Q RF 22 R12C5[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate_0_s0/Q
1.148 0.628 tNET FF 1 R14C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n792_s1/I1
1.962 0.814 tINS FF 11 R14C6[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n792_s1/F
3.059 1.097 tNET FF 1 R9C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/int_reg_s5/I3
3.824 0.765 tINS FF 2 R9C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/int_reg_s5/F
5.142 1.318 tNET FF 1 R12C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n838_s59/I1
5.606 0.464 tINS FF 4 R12C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n838_s59/F
6.215 0.608 tNET FF 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n840_s43/I0
7.029 0.814 tINS FF 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n840_s43/F
7.029 0.000 tNET FF 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0/CLK
39.884 -0.296 tSu 1 R9C4[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.857, 41.721%; route: 3.652, 53.320%; tC2Q: 0.340, 4.959%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path22

Path Summary:

Slack 32.858
Data Arrival Time 7.026
Data Required Time 39.884
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/CLK
0.520 0.340 tC2Q RF 2 R16C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_2_s0/Q
1.962 1.442 tNET FF 2 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/I1
2.737 0.774 tINS FF 1 R12C13[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n464_s0/COUT
2.737 0.000 tNET FF 2 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/CIN
2.779 0.042 tINS FF 1 R12C13[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n465_s0/COUT
2.779 0.000 tNET FF 2 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/CIN
2.821 0.042 tINS FF 1 R12C13[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n466_s0/COUT
2.821 0.000 tNET FF 2 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/CIN
2.863 0.042 tINS FF 1 R12C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n467_s0/COUT
2.863 0.000 tNET FF 2 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/CIN
2.906 0.042 tINS FF 1 R12C14[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n468_s0/COUT
2.906 0.000 tNET FF 2 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/CIN
2.948 0.042 tINS FF 1 R12C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n469_s0/COUT
2.948 0.000 tNET FF 2 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/CIN
2.990 0.042 tINS FF 1 R12C14[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n470_s0/COUT
2.990 0.000 tNET FF 2 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/CIN
3.032 0.042 tINS FF 1 R12C14[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n471_s0/COUT
3.032 0.000 tNET FF 2 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/CIN
3.075 0.042 tINS FF 1 R12C14[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n472_s0/COUT
3.075 0.000 tNET FF 2 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/CIN
3.117 0.042 tINS FF 1 R12C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n473_s0/COUT
3.117 0.000 tNET FF 2 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/CIN
3.159 0.042 tINS FF 1 R12C15[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n474_s0/COUT
3.159 0.000 tNET FF 2 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/CIN
3.201 0.042 tINS FF 1 R12C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n475_s0/COUT
3.201 0.000 tNET FF 2 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/CIN
3.244 0.042 tINS FF 1 R12C15[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/COUT
3.244 0.000 tNET FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/CIN
3.286 0.042 tINS FF 2 R12C15[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/COUT
4.551 1.265 tNET FF 1 R14C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s26/I0
5.315 0.765 tINS FF 1 R14C11[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s26/F
5.319 0.004 tNET FF 1 R14C11[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s18/I3
6.105 0.786 tINS FR 3 R14C11[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s18/F
6.417 0.312 tNET RR 1 R14C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n614_s47/I3
7.026 0.609 tINS RF 1 R14C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n614_s47/F
7.026 0.000 tNET FF 1 R14C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R14C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/CLK
39.884 -0.296 tSu 1 R14C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.483, 50.883%; route: 3.023, 44.156%; tC2Q: 0.340, 4.961%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path23

Path Summary:

Slack 32.883
Data Arrival Time 7.265
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_1_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
0.520 0.340 tC2Q RF 10 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q
1.738 1.218 tNET FF 1 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/I1
2.498 0.760 tINS FR 3 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/F
2.813 0.315 tNET RR 1 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/I1
3.578 0.765 tINS RF 2 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/F
4.549 0.971 tNET FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/I3
5.363 0.814 tINS FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/F
5.971 0.608 tNET FF 1 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/I0
6.435 0.463 tINS FR 4 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/F
7.265 0.831 tNET RR 1 R8C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_1_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R8C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_1_s0/CLK
40.148 -0.032 tSu 1 R8C4[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.802, 39.555%; route: 3.943, 55.651%; tC2Q: 0.340, 4.794%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path24

Path Summary:

Slack 32.883
Data Arrival Time 7.265
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
0.520 0.340 tC2Q RF 10 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/Q
1.738 1.218 tNET FF 1 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/I1
2.498 0.760 tINS FR 3 R8C5[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n846_s9/F
2.813 0.315 tNET RR 1 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/I1
3.578 0.765 tINS RF 2 R8C4[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s10/F
4.549 0.971 tNET FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/I3
5.363 0.814 tINS FF 1 R12C4[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s5/F
5.971 0.608 tNET FF 1 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/I0
6.435 0.463 tINS FR 4 R14C4[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s4/F
7.265 0.831 tNET RR 1 R8C4[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R8C4[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CLK
40.148 -0.032 tSu 1 R8C4[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.802, 39.555%; route: 3.943, 55.651%; tC2Q: 0.340, 4.794%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path25

Path Summary:

Slack 32.933
Data Arrival Time 7.215
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_7_s2
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_7_s2/CLK
0.520 0.340 tC2Q RF 3 R15C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_7_s2/Q
1.118 0.598 tNET FF 1 R16C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s4/I2
1.932 0.814 tINS FF 3 R16C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s4/F
2.540 0.608 tNET FF 1 R15C12[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/I1
3.355 0.814 tINS FF 18 R15C12[3][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/F
3.983 0.628 tNET FF 1 R14C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_15_s8/I0
4.797 0.814 tINS FF 2 R14C11[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_15_s8/F
5.756 0.959 tNET FF 1 R13C14[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_15_s4/I2
6.351 0.594 tINS FR 16 R13C14[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_15_s4/F
7.215 0.865 tNET RR 1 R12C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_0_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R12C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_0_s0/CLK
40.148 -0.032 tSu 1 R12C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.037, 43.175%; route: 3.658, 51.997%; tC2Q: 0.340, 4.828%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/CLK
0.383 0.247 tC2Q RR 8 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/Q
0.385 0.002 tNET RR 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1590_s4/I0
0.661 0.276 tINS RF 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1590_s4/F
0.661 0.000 tNET FF 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/CLK
0.136 0.000 tHld 1 R6C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/CLK
0.383 0.247 tC2Q RR 7 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/Q
0.385 0.002 tNET RR 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1589_s2/I1
0.661 0.276 tINS RF 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1589_s2/F
0.661 0.000 tNET FF 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1/CLK
0.136 0.000 tHld 1 R5C13[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/CLK
0.383 0.247 tC2Q RR 4 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/Q
0.385 0.002 tNET RR 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1362_s4/I1
0.661 0.276 tINS RF 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1362_s4/F
0.661 0.000 tNET FF 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/CLK
0.136 0.000 tHld 1 R8C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/CLK
0.383 0.247 tC2Q RR 2 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/Q
0.385 0.002 tNET RR 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1196_s7/I0
0.661 0.276 tINS RF 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1196_s7/F
0.661 0.000 tNET FF 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1/CLK
0.136 0.000 tHld 1 R9C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/CLK
0.383 0.247 tC2Q RR 4 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/Q
0.385 0.002 tNET RR 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1435_s2/I1
0.661 0.276 tINS RF 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1435_s2/F
0.661 0.000 tNET FF 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/CLK
0.136 0.000 tHld 1 R11C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/CLK
0.383 0.247 tC2Q RR 4 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/Q
0.385 0.002 tNET RR 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1434_s4/I1
0.661 0.276 tINS RF 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1434_s4/F
0.661 0.000 tNET FF 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/CLK
0.136 0.000 tHld 1 R9C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_2_s0
To led_cnt_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C7[0][A] led_cnt_2_s0/CLK
0.383 0.247 tC2Q RR 3 R4C7[0][A] led_cnt_2_s0/Q
0.385 0.002 tNET RR 1 R4C7[0][A] n87_s2/I2
0.661 0.276 tINS RF 1 R4C7[0][A] n87_s2/F
0.661 0.000 tNET FF 1 R4C7[0][A] led_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C7[0][A] led_cnt_2_s0/CLK
0.136 0.000 tHld 1 R4C7[0][A] led_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_3_s0
To led_cnt_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C5[1][A] led_cnt_3_s0/CLK
0.383 0.247 tC2Q RR 2 R4C5[1][A] led_cnt_3_s0/Q
0.385 0.002 tNET RR 1 R4C5[1][A] n86_s2/I3
0.661 0.276 tINS RF 1 R4C5[1][A] n86_s2/F
0.661 0.000 tNET FF 1 R4C5[1][A] led_cnt_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C5[1][A] led_cnt_3_s0/CLK
0.136 0.000 tHld 1 R4C5[1][A] led_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_11_s0
To led_cnt_11_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C7[0][A] led_cnt_11_s0/CLK
0.383 0.247 tC2Q RR 3 R6C7[0][A] led_cnt_11_s0/Q
0.385 0.002 tNET RR 1 R6C7[0][A] n78_s2/I3
0.661 0.276 tINS RF 1 R6C7[0][A] n78_s2/F
0.661 0.000 tNET FF 1 R6C7[0][A] led_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C7[0][A] led_cnt_11_s0/CLK
0.136 0.000 tHld 1 R6C7[0][A] led_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_17_s0
To led_cnt_17_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C5[0][A] led_cnt_17_s0/CLK
0.383 0.247 tC2Q RR 3 R4C5[0][A] led_cnt_17_s0/Q
0.385 0.002 tNET RR 1 R4C5[0][A] n72_s2/I2
0.661 0.276 tINS RF 1 R4C5[0][A] n72_s2/F
0.661 0.000 tNET FF 1 R4C5[0][A] led_cnt_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C5[0][A] led_cnt_17_s0/CLK
0.136 0.000 tHld 1 R4C5[0][A] led_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_21_s0
To led_cnt_21_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C6[0][A] led_cnt_21_s0/CLK
0.383 0.247 tC2Q RR 2 R5C6[0][A] led_cnt_21_s0/Q
0.385 0.002 tNET RR 1 R5C6[0][A] n68_s2/I3
0.661 0.276 tINS RF 1 R5C6[0][A] n68_s2/F
0.661 0.000 tNET FF 1 R5C6[0][A] led_cnt_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C6[0][A] led_cnt_21_s0/CLK
0.136 0.000 tHld 1 R5C6[0][A] led_cnt_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_cnt_28_s0
To led_cnt_28_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C7[1][A] led_cnt_28_s0/CLK
0.383 0.247 tC2Q RR 3 R4C7[1][A] led_cnt_28_s0/Q
0.385 0.002 tNET RR 1 R4C7[1][A] n61_s2/I3
0.661 0.276 tINS RF 1 R4C7[1][A] n61_s2/F
0.661 0.000 tNET FF 1 R4C7[1][A] led_cnt_28_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C7[1][A] led_cnt_28_s0/CLK
0.136 0.000 tHld 1 R4C7[1][A] led_cnt_28_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/CLK
0.383 0.247 tC2Q RR 4 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/Q
0.386 0.003 tNET RR 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1173_s4/I0
0.662 0.276 tINS RF 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1173_s4/F
0.662 0.000 tNET FF 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3/CLK
0.136 0.000 tHld 1 R8C16[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/j_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/CLK
0.383 0.247 tC2Q RR 4 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/Q
0.386 0.003 tNET RR 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1365_s4/I1
0.662 0.276 tINS RF 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1365_s4/F
0.662 0.000 tNET FF 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1/CLK
0.136 0.000 tHld 1 R6C15[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/CLK
0.383 0.247 tC2Q RR 3 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/Q
0.386 0.003 tNET RR 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1433_s2/I3
0.662 0.276 tINS RF 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1433_s2/F
0.662 0.000 tNET FF 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0/CLK
0.136 0.000 tHld 1 R9C16[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/CLK
0.383 0.247 tC2Q RR 4 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/Q
0.386 0.003 tNET RR 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n60_s1/I3
0.662 0.276 tINS RF 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n60_s1/F
0.662 0.000 tNET FF 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1/CLK
0.136 0.000 tHld 1 R7C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From led_cnt_0_s0
To led_cnt_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C5[1][A] led_cnt_0_s0/CLK
0.383 0.247 tC2Q RR 5 R5C5[1][A] led_cnt_0_s0/Q
0.386 0.003 tNET RR 1 R5C5[1][A] n89_s4/I0
0.662 0.276 tINS RF 1 R5C5[1][A] n89_s4/F
0.662 0.000 tNET FF 1 R5C5[1][A] led_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C5[1][A] led_cnt_0_s0/CLK
0.136 0.000 tHld 1 R5C5[1][A] led_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From led_cnt_7_s0
To led_cnt_7_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C5[0][A] led_cnt_7_s0/CLK
0.383 0.247 tC2Q RR 3 R5C5[0][A] led_cnt_7_s0/Q
0.386 0.003 tNET RR 1 R5C5[0][A] n82_s2/I2
0.662 0.276 tINS RF 1 R5C5[0][A] n82_s2/F
0.662 0.000 tNET FF 1 R5C5[0][A] led_cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R5C5[0][A] led_cnt_7_s0/CLK
0.136 0.000 tHld 1 R5C5[0][A] led_cnt_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From led_cnt_8_s0
To led_cnt_8_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C7[1][A] led_cnt_8_s0/CLK
0.383 0.247 tC2Q RR 5 R6C7[1][A] led_cnt_8_s0/Q
0.386 0.003 tNET RR 1 R6C7[1][A] n81_s5/I0
0.662 0.276 tINS RF 1 R6C7[1][A] n81_s5/F
0.662 0.000 tNET FF 1 R6C7[1][A] led_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C7[1][A] led_cnt_8_s0/CLK
0.136 0.000 tHld 1 R6C7[1][A] led_cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From led_cnt_10_s0
To led_cnt_10_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C6[0][A] led_cnt_10_s0/CLK
0.383 0.247 tC2Q RR 4 R6C6[0][A] led_cnt_10_s0/Q
0.386 0.003 tNET RR 1 R6C6[0][A] n79_s2/I0
0.662 0.276 tINS RF 1 R6C6[0][A] n79_s2/F
0.662 0.000 tNET FF 1 R6C6[0][A] led_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C6[0][A] led_cnt_10_s0/CLK
0.136 0.000 tHld 1 R6C6[0][A] led_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/CLK
0.383 0.247 tC2Q RR 7 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/Q
0.387 0.003 tNET RR 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n674_s3/I0
0.663 0.276 tINS RF 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n674_s3/F
0.663 0.000 tNET FF 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/CLK
0.136 0.000 tHld 1 R12C11[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/CLK
0.383 0.247 tC2Q RR 5 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/Q
0.387 0.003 tNET RR 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1376_s4/I0
0.663 0.276 tINS RF 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1376_s4/F
0.663 0.000 tNET FF 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1/CLK
0.136 0.000 tHld 1 R4C15[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/CLK
0.383 0.247 tC2Q RR 5 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/Q
0.387 0.003 tNET RR 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1369_s4/I1
0.663 0.276 tINS RF 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1369_s4/F
0.663 0.000 tNET FF 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1/CLK
0.136 0.000 tHld 1 R4C14[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/CLK
0.383 0.247 tC2Q RR 12 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/Q
0.387 0.003 tNET RR 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1199_s2/I0
0.663 0.276 tINS RF 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1199_s2/F
0.663 0.000 tNET FF 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1/CLK
0.136 0.000 tHld 1 R9C14[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/CLK
0.383 0.247 tC2Q RR 6 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/Q
0.387 0.003 tNET RR 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n63_s3/I2
0.663 0.276 tINS RF 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n63_s3/F
0.663 0.000 tNET FF 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3/CLK
0.136 0.000 tHld 1 R11C8[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 37.807
Data Arrival Time 2.222
Data Required Time 40.029
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 8 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.029 -0.152 tSu 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path2

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLK
40.148 -0.032 tSu 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path3

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLK
40.148 -0.032 tSu 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path4

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
40.148 -0.032 tSu 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path5

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLK
40.148 -0.032 tSu 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path6

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLK
40.148 -0.032 tSu 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path7

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
40.148 -0.032 tSu 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path8

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLK
40.148 -0.032 tSu 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path9

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLK
40.148 -0.032 tSu 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path10

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLK
40.148 -0.032 tSu 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path11

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLK
40.148 -0.032 tSu 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path12

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLK
40.148 -0.032 tSu 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path13

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK
40.148 -0.032 tSu 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path14

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
40.148 -0.032 tSu 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path15

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLK
40.148 -0.032 tSu 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path16

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLK
40.148 -0.032 tSu 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path17

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLK
40.148 -0.032 tSu 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path18

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLK
40.148 -0.032 tSu 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path19

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLK
40.148 -0.032 tSu 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path20

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLK
40.148 -0.032 tSu 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path21

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK
40.148 -0.032 tSu 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path22

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK
40.148 -0.032 tSu 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path23

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLK
40.148 -0.032 tSu 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path24

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLK
40.148 -0.032 tSu 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path25

Path Summary:

Slack 37.927
Data Arrival Time 2.222
Data Required Time 40.148
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.520 0.340 tC2Q RF 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
2.222 1.702 tNET FF 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLK
40.148 -0.032 tSu 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 8 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
0.146 0.009 tHld 1 BSRAM_R10[1] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLK
0.146 0.009 tHld 1 R4C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.146 0.009 tHld 1 R4C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.146 0.009 tHld 1 R4C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLK
0.146 0.009 tHld 1 R4C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLK
0.146 0.009 tHld 1 R4C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.146 0.009 tHld 1 R4C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLK
0.146 0.009 tHld 1 R4C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLK
0.146 0.009 tHld 1 R4C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLK
0.146 0.009 tHld 1 R4C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLK
0.146 0.009 tHld 1 R4C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLK
0.146 0.009 tHld 1 R4C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK
0.146 0.009 tHld 1 R4C10[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK
0.146 0.009 tHld 1 R9C10[3][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLK
0.146 0.009 tHld 1 R6C9[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLK
0.146 0.009 tHld 1 R6C9[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLK
0.146 0.009 tHld 1 R6C9[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLK
0.146 0.009 tHld 1 R6C9[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLK
0.146 0.009 tHld 1 R6C9[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLK
0.146 0.009 tHld 1 R6C9[2][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK
0.146 0.009 tHld 1 R6C10[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK
0.146 0.009 tHld 1 R6C10[0][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLK
0.146 0.009 tHld 1 R6C10[1][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLK
0.146 0.009 tHld 1 R6C10[1][B] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack 1.382
Data Arrival Time 1.528
Data Required Time 0.146
From u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0
To u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0
Launch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK
0.383 0.247 tC2Q RR 202 R7C8[0][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q
1.528 1.144 tNET RR 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 277 R20C0 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLK
0.146 0.009 tHld 1 R6C10[2][A] u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: led_cnt_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_30_s0/CLK

MPW2

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: led_cnt_28_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_28_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_28_s0/CLK

MPW3

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: led_cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_24_s0/CLK

MPW4

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: led_cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: led_cnt_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_0_s0/CLK

MPW6

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CLK

MPW7

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0/CLK

MPW8

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK

MPW9

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK

MPW10

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
Objects: u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
20.193 0.193 tNET FF u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT
40.136 0.136 tNET RR u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
277 GW_OSC_CLK_d 31.411 0.489
202 RST_N 34.149 2.306
34 User_model_state[1] 33.145 1.710
28 full 31.491 1.578
23 tdo_bit_cnt[3] 35.093 1.001
23 cstate[2] 33.206 1.366
23 wren_Z 35.027 1.476
22 n1474_4 33.288 1.122
22 cstate[0] 32.855 1.003
22 cstate[1] 33.214 1.114

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R13C16 87.50%
R6C10 80.56%
R12C16 80.56%
R12C7 79.17%
R4C10 77.78%
R6C9 77.78%
R4C9 76.39%
R4C7 75.00%
R6C7 75.00%
R15C9 70.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command