Top Level Module |
Top |
Synthesis Process |
Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.19s, Peak memory usage = 245.988MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 245.988MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 245.988MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 245.988MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 245.988MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 245.988MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 245.988MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 245.988MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 245.988MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 245.988MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 245.988MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.346s, Peak memory usage = 252.055MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 252.055MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 252.055MB
|
Total Time and Memory Usage |
CPU time = 0h 0m 0.62s, Elapsed time = 0h 0m 0.638s, Peak memory usage = 252.055MB |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk |
0.000 |
0.000 |
tCL |
RR |
277 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT |
0.538 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/rden_s0/CLK |
0.878 |
0.340 |
tC2Q |
RF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/rden_s0/Q |
1.589 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/FIFO_rden_s0/I1 |
2.403 |
0.814 |
tINS |
FF |
6 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/FIFO_rden_s0/F |
3.115 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n101_s0/I1 |
3.929 |
0.814 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n101_s0/F |
4.640 |
0.711 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1 |
5.415 |
0.774 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT |
5.415 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN |
5.457 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT |
5.457 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN |
5.499 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/COUT |
5.499 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/CIN |
5.541 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/COUT |
5.541 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/CIN |
5.584 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/COUT |
5.584 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/CIN |
5.626 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/COUT |
5.626 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/CIN |
5.668 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/COUT |
5.668 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/CIN |
5.710 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/COUT |
5.710 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/CIN |
5.753 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_8_s/COUT |
5.753 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/CIN |
5.795 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_9_s/COUT |
5.795 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/CIN |
5.837 |
0.042 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_10_s/COUT |
5.837 |
0.000 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_11_s/CIN |
6.254 |
0.417 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rbin_next_11_s/SUM |
6.966 |
0.711 |
tNET |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n249_s0/I0 |
7.676 |
0.710 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n249_s0/COUT |
8.387 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rempty_val_s1/I0 |
9.152 |
0.765 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/rempty_val_s1/F |
9.863 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Empty_s0/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk |
0.000 |
0.000 |
tCL |
RR |
277 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT |
0.538 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
0.878 |
0.340 |
tC2Q |
RF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q |
1.589 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1 |
2.403 |
0.814 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F |
3.115 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1 |
3.929 |
0.814 |
tINS |
FF |
28 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
4.640 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/I0 |
5.405 |
0.765 |
tINS |
FF |
9 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/F |
6.116 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/I3 |
6.580 |
0.464 |
tINS |
FF |
3 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/F |
7.292 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s1/I1 |
8.106 |
0.814 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s1/F |
8.817 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s0/I2 |
9.412 |
0.594 |
tINS |
FR |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s0/F |
9.950 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/checksum_add_0_s1/CE |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk |
0.000 |
0.000 |
tCL |
RR |
277 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT |
0.538 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
0.878 |
0.340 |
tC2Q |
RF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q |
1.589 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1 |
2.403 |
0.814 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F |
3.115 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1 |
3.929 |
0.814 |
tINS |
FF |
28 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
4.640 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/I0 |
5.405 |
0.765 |
tINS |
FF |
9 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/F |
6.116 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/I3 |
6.580 |
0.464 |
tINS |
FF |
3 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/F |
7.292 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s1/I1 |
8.106 |
0.814 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s1/F |
8.817 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s0/I2 |
9.412 |
0.594 |
tINS |
FR |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s0/F |
9.950 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/checksum_add_1_s1/CE |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk |
0.000 |
0.000 |
tCL |
RR |
277 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT |
0.538 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
0.878 |
0.340 |
tC2Q |
RF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q |
1.589 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1 |
2.403 |
0.814 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F |
3.115 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1 |
3.929 |
0.814 |
tINS |
FF |
28 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
4.640 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s50/I2 |
5.249 |
0.609 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s50/F |
5.961 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s44/I2 |
6.570 |
0.609 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s44/F |
7.281 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s38/I3 |
7.745 |
0.464 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s38/F |
8.457 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s34/I3 |
8.920 |
0.464 |
tINS |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/n853_s34/F |
9.632 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U2/sda_out_s2/D |
AT |
DELAY |
TYPE |
RF |
FANOUT |
NODE |
0.000 |
0.000 |
|
|
|
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT.default_clk |
0.000 |
0.000 |
tCL |
RR |
277 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U1/osc_inst/OSCOUT |
0.538 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
0.878 |
0.340 |
tC2Q |
RF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/Q |
1.589 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/I1 |
2.403 |
0.814 |
tINS |
FF |
2 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/n7_s2/F |
3.115 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/I1 |
3.929 |
0.814 |
tINS |
FF |
28 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
4.640 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/I0 |
5.405 |
0.765 |
tINS |
FF |
9 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1640_s4/F |
6.116 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/I3 |
6.580 |
0.464 |
tINS |
FF |
3 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/n1486_s3/F |
7.292 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_7_s8/I0 |
8.056 |
0.765 |
tINS |
FF |
8 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_7_s8/F |
8.768 |
0.711 |
tNET |
FF |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s5/I3 |
9.231 |
0.463 |
tINS |
FR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s5/F |
9.769 |
0.538 |
tNET |
RR |
1 |
u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C/U3/tdo_fifo_in_0_s0/CE |