Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\goconfig_uart\goconfig_uart.v
E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\gowin_rpll\gowin_rpll.v
E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18MG196C7/I6
Device GW2A-18
Created Time Tue Dec 17 17:27:27 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.223s, Peak memory usage = 460.074MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 460.074MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 460.074MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 460.074MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 460.074MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 460.074MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 460.074MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 460.074MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 460.074MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 460.074MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 460.074MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.323s, Peak memory usage = 460.074MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 460.074MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 460.074MB
Total Time and Memory Usage CPU time = 0h 0m 0.667s, Elapsed time = 0h 0m 0.706s, Peak memory usage = 460.074MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 12
I/O Buf 12
    IBUF 4
    OBUF 8
Register 546
    DFFS 1
    DFFP 6
    DFFPE 15
    DFFC 258
    DFFCE 266
LUT 830
    LUT2 129
    LUT3 215
    LUT4 486
INV 7
    INV 7
CLOCK 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 837(837 LUT, 0 ALU) / 20736 5%
Register 546 / 15894 4%
  --Register as Latch 0 / 15894 0%
  --Register as FF 546 / 15894 4%
BSRAM 0 / 46 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_in Base 20.000 50.0 0.000 10.000 clk_in_ibuf/I
2 pll_25M/rpll_inst/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 clk_in_ibuf/I clk_in pll_25M/rpll_inst/CLKOUT
3 pll_25M/rpll_inst/CLKOUTP.default_gen_clk Generated 40.000 25.0 0.000 20.000 clk_in_ibuf/I clk_in pll_25M/rpll_inst/CLKOUTP
4 pll_25M/rpll_inst/CLKOUTD.default_gen_clk Generated 80.000 12.5 0.000 40.000 clk_in_ibuf/I clk_in pll_25M/rpll_inst/CLKOUTD
5 pll_25M/rpll_inst/CLKOUTD3.default_gen_clk Generated 120.000 8.3 0.000 60.000 clk_in_ibuf/I clk_in pll_25M/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 pll_25M/rpll_inst/CLKOUT.default_gen_clk 25.000(MHz) 163.934(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 16.950
Data Arrival Time 4.223
Data Required Time 21.173
From inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0
To inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1
Launch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[F]
Latch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
0.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
1.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0/CLK
1.365 0.290 tC2Q RF 2 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0/Q
1.957 0.593 tNET FF 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n264_s2/I0
2.603 0.646 tINS FF 2 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n264_s2/F
3.196 0.593 tNET FF 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s3/I2
3.773 0.577 tINS FR 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s3/F
4.223 0.450 tNET RR 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
20.625 0.625 tCL FF 547 pll_25M/rpll_inst/CLKOUT
21.217 0.593 tNET FF 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CLK
21.173 -0.044 tSu 1 inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1
Path Statistics:
Clock Skew: 0.143
Setup Relationship: 20.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 1.224, 38.865%; route: 1.635, 51.925%; tC2Q: 0.290, 9.210%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 2

Path Summary:
Slack 33.929
Data Arrival Time 7.102
Data Required Time 41.031
From inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0
Launch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
0.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
1.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
1.365 0.290 tC2Q RF 5 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.957 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.651 0.694 tINS FF 6 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
3.243 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.937 0.694 tINS FF 8 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
4.530 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/I1
5.223 0.694 tINS FF 3 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/F
5.816 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/I1
6.510 0.694 tINS FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/F
7.102 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
40.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
41.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/CLK
41.031 -0.044 tSu 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 3

Path Summary:
Slack 33.929
Data Arrival Time 7.102
Data Required Time 41.031
From inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0
Launch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
0.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
1.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
1.365 0.290 tC2Q RF 5 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.957 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.651 0.694 tINS FF 6 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
3.243 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.937 0.694 tINS FF 8 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
4.530 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/I1
5.223 0.694 tINS FF 3 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/F
5.816 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s2/I1
6.510 0.694 tINS FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s2/F
7.102 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
40.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
41.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0/CLK
41.031 -0.044 tSu 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 4

Path Summary:
Slack 33.929
Data Arrival Time 7.102
Data Required Time 41.031
From inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0
Launch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
0.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
1.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
1.365 0.290 tC2Q RF 5 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.957 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.651 0.694 tINS FF 6 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
3.243 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.937 0.694 tINS FF 8 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
4.530 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/I1
5.223 0.694 tINS FF 2 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/F
5.816 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n106_s2/I1
6.510 0.694 tINS FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n106_s2/F
7.102 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
40.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
41.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0/CLK
41.031 -0.044 tSu 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 5

Path Summary:
Slack 33.929
Data Arrival Time 7.102
Data Required Time 41.031
From inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0
Launch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk pll_25M/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
0.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
1.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
1.365 0.290 tC2Q RF 5 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.957 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.651 0.694 tINS FF 6 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
3.243 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.937 0.694 tINS FF 8 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
4.530 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/I1
5.223 0.694 tINS FF 2 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/F
5.816 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s2/I1
6.510 0.694 tINS FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s2/F
7.102 0.593 tNET FF 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 pll_25M/rpll_inst/CLKOUT.default_gen_clk
40.625 0.625 tCL RR 547 pll_25M/rpll_inst/CLKOUT
41.075 0.450 tNET RR 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0/CLK
41.031 -0.044 tSu 1 inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%