Timing Messages
Report Title | Timing Analysis Report |
Design File | E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\fpga_project.cst |
Timing Constraint File | --- |
Tool Version | V1.9.11 (64-bit) |
Part Number | GW2A-LV18MG196C7/I6 |
Device | GW2A-18 |
Created Time | Tue Dec 17 17:27:31 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C7/I6 |
Hold Delay Model | Fast 1.05V 0C C7/I6 |
Numbers of Paths Analyzed | 2689 |
Numbers of Endpoints Analyzed | 1381 |
Numbers of Falling Endpoints | 69 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk_in | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_in_ibuf/I | ||
2 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | clk_in_ibuf/I | clk_in | pll_25M/rpll_inst/CLKOUT |
3 | pll_25M/rpll_inst/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | clk_in_ibuf/I | clk_in | pll_25M/rpll_inst/CLKOUTP |
4 | pll_25M/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.500 | 0.000 | 40.000 | clk_in_ibuf/I | clk_in | pll_25M/rpll_inst/CLKOUTD |
5 | pll_25M/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.333 | 0.000 | 60.000 | clk_in_ibuf/I | clk_in | pll_25M/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | 25.000(MHz) | 157.271(MHz) | 5 | TOP |
No timing paths to get frequency of clk_in!
No timing paths to get frequency of pll_25M/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of pll_25M/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of pll_25M/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk_in | Setup | 0.000 | 0 |
clk_in | Hold | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
pll_25M/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 33.642 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_3_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 6.315 |
2 | 33.733 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 6.223 |
3 | 34.110 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_RD_PAGE_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.846 |
4 | 34.131 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_IDLE_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.825 |
5 | 34.177 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.779 |
6 | 34.189 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.767 |
7 | 34.219 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_DIS_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.737 |
8 | 34.224 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_3_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.732 |
9 | 34.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.642 |
10 | 34.330 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.626 |
11 | 34.335 | led_cnt_0_s0/Q | led_cnt_27_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.621 |
12 | 34.406 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.550 |
13 | 34.436 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s12/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.520 |
14 | 34.481 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s1/CE | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.475 |
15 | 34.523 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_PAGE_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.434 |
16 | 34.560 | led_cnt_16_s0/Q | led_cnt_9_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.396 |
17 | 34.560 | led_cnt_16_s0/Q | led_cnt_12_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.396 |
18 | 34.570 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_CHK_OP_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.387 |
19 | 17.291 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 2.669 |
20 | 17.291 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 2.669 |
21 | 34.636 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.OP_RD_ID_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.320 |
22 | 34.643 | led_cnt_0_s0/Q | led_cnt_25_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.313 |
23 | 34.744 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_op_end_flag_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.213 |
24 | 34.771 | led_cnt_0_s0/Q | led_cnt_26_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.185 |
25 | 34.778 | led_cnt_0_s0/Q | led_cnt_24_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 40.000 | 0.000 | 5.178 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.532 | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/Q | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
2 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
3 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
4 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
5 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
6 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
7 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
8 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
9 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
10 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
11 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
12 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
13 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/Q | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
14 | 0.532 | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/Q | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
15 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
16 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
17 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
18 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
19 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
20 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
21 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
22 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
23 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
24 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
25 | 0.532 | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/Q | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/D | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.546 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg_s7/PRESET | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
2 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_vld_reg_s5/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
3 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_en_reg_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
4 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
5 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
6 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_pos_reg_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
7 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_7_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
8 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_reg_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
9 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
10 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
11 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_2_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
12 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/gap_cnt_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
13 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg1_s0/PRESET | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
14 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
15 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_mosi_reg_s0/PRESET | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
16 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
17 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
18 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
19 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
20 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
21 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
22 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
23 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
24 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_2_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
25 | 18.314 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_3_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] | 20.000 | -0.004 | 1.646 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_en_s4/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
2 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_0_s3/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
3 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_1_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
4 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_2_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
5 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_3_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
6 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_4_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
7 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_5_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
8 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
9 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
10 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_8_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
11 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_9_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
12 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_10_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
13 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_11_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
14 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_12_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
15 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_13_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
16 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
17 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ms/ms_flag_reg_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
18 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_vld_reg_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
19 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
20 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
21 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
22 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
23 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
24 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_0_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
25 | 1.156 | inst_uart/inst_GW_UART/rstn_flag_s2/Q | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_1_s0/CLEAR | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 1.170 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | led_cnt_30_s0 |
2 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | led_cnt_28_s0 |
3 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | led_cnt_24_s0 |
4 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | led_cnt_16_s0 |
5 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | led_cnt_0_s0 |
6 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | inst_uart/inst_GW_UART/rstn_cmd_data_5_s1 |
7 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_21_s0 |
8 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | inst_uart/inst_GW_UART/inst_uart_spi/idle_cnt_6_s1 |
9 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1 |
10 | 17.866 | 19.116 | 1.250 | Low Pulse Width | pll_25M/rpll_inst/CLKOUT.default_gen_clk | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 33.642 |
Data Arrival Time | 13.002 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_3_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.651 | 1.674 | tNET | FF | 1 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/I1 |
9.345 | 0.694 | tINS | FF | 3 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/F |
9.867 | 0.522 | tNET | FF | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/I2 |
10.444 | 0.577 | tINS | FR | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/F |
10.660 | 0.216 | tNET | RR | 1 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/I2 |
11.124 | 0.464 | tINS | RF | 3 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/F |
11.445 | 0.322 | tNET | FF | 1 | R26C22[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s9/I1 |
12.131 | 0.686 | tINS | FR | 2 | R26C22[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s9/F |
13.002 | 0.871 | tNET | RR | 1 | R27C23[1][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R27C23[1][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_3_s1/CLK |
46.644 | -0.044 | tSu | 1 | R27C23[1][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.421, 38.343%; route: 3.603, 57.064%; tC2Q: 0.290, 4.592% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path2
Path Summary:
Slack | 33.733 |
Data Arrival Time | 12.910 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.651 | 1.674 | tNET | FF | 1 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/I1 |
9.345 | 0.694 | tINS | FF | 3 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/F |
9.867 | 0.522 | tNET | FF | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/I2 |
10.444 | 0.577 | tINS | FR | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/F |
10.660 | 0.216 | tNET | RR | 1 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/I2 |
11.124 | 0.464 | tINS | RF | 3 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/F |
11.632 | 0.509 | tNET | FF | 1 | R26C22[2][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s7/I2 |
12.041 | 0.409 | tINS | FR | 1 | R26C22[2][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s7/F |
12.910 | 0.869 | tNET | RR | 1 | R26C21[2][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R26C21[2][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s1/CLK |
46.644 | -0.044 | tSu | 1 | R26C21[2][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.144, 34.450%; route: 3.789, 60.890%; tC2Q: 0.290, 4.660% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path3
Path Summary:
Slack | 34.110 |
Data Arrival Time | 12.533 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_RD_PAGE_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.521 | 0.888 | tNET | FF | 1 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/I1 |
10.087 | 0.566 | tINS | FF | 6 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/F |
10.322 | 0.235 | tNET | FF | 1 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/I2 |
11.016 | 0.694 | tINS | FF | 4 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/F |
11.847 | 0.831 | tNET | FF | 1 | R20C28[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_RD_PAGE_s1/I0 |
12.533 | 0.686 | tINS | FR | 1 | R20C28[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_RD_PAGE_s1/F |
12.533 | 0.000 | tNET | RR | 1 | R20C28[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_RD_PAGE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R20C28[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_RD_PAGE_s0/CLK |
46.644 | -0.044 | tSu | 1 | R20C28[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_RD_PAGE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.593, 44.347%; route: 2.963, 50.692%; tC2Q: 0.290, 4.961% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path4
Path Summary:
Slack | 34.131 |
Data Arrival Time | 12.512 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_IDLE_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.612 | 0.979 | tNET | FF | 1 | R21C30[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s5/I3 |
10.189 | 0.577 | tINS | FR | 2 | R21C30[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s5/F |
10.407 | 0.217 | tNET | RR | 1 | R21C29[3][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s2/I2 |
10.973 | 0.566 | tINS | RF | 2 | R21C29[3][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s2/F |
11.800 | 0.827 | tNET | FF | 1 | R18C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_IDLE_s2/I1 |
12.512 | 0.712 | tINS | FR | 1 | R18C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_IDLE_s2/F |
12.512 | 0.000 | tNET | RR | 1 | R18C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_IDLE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R18C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_IDLE_s0/CLK |
46.644 | -0.044 | tSu | 1 | R18C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_IDLE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.503, 42.961%; route: 3.033, 52.060%; tC2Q: 0.290, 4.979% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path5
Path Summary:
Slack | 34.177 |
Data Arrival Time | 12.467 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/I2 |
9.338 | 0.694 | tINS | FF | 2 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/F |
9.839 | 0.502 | tNET | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/I3 |
10.406 | 0.566 | tINS | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/F |
10.714 | 0.309 | tNET | FF | 1 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/I3 |
11.427 | 0.712 | tINS | FR | 3 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/F |
11.648 | 0.221 | tNET | RR | 1 | R25C38[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s7/I0 |
12.057 | 0.409 | tINS | RR | 1 | R25C38[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s7/F |
12.467 | 0.410 | tNET | RR | 1 | R26C38[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R26C38[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s1/CLK |
46.644 | -0.044 | tSu | 1 | R26C38[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.381, 41.202%; route: 3.108, 53.780%; tC2Q: 0.290, 5.018% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path6
Path Summary:
Slack | 34.189 |
Data Arrival Time | 12.455 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/I2 |
9.338 | 0.694 | tINS | FF | 2 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/F |
9.839 | 0.502 | tNET | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/I3 |
10.406 | 0.566 | tINS | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/F |
10.714 | 0.309 | tNET | FF | 1 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/I3 |
11.427 | 0.712 | tINS | FR | 3 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/F |
11.430 | 0.003 | tNET | RR | 1 | R25C37[3][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s6/I0 |
12.008 | 0.577 | tINS | RR | 2 | R25C37[3][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s6/F |
12.455 | 0.447 | tNET | RR | 1 | R24C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R24C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s1/CLK |
46.644 | -0.044 | tSu | 1 | R24C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.550, 44.215%; route: 2.927, 50.757%; tC2Q: 0.290, 5.028% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path7
Path Summary:
Slack | 34.219 |
Data Arrival Time | 12.424 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_DIS_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.521 | 0.888 | tNET | FF | 1 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/I1 |
10.087 | 0.566 | tINS | FF | 6 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/F |
10.322 | 0.235 | tNET | FF | 1 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/I2 |
11.016 | 0.694 | tINS | FF | 4 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/F |
11.847 | 0.831 | tNET | FF | 1 | R20C30[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_DIS_s1/I0 |
12.424 | 0.577 | tINS | FR | 1 | R20C30[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_DIS_s1/F |
12.424 | 0.000 | tNET | RR | 1 | R20C30[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_DIS_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R20C30[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_DIS_s0/CLK |
46.644 | -0.044 | tSu | 1 | R20C30[0][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_DIS_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.484, 43.293%; route: 2.963, 51.653%; tC2Q: 0.290, 5.055% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path8
Path Summary:
Slack | 34.224 |
Data Arrival Time | 12.419 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_3_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/I2 |
9.338 | 0.694 | tINS | FF | 2 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/F |
9.839 | 0.502 | tNET | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/I3 |
10.406 | 0.566 | tINS | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/F |
10.714 | 0.309 | tNET | FF | 1 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/I3 |
11.427 | 0.712 | tINS | FR | 3 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/F |
11.430 | 0.003 | tNET | RR | 1 | R25C37[3][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s6/I0 |
12.008 | 0.577 | tINS | RR | 2 | R25C37[3][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_2_s6/F |
12.419 | 0.412 | tNET | RR | 1 | R25C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_3_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R25C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_3_s1/CLK |
46.644 | -0.044 | tSu | 1 | R25C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.550, 44.488%; route: 2.892, 50.453%; tC2Q: 0.290, 5.059% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path9
Path Summary:
Slack | 34.314 |
Data Arrival Time | 12.329 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.651 | 1.674 | tNET | FF | 1 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/I1 |
9.345 | 0.694 | tINS | FF | 3 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/F |
9.867 | 0.522 | tNET | FF | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/I2 |
10.444 | 0.577 | tINS | FR | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/F |
10.660 | 0.216 | tNET | RR | 1 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/I2 |
11.124 | 0.464 | tINS | RF | 3 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/F |
11.342 | 0.219 | tNET | FF | 1 | R26C23[1][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s9/I2 |
11.920 | 0.577 | tINS | FR | 1 | R26C23[1][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s9/F |
12.329 | 0.410 | tNET | RR | 1 | R26C22[0][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R26C22[0][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s1/CLK |
46.644 | -0.044 | tSu | 1 | R26C22[0][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.312, 40.987%; route: 3.040, 53.873%; tC2Q: 0.290, 5.140% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path10
Path Summary:
Slack | 34.330 |
Data Arrival Time | 12.313 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.651 | 1.674 | tNET | FF | 1 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/I1 |
9.345 | 0.694 | tINS | FF | 3 | R27C23[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_next_2_s14/F |
9.867 | 0.522 | tNET | FF | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/I2 |
10.444 | 0.577 | tINS | FR | 1 | R26C24[3][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s16/F |
10.660 | 0.216 | tNET | RR | 1 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/I2 |
11.124 | 0.464 | tINS | RF | 3 | R26C24[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_1_s10/F |
11.445 | 0.322 | tNET | FF | 1 | R26C22[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s9/I1 |
12.131 | 0.686 | tINS | FR | 2 | R26C22[3][B] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s9/F |
12.313 | 0.182 | tNET | RR | 1 | R26C22[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R26C22[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s1/CLK |
46.644 | -0.044 | tSu | 1 | R26C22[2][A] | inst_uart/inst_GW_UART/inst_uart_spi/xxx_flash_fsm_curr_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.421, 43.037%; route: 2.915, 51.808%; tC2Q: 0.290, 5.155% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path11
Path Summary:
Slack | 34.335 |
Data Arrival Time | 12.309 |
Data Required Time | 46.644 |
From | led_cnt_0_s0 |
To | led_cnt_27_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[0][A] | led_cnt_0_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 6 | R30C36[0][A] | led_cnt_0_s0/Q |
7.822 | 0.845 | tNET | FF | 1 | R30C31[2][B] | n77_s3/I0 |
8.516 | 0.694 | tINS | FF | 7 | R30C31[2][B] | n77_s3/F |
9.039 | 0.522 | tNET | FF | 1 | R30C32[0][B] | n68_s3/I0 |
9.732 | 0.694 | tINS | FF | 9 | R30C32[0][B] | n68_s3/F |
10.394 | 0.661 | tNET | FF | 1 | R30C35[1][A] | n55_s3/I0 |
11.087 | 0.694 | tINS | FF | 3 | R30C35[1][A] | n55_s3/F |
11.596 | 0.509 | tNET | FF | 1 | R30C37[1][A] | n54_s2/I0 |
12.309 | 0.712 | tINS | FR | 1 | R30C37[1][A] | n54_s2/F |
12.309 | 0.000 | tNET | RR | 1 | R30C37[1][A] | led_cnt_27_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C37[1][A] | led_cnt_27_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C37[1][A] | led_cnt_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.794, 49.699%; route: 2.538, 45.142%; tC2Q: 0.290, 5.159% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path12
Path Summary:
Slack | 34.406 |
Data Arrival Time | 12.237 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/I2 |
9.338 | 0.694 | tINS | FF | 2 | R26C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_next_1_s11/F |
9.839 | 0.502 | tNET | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/I3 |
10.406 | 0.566 | tINS | FF | 1 | R25C38[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s8/F |
10.714 | 0.309 | tNET | FF | 1 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/I3 |
11.427 | 0.712 | tINS | FR | 3 | R25C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s5/F |
11.648 | 0.221 | tNET | RR | 1 | R25C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s3/I1 |
12.057 | 0.409 | tINS | RR | 1 | R25C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s3/F |
12.237 | 0.180 | tNET | RR | 1 | R25C38[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R25C38[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s1/CLK |
46.644 | -0.044 | tSu | 1 | R25C38[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/fsm_curr_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.381, 42.907%; route: 2.879, 51.868%; tC2Q: 0.290, 5.225% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path13
Path Summary:
Slack | 34.436 |
Data Arrival Time | 12.208 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s12 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.521 | 0.888 | tNET | FF | 1 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/I1 |
10.087 | 0.566 | tINS | FF | 6 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/F |
10.757 | 0.669 | tNET | FF | 1 | R26C30[0][A] | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s5/I0 |
11.323 | 0.566 | tINS | FF | 2 | R26C30[0][A] | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s5/F |
11.521 | 0.198 | tNET | FF | 1 | R26C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n915_s4/I0 |
12.208 | 0.686 | tINS | FR | 1 | R26C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n915_s4/F |
12.208 | 0.000 | tNET | RR | 1 | R26C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s12/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R26C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s12/CLK |
46.644 | -0.044 | tSu | 1 | R26C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/ms_op_start_reg_s12 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.465, 44.653%; route: 2.765, 50.093%; tC2Q: 0.290, 5.253% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path14
Path Summary:
Slack | 34.481 |
Data Arrival Time | 12.162 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/CLK |
6.977 | 0.290 | tC2Q | RF | 4 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q |
7.814 | 0.837 | tNET | FF | 1 | R29C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n758_s4/I1 |
8.381 | 0.566 | tINS | FF | 8 | R29C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n758_s4/F |
8.713 | 0.333 | tNET | FF | 1 | R29C36[3][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s4/I1 |
9.407 | 0.694 | tINS | FF | 3 | R29C36[3][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s4/F |
9.923 | 0.516 | tNET | FF | 1 | R27C36[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s2/I2 |
10.635 | 0.712 | tINS | FR | 2 | R27C36[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s2/F |
10.852 | 0.217 | tNET | RR | 1 | R26C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s3/I2 |
11.539 | 0.686 | tINS | RR | 1 | R26C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s3/F |
12.162 | 0.624 | tNET | RR | 1 | R29C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R29C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s1/CLK |
46.644 | -0.044 | tSu | 1 | R29C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_cnt_en_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.659, 48.561%; route: 2.526, 46.142%; tC2Q: 0.290, 5.297% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path15
Path Summary:
Slack | 34.523 |
Data Arrival Time | 12.121 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_PAGE_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.521 | 0.888 | tNET | FF | 1 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/I1 |
10.087 | 0.566 | tINS | FF | 6 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/F |
10.322 | 0.235 | tNET | FF | 1 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/I2 |
11.016 | 0.694 | tINS | FF | 4 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/F |
11.544 | 0.527 | tNET | FF | 1 | R22C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s1/I0 |
12.121 | 0.577 | tINS | FR | 1 | R22C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s1/F |
12.121 | 0.000 | tNET | RR | 1 | R22C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_PAGE_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R22C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_PAGE_s0/CLK |
46.644 | -0.044 | tSu | 1 | R22C30[1][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FLASH_WR_PAGE_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.484, 45.710%; route: 2.660, 48.953%; tC2Q: 0.290, 5.337% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path16
Path Summary:
Slack | 34.560 |
Data Arrival Time | 12.084 |
Data Required Time | 46.644 |
From | led_cnt_16_s0 |
To | led_cnt_9_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[1][B] | led_cnt_16_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R30C36[1][B] | led_cnt_16_s0/Q |
7.711 | 0.733 | tNET | FF | 1 | R30C34[3][A] | n63_s3/I0 |
8.357 | 0.646 | tINS | FF | 1 | R30C34[3][A] | n63_s3/F |
8.666 | 0.309 | tNET | FF | 1 | R30C32[0][A] | n16_s2/I2 |
9.232 | 0.566 | tINS | FF | 1 | R30C32[0][A] | n16_s2/F |
9.936 | 0.704 | tNET | FF | 1 | R30C33[2][B] | n16_s0/I1 |
10.502 | 0.566 | tINS | FF | 10 | R30C33[2][B] | n16_s0/F |
11.371 | 0.869 | tNET | FF | 1 | R30C38[2][B] | n72_s2/I0 |
12.084 | 0.712 | tINS | FR | 1 | R30C38[2][B] | n72_s2/F |
12.084 | 0.000 | tNET | RR | 1 | R30C38[2][B] | led_cnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C38[2][B] | led_cnt_9_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C38[2][B] | led_cnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.491, 46.166%; route: 2.615, 48.460%; tC2Q: 0.290, 5.374% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path17
Path Summary:
Slack | 34.560 |
Data Arrival Time | 12.084 |
Data Required Time | 46.644 |
From | led_cnt_16_s0 |
To | led_cnt_12_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[1][B] | led_cnt_16_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R30C36[1][B] | led_cnt_16_s0/Q |
7.711 | 0.733 | tNET | FF | 1 | R30C34[3][A] | n63_s3/I0 |
8.357 | 0.646 | tINS | FF | 1 | R30C34[3][A] | n63_s3/F |
8.666 | 0.309 | tNET | FF | 1 | R30C32[0][A] | n16_s2/I2 |
9.232 | 0.566 | tINS | FF | 1 | R30C32[0][A] | n16_s2/F |
9.936 | 0.704 | tNET | FF | 1 | R30C33[2][B] | n16_s0/I1 |
10.502 | 0.566 | tINS | FF | 10 | R30C33[2][B] | n16_s0/F |
11.371 | 0.869 | tNET | FF | 1 | R30C38[1][A] | n69_s2/I2 |
12.084 | 0.712 | tINS | FR | 1 | R30C38[1][A] | n69_s2/F |
12.084 | 0.000 | tNET | RR | 1 | R30C38[1][A] | led_cnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C38[1][A] | led_cnt_12_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C38[1][A] | led_cnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.491, 46.166%; route: 2.615, 48.460%; tC2Q: 0.290, 5.374% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path18
Path Summary:
Slack | 34.570 |
Data Arrival Time | 12.074 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_CHK_OP_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.612 | 0.979 | tNET | FF | 1 | R21C30[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s5/I3 |
10.189 | 0.577 | tINS | FR | 2 | R21C30[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s5/F |
10.407 | 0.217 | tNET | RR | 1 | R21C29[3][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s2/I2 |
10.973 | 0.566 | tINS | RF | 2 | R21C29[3][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s2/F |
11.496 | 0.524 | tNET | FF | 1 | R18C29[0][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s1/I0 |
12.074 | 0.577 | tINS | FR | 1 | R18C29[0][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FSM_CHK_OP_s1/F |
12.074 | 0.000 | tNET | RR | 1 | R18C29[0][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_CHK_OP_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R18C29[0][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_CHK_OP_s0/CLK |
46.644 | -0.044 | tSu | 1 | R18C29[0][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.FSM_CHK_OP_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.367, 43.951%; route: 2.729, 50.665%; tC2Q: 0.290, 5.384% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path19
Path Summary:
Slack | 17.291 |
Data Arrival Time | 9.356 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_next_0_s1/I3 |
9.356 | 0.712 | tINS | FR | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_next_0_s1/F |
9.356 | 0.000 | tNET | RR | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.712, 26.696%; route: 1.666, 62.439%; tC2Q: 0.290, 10.866% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path20
Path Summary:
Slack | 17.291 |
Data Arrival Time | 9.356 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.644 | 1.666 | tNET | FF | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_next_1_s1/I3 |
9.356 | 0.712 | tINS | FR | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_next_1_s1/F |
9.356 | 0.000 | tNET | RR | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.712, 26.696%; route: 1.666, 62.439%; tC2Q: 0.290, 10.866% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path21
Path Summary:
Slack | 34.636 |
Data Arrival Time | 12.007 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.OP_RD_ID_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/CLK |
6.977 | 0.290 | tC2Q | RF | 5 | R23C38[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_op_rdy_reg_s4/Q |
7.987 | 1.009 | tNET | FF | 1 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/I3 |
8.633 | 0.646 | tINS | FF | 16 | R27C31[3][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s3/F |
9.521 | 0.888 | tNET | FF | 1 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/I1 |
10.087 | 0.566 | tINS | FF | 6 | R22C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.CHK_FLS_ST_s2/F |
10.322 | 0.235 | tNET | FF | 1 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/I2 |
11.016 | 0.694 | tINS | FF | 4 | R23C29[2][A] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.FLASH_WR_PAGE_s2/F |
11.544 | 0.527 | tNET | FF | 1 | R24C28[2][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.OP_RD_ID_s1/I0 |
12.007 | 0.464 | tINS | FF | 1 | R24C28[2][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_next.OP_RD_ID_s1/F |
12.007 | 0.000 | tNET | FF | 1 | R24C28[2][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.OP_RD_ID_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R24C28[2][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.OP_RD_ID_s0/CLK |
46.644 | -0.044 | tSu | 1 | R24C28[2][B] | inst_uart/inst_GW_UART/inst_ctrl/fsm_curr.OP_RD_ID_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.370, 44.549%; route: 2.660, 50.000%; tC2Q: 0.290, 5.451% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path22
Path Summary:
Slack | 34.643 |
Data Arrival Time | 12.001 |
Data Required Time | 46.644 |
From | led_cnt_0_s0 |
To | led_cnt_25_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[0][A] | led_cnt_0_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 6 | R30C36[0][A] | led_cnt_0_s0/Q |
7.822 | 0.845 | tNET | FF | 1 | R30C31[2][B] | n77_s3/I0 |
8.516 | 0.694 | tINS | FF | 7 | R30C31[2][B] | n77_s3/F |
9.039 | 0.522 | tNET | FF | 1 | R30C32[0][B] | n68_s3/I0 |
9.732 | 0.694 | tINS | FF | 9 | R30C32[0][B] | n68_s3/F |
10.083 | 0.351 | tNET | FF | 1 | R30C34[3][B] | n58_s3/I0 |
10.777 | 0.694 | tINS | FF | 6 | R30C34[3][B] | n58_s3/F |
11.288 | 0.512 | tNET | FF | 1 | R30C35[0][A] | n56_s2/I0 |
12.001 | 0.712 | tINS | FR | 1 | R30C35[0][A] | n56_s2/F |
12.001 | 0.000 | tNET | RR | 1 | R30C35[0][A] | led_cnt_25_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C35[0][A] | led_cnt_25_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C35[0][A] | led_cnt_25_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.794, 52.579%; route: 2.230, 41.963%; tC2Q: 0.290, 5.458% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path23
Path Summary:
Slack | 34.744 |
Data Arrival Time | 11.900 |
Data Required Time | 46.644 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_op_end_flag_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/CLK |
6.977 | 0.290 | tC2Q | RF | 4 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q |
7.814 | 0.837 | tNET | FF | 1 | R29C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n758_s4/I1 |
8.381 | 0.566 | tINS | FF | 8 | R29C38[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n758_s4/F |
8.713 | 0.333 | tNET | FF | 1 | R29C36[3][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s4/I1 |
9.407 | 0.694 | tINS | FF | 3 | R29C36[3][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n676_s4/F |
9.923 | 0.516 | tNET | FF | 1 | R27C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_data_rdy_reg_s4/I1 |
10.616 | 0.694 | tINS | FF | 1 | R27C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/next_data_rdy_reg_s4/F |
11.436 | 0.820 | tNET | FF | 1 | R24C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n655_s1/I0 |
11.900 | 0.464 | tINS | FF | 1 | R24C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n655_s1/F |
11.900 | 0.000 | tNET | FF | 1 | R24C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_op_end_flag_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R24C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_op_end_flag_s0/CLK |
46.644 | -0.044 | tSu | 1 | R24C37[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_op_end_flag_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.418, 46.378%; route: 2.505, 48.059%; tC2Q: 0.290, 5.563% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path24
Path Summary:
Slack | 34.771 |
Data Arrival Time | 11.873 |
Data Required Time | 46.644 |
From | led_cnt_0_s0 |
To | led_cnt_26_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[0][A] | led_cnt_0_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 6 | R30C36[0][A] | led_cnt_0_s0/Q |
7.822 | 0.845 | tNET | FF | 1 | R30C31[2][B] | n77_s3/I0 |
8.516 | 0.694 | tINS | FF | 7 | R30C31[2][B] | n77_s3/F |
9.039 | 0.522 | tNET | FF | 1 | R30C32[0][B] | n68_s3/I0 |
9.732 | 0.694 | tINS | FF | 9 | R30C32[0][B] | n68_s3/F |
10.394 | 0.661 | tNET | FF | 1 | R30C35[1][A] | n55_s3/I0 |
11.087 | 0.694 | tINS | FF | 3 | R30C35[1][A] | n55_s3/F |
11.409 | 0.322 | tNET | FF | 1 | R30C37[1][B] | n55_s2/I0 |
11.873 | 0.464 | tINS | FF | 1 | R30C37[1][B] | n55_s2/F |
11.873 | 0.000 | tNET | FF | 1 | R30C37[1][B] | led_cnt_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C37[1][B] | led_cnt_26_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C37[1][B] | led_cnt_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.545, 49.081%; route: 2.350, 45.326%; tC2Q: 0.290, 5.593% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Path25
Path Summary:
Slack | 34.778 |
Data Arrival Time | 11.866 |
Data Required Time | 46.644 |
From | led_cnt_0_s0 |
To | led_cnt_24_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R30C36[0][A] | led_cnt_0_s0/CLK |
6.977 | 0.290 | tC2Q | RF | 6 | R30C36[0][A] | led_cnt_0_s0/Q |
7.822 | 0.845 | tNET | FF | 1 | R30C31[2][B] | n77_s3/I0 |
8.516 | 0.694 | tINS | FF | 7 | R30C31[2][B] | n77_s3/F |
9.039 | 0.522 | tNET | FF | 1 | R30C32[0][B] | n68_s3/I0 |
9.732 | 0.694 | tINS | FF | 9 | R30C32[0][B] | n68_s3/F |
10.083 | 0.351 | tNET | FF | 1 | R30C34[3][B] | n58_s3/I0 |
10.777 | 0.694 | tINS | FF | 6 | R30C34[3][B] | n58_s3/F |
11.288 | 0.512 | tNET | FF | 1 | R30C35[0][B] | n57_s2/I0 |
11.866 | 0.577 | tINS | FR | 1 | R30C35[0][B] | n57_s2/F |
11.866 | 0.000 | tNET | RR | 1 | R30C35[0][B] | led_cnt_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
40.000 | 40.000 | active clock edge time | ||||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
44.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
46.687 | 2.622 | tNET | RR | 1 | R30C35[0][B] | led_cnt_24_s0/CLK |
46.644 | -0.044 | tSu | 1 | R30C35[0][B] | led_cnt_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 40.000 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 2.659, 51.343%; route: 2.230, 43.057%; tC2Q: 0.290, 5.600% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/n39_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/n39_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path2
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n251_s1/I2 |
6.353 | 0.290 | tINS | RF | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n251_s1/F |
6.353 | 0.000 | tNET | FF | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path3
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 4 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n764_s1/I1 |
6.353 | 0.290 | tINS | RF | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/n764_s1/F |
6.353 | 0.000 | tNET | FF | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1/CLK |
5.821 | 0.014 | tHld | 1 | R29C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/data_num_cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path4
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n857_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n857_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3/CLK |
5.821 | 0.014 | tHld | 1 | R25C32[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_3_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path5
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n856_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n856_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3/CLK |
5.821 | 0.014 | tHld | 1 | R25C31[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_4_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path6
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n852_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n852_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3/CLK |
5.821 | 0.014 | tHld | 1 | R25C31[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_8_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path7
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n851_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n851_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3/CLK |
5.821 | 0.014 | tHld | 1 | R21C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_9_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path8
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n850_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n850_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3/CLK |
5.821 | 0.014 | tHld | 1 | R18C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_10_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path9
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n848_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n848_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3/CLK |
5.821 | 0.014 | tHld | 1 | R22C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_12_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path10
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n846_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n846_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3/CLK |
5.821 | 0.014 | tHld | 1 | R18C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_14_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path11
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n845_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n845_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3/CLK |
5.821 | 0.014 | tHld | 1 | R20C28[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_15_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path12
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n844_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/n844_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3/CLK |
5.821 | 0.014 | tHld | 1 | R27C25[0][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_16_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path13
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4 |
To | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/Q |
6.063 | 0.003 | tNET | RR | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n837_s4/I1 |
6.353 | 0.290 | tINS | RF | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n837_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4/CLK |
5.821 | 0.014 | tHld | 1 | R22C28[1][A] | inst_uart/inst_GW_UART/inst_ctrl/flash_addr_reg_23_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path14
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1 |
To | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 3 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n635_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/n635_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1/CLK |
5.821 | 0.014 | tHld | 1 | R25C29[1][A] | inst_uart/inst_GW_UART/inst_ctrl/wait_ms_cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path15
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 4 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n146_s3/I1 |
6.353 | 0.290 | tINS | RF | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n146_s3/F |
6.353 | 0.000 | tNET | FF | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1/CLK |
5.821 | 0.014 | tHld | 1 | R29C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path16
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n144_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n144_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C18[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/cnt_n_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path17
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 6 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n102_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n102_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0/CLK |
5.821 | 0.014 | tHld | 1 | R27C19[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path18
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 3 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n90_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/n90_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C20[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path19
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/CLK |
6.060 | 0.252 | tC2Q | RR | 5 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/Q |
6.063 | 0.003 | tNET | RR | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n227_s6/I3 |
6.353 | 0.290 | tINS | RF | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n227_s6/F |
6.353 | 0.000 | tNET | FF | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3/CLK |
5.821 | 0.014 | tHld | 1 | R20C23[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path20
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 3 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n225_s4/I0 |
6.353 | 0.290 | tINS | RF | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n225_s4/F |
6.353 | 0.000 | tNET | FF | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1/CLK |
5.821 | 0.014 | tHld | 1 | R20C23[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path21
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/Q |
6.063 | 0.003 | tNET | RR | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n224_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n224_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1/CLK |
5.821 | 0.014 | tHld | 1 | R20C25[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/cnt_n_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path22
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 4 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n117_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n117_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0/CLK |
5.821 | 0.014 | tHld | 1 | R18C24[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path23
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 5 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n105_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n105_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0/CLK |
5.821 | 0.014 | tHld | 1 | R18C27[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path24
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 3 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/CLK |
5.821 | 0.014 | tHld | 1 | R18C26[1][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path25
Path Summary:
Slack | 0.532 |
Data Arrival Time | 6.353 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0 |
To | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/CLK |
6.060 | 0.252 | tC2Q | RR | 2 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/Q |
6.063 | 0.003 | tNET | RR | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n100_s2/I2 |
6.353 | 0.290 | tINS | RF | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n100_s2/F |
6.353 | 0.000 | tNET | FF | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0/CLK |
5.821 | 0.014 | tHld | 1 | R18C26[0][A] | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.290, 53.157%; route: 0.003, 0.560%; tC2Q: 0.252, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg_s7 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C35[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg_s7/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg_s7/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg_s7 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path2
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_vld_reg_s5 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_vld_reg_s5/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_vld_reg_s5/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_vld_reg_s5 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path3
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_en_reg_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_en_reg_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_en_reg_s1/CLK |
26.647 | -0.044 | tSu | 1 | R25C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_en_reg_s1 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path4
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CLK |
26.647 | -0.044 | tSu | 1 | R25C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path5
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg_s1/CLK |
26.647 | -0.044 | tSu | 1 | R25C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg_s1 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path6
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_pos_reg_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_pos_reg_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_pos_reg_s1/CLK |
26.647 | -0.044 | tSu | 1 | R25C33[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_pos_reg_s1 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path7
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_7_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_7_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C36[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_7_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path8
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_reg_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_reg_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_rdy_reg_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path9
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C33[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C33[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C33[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path10
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C33[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path11
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_2_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C33[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C33[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_2_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C33[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_neg_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path12
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/gap_cnt_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R27C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/gap_cnt_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R27C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/gap_cnt_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R27C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/gap_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path13
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | IOR34[A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg1_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | IOR34[A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg1_s0/CLK |
26.647 | -0.044 | tSu | 1 | IOR34[A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_cs_n_reg1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path14
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C33[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_en_reg1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path15
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_mosi_reg_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | IOR33[B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_mosi_reg_s0/PRESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | IOR33[B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_mosi_reg_s0/CLK |
26.647 | -0.044 | tSu | 1 | IOR33[B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/spi_mosi_reg_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path16
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path17
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/fsm_curr_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path18
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path19
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R26C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R26C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R26C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_start_reg_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path20
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path21
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_end_reg_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path22
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_0_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_0_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path23
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_1_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C34[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_1_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path24
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_2_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R25C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R25C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_2_s0/CLK |
26.647 | -0.044 | tSu | 1 | R25C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_2_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Path25
Path Summary:
Slack | 18.314 |
Data Arrival Time | 8.333 |
Data Required Time | 26.647 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_3_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
6.687 | 2.622 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.977 | 0.290 | tC2Q | RF | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
8.333 | 1.356 | tNET | FF | 1 | R24C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
20.000 | 20.000 | active clock edge time | ||||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
24.066 | 4.066 | tCL | FF | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | 1 | R24C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_3_s0/CLK |
26.647 | -0.044 | tSu | 1 | R24C35[2][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_reg_3_s0 |
Path Statistics:
Clock Skew | 0.004 |
Setup Relationship | 20.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.622, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.356, 82.380%; tC2Q: 0.290, 17.620% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.625, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_en_s4 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C29[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_en_s4/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C29[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_en_s4/CLK |
5.821 | 0.014 | tHld | 1 | R26C29[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_en_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path2
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_0_s3 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R24C28[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R24C28[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_0_s3/CLK |
5.821 | 0.014 | tHld | 1 | R24C28[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path3
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_1_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R24C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_1_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R24C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_1_s1/CLK |
5.821 | 0.014 | tHld | 1 | R24C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_1_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path4
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_2_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R25C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_2_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_2_s1/CLK |
5.821 | 0.014 | tHld | 1 | R25C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_2_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path5
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_3_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C27[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_3_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C27[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_3_s1/CLK |
5.821 | 0.014 | tHld | 1 | R26C27[2][A] | inst_uart/inst_GW_UART/inst_ms/cnt_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path6
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_4_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_4_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_4_s1/CLK |
5.821 | 0.014 | tHld | 1 | R26C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_4_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path7
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_5_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_5_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_5_s1/CLK |
5.821 | 0.014 | tHld | 1 | R26C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_5_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path8
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1/CLK |
5.821 | 0.014 | tHld | 1 | R26C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path9
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path10
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_8_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_8_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_8_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_8_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path11
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_9_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R22C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_9_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_9_s1/CLK |
5.821 | 0.014 | tHld | 1 | R22C27[1][B] | inst_uart/inst_GW_UART/inst_ms/cnt_9_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path12
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_10_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R22C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_10_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_10_s1/CLK |
5.821 | 0.014 | tHld | 1 | R22C27[0][B] | inst_uart/inst_GW_UART/inst_ms/cnt_10_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path13
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_11_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R22C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_11_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R22C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_11_s1/CLK |
5.821 | 0.014 | tHld | 1 | R22C27[0][A] | inst_uart/inst_GW_UART/inst_ms/cnt_11_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path14
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_12_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R23C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_12_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R23C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_12_s1/CLK |
5.821 | 0.014 | tHld | 1 | R23C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_12_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path15
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_13_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_13_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_13_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C27[2][B] | inst_uart/inst_GW_UART/inst_ms/cnt_13_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path16
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1/CLK |
5.821 | 0.014 | tHld | 1 | R27C27[1][A] | inst_uart/inst_GW_UART/inst_ms/cnt_14_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path17
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ms/ms_flag_reg_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R25C28[0][B] | inst_uart/inst_GW_UART/inst_ms/ms_flag_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R25C28[0][B] | inst_uart/inst_GW_UART/inst_ms/ms_flag_reg_s0/CLK |
5.821 | 0.014 | tHld | 1 | R25C28[0][B] | inst_uart/inst_GW_UART/inst_ms/ms_flag_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path18
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_vld_reg_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C32[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_vld_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C32[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_vld_reg_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C32[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_vld_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path19
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_0_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C36[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path20
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_1_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C36[0][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/tx_done_sync_reg_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path21
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C36[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C36[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_0_s0/CLK |
5.821 | 0.014 | tHld | 1 | R27C36[2][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path22
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C36[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C36[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_1_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C36[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path23
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C35[1][A] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/clk_pos_cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path24
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_0_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R26C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_0_s0/CLK |
5.821 | 0.014 | tHld | 1 | R26C34[1][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Path25
Path Summary:
Slack | 1.156 |
Data Arrival Time | 6.977 |
Data Required Time | 5.821 |
From | inst_uart/inst_GW_UART/rstn_flag_s2 |
To | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_1_s0 |
Launch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | pll_25M/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/CLK |
6.060 | 0.252 | tC2Q | RR | 513 | R26C26[1][A] | inst_uart/inst_GW_UART/rstn_flag_s2/Q |
6.977 | 0.917 | tNET | RR | 1 | R27C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||||
4.066 | 4.066 | tCL | RR | 547 | PLL_R[0] | pll_25M/rpll_inst/CLKOUT |
5.807 | 1.742 | tNET | RR | 1 | R27C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_1_s0/CLK |
5.821 | 0.014 | tHld | 1 | R27C34[0][B] | inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_rx_reg_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.917, 78.412%; tC2Q: 0.252, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.742, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_30_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | led_cnt_30_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | led_cnt_30_s0/CLK |
MPW2
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_28_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | led_cnt_28_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | led_cnt_28_s0/CLK |
MPW3
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_24_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | led_cnt_24_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | led_cnt_24_s0/CLK |
MPW4
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | led_cnt_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | led_cnt_16_s0/CLK |
MPW5
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | led_cnt_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | led_cnt_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | led_cnt_0_s0/CLK |
MPW6
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | inst_uart/inst_GW_UART/rstn_cmd_data_5_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | inst_uart/inst_GW_UART/rstn_cmd_data_5_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | inst_uart/inst_GW_UART/rstn_cmd_data_5_s1/CLK |
MPW7
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_21_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_21_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/div_cnt_21_s0/CLK |
MPW8
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | inst_uart/inst_GW_UART/inst_uart_spi/idle_cnt_6_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | inst_uart/inst_GW_UART/inst_uart_spi/idle_cnt_6_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | inst_uart/inst_GW_UART/inst_uart_spi/idle_cnt_6_s1/CLK |
MPW9
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | inst_uart/inst_GW_UART/inst_ms/cnt_6_s1/CLK |
MPW10
MPW Summary:
Slack: | 17.866 |
Actual Width: | 19.116 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | pll_25M/rpll_inst/CLKOUT.default_gen_clk |
Objects: | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
24.066 | 4.066 | tCL | FF | pll_25M/rpll_inst/CLKOUT |
26.691 | 2.625 | tNET | FF | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
40.000 | 0.000 | active clock edge time | ||
40.000 | 0.000 | pll_25M/rpll_inst/CLKOUT.default_gen_clk | ||
44.066 | 4.066 | tCL | RR | pll_25M/rpll_inst/CLKOUT |
45.807 | 1.742 | tNET | RR | inst_uart/inst_GW_UART/inst_ms/cnt_7_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
547 | clk_25M | 17.291 | 2.836 |
513 | rstn_flag | 17.291 | 1.864 |
40 | fsm_curr.FSM_OP_END | 36.970 | 0.913 |
32 | rstn_cmd_data_31_10 | 35.329 | 0.872 |
30 | fsm_curr.FSM_CHK_OP | 35.336 | 1.110 |
29 | rstn_cnt_2_10 | 35.693 | 0.878 |
29 | rstn_cnt_2_11 | 35.329 | 0.607 |
24 | n123_10 | 37.174 | 0.872 |
24 | n949_8 | 37.098 | 1.217 |
24 | F_erase_reg_0 | 35.461 | 1.184 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R22C32 | 86.11% |
R20C22 | 81.94% |
R26C33 | 81.94% |
R20C28 | 80.56% |
R18C28 | 80.56% |
R25C31 | 80.56% |
R27C33 | 79.17% |
R22C26 | 79.17% |
R26C35 | 79.17% |
R25C34 | 79.17% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
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