PnR Messages

Report Title PnR Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18MG196C7/I6
Device GW2A-18
Created Time Tue Dec 17 17:27:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.085s, Elapsed time = 0h 0m 0.085s Placement Phase 1: CPU time = 0h 0m 0.255s, Elapsed time = 0h 0m 0.255s Placement Phase 2: CPU time = 0h 0m 0.144s, Elapsed time = 0h 0m 0.144s Placement Phase 3: CPU time = 0h 0m 0.928s, Elapsed time = 0h 0m 0.929s Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.264s, Elapsed time = 0h 0m 0.264s Routing Phase 2: CPU time = 0h 0m 0.588s, Elapsed time = 0h 0m 0.588s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.853s, Elapsed time = 0h 0m 0.853s Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 460MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 834/20736 5%
    --LUT,ALU,ROM16 834(834 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 546/15894 4%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 543/15552 4%
    --I/O Register as Latch 0/342 0%
    --I/O Register as FF 3/342 <1%
CLS 570/10368 6%
I/O Port 12/114 11%
I/O Buf 12 -
    --Input Buf 4 -
    --Output Buf 8 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/120%
bank 1 0/140%
bank 2 1/167%
bank 3 7/2528%
bank 4 0/130%
bank 5 0/80%
bank 6 4/1234%
bank 7 0/140%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 1/8 13%
GCLK_PIN 1/8 13%
rPLL 1/4 25%

Global Clock Signals:

Signal Global Clock Location
clk_25M PRIMARY TR TL BR BL
inst_uart/inst_GW_UART/rstn_flag LW -
clk_in_d HCLK TOP[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
uart_rx - M1/6 Y in IOL47[B] LPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
spi_miso - N11/3 Y in IOR33[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
clk_in - F13/2 Y in IOR27[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.2
rstn - P9/3 N in IOR35[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
uart_tx - M2/6 Y out IOL47[A] LPLL2_T_fb LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
spi_sclk - N13/3 Y out IOR34[B] MCLK/D4 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
spi_cs_n - P2/3 Y out IOR34[A] MCS_N/D5 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
spi_mosi - P11/3 Y out IOR33[B] MO/D6 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
reconfig_n - N1/3 Y out IOR31[B] RECONFIG_N LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
uart_rx_test - K1/6 Y out IOL35[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
uart_tx_test - K2/6 Y out IOL35[A] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
test - J12/3 N out IOR40[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
B2/0 - in IOT16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A2/0 - in IOT16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B3/0 - in IOT18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A3/0 - in IOT18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B4/0 - in IOT21[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A4/0 - in IOT21[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B5/0 - in IOT22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A5/0 - in IOT22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B6/0 - in IOT24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A6/0 - in IOT24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B7/0 - in IOT27[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A7/0 - in IOT27[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D8/1 - in IOT30[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/1 - in IOT30[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B8/1 - in IOT32[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A8/1 - in IOT32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B9/1 - in IOT34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A9/1 - in IOT34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B10/1 - in IOT37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A10/1 - in IOT37[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B11/1 - in IOT38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A11/1 - in IOT38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B12/1 - in IOT40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A12/1 - in IOT40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D11/1 - in IOT42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C11/1 - in IOT42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N12/5 - in IOB16[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P12/5 - in IOB16[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N10/5 - in IOB20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P10/5 - in IOB20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L8/5 - in IOB24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M8/5 - in IOB24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N8/5 - in IOB27[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P8/5 - in IOB27[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N7/4 - in IOB30[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P7/4 - in IOB30[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N6/4 - in IOB34[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P6/4 - in IOB34[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N5/4 - in IOB37[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P5/4 - in IOB37[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L4/4 - in IOB38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M4/4 - in IOB38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N4/4 - in IOB40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P4/4 - in IOB40[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N3/4 - in IOB43[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P3/4 - in IOB43[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M12/4 - in IOB48[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D2/7 - in IOL7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D1/7 - in IOL7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C1/7 - in IOL15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B1/7 - in IOL15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D4/7 - in IOL20[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D3/7 - in IOL20[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E2/7 - in IOL22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E1/7 - in IOL22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F4/7 - in IOL24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F3/7 - in IOL24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F2/7 - in IOL26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F1/7 - in IOL26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H2/7 - in IOL27[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H1/7 - in IOL27[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G2/6 - in IOL29[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G1/6 - in IOL29[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J2/6 - in IOL31[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J1/6 - in IOL31[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J4/6 - in IOL33[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J3/6 - in IOL33[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K2/6 uart_tx_test out IOL35[A] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
K1/6 uart_rx_test out IOL35[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
L2/6 - in IOL45[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L1/6 - in IOL45[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M2/6 uart_tx out IOL47[A] LPLL2_T_fb LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
M1/6 uart_rx in IOL47[B] LPLL2_C_fb LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
D13/2 - in IOR7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
D14/2 - in IOR7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C12/2 - in IOR13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C13/2 - in IOR13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
E13/2 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
E14/2 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F11/2 - in IOR22[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F12/2 - in IOR22[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
G13/2 - in IOR24[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
G14/2 - in IOR24[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
C14/2 - out IOR25[A] - LVCMOS18 8 UP NA NA OFF NA NA NA 1.2
B14/2 - in IOR25[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B13/2 - in IOR26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A13/2 - in IOR26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F13/2 clk_in in IOR27[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.2
F14/2 - in IOR27[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
H13/3 - in IOR29[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H14/3 - in IOR29[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N9/3 - in IOR30[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
P13/3 - in IOR30[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N1/3 reconfig_n out IOR31[B] RECONFIG_N LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
N2/3 - in IOR32[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N14/3 - in IOR32[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
N11/3 spi_miso in IOR33[A] MI/D7 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
P11/3 spi_mosi out IOR33[B] MO/D6 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
P2/3 spi_cs_n out IOR34[A] MCS_N/D5 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
N13/3 spi_sclk out IOR34[B] MCLK/D4 LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
P9/3 rstn in IOR35[A] FASTRD_N/D3 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
L12/3 - in IOR35[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H11/3 - in IOR36[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H12/3 - in IOR36[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J13/3 - in IOR38[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J14/3 - in IOR38[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J11/3 - in IOR40[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
J12/3 test out IOR40[B] - LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
K13/3 - in IOR42[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
K14/3 - in IOR42[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L13/3 - in IOR44[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
L14/3 - in IOR44[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M13/3 - in IOR45[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
M14/3 - in IOR45[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8