Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\GOCONFIGUART\data\goConfig_UART.v
D:\Gowin\Gowin_V1.9.11_x64\IDE\ipcore\GOCONFIGUART\data\goConfig_UART_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18MG196C7/I6
Device GW2A-18
Created Time Tue Dec 17 17:27:22 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module goConfig_UART_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 69.855MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 69.855MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 69.855MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 69.855MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 69.855MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 69.855MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 69.855MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 69.855MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 69.855MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 69.855MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 69.855MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 69.855MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 100.441MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.185s, Peak memory usage = 100.441MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 100.441MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 100.441MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 9
I/O Buf 9
    IBUF 4
    OBUF 5
Register 513
    DFFS 1
    DFFP 6
    DFFPE 15
    DFFC 226
    DFFCE 265
LUT 768
    LUT2 121
    LUT3 195
    LUT4 452
INV 6
    INV 6

Resource Utilization Summary

Resource Usage Utilization
Logic 774(774 LUT, 0 ALU) / 20736 4%
Register 513 / 15894 4%
  --Register as Latch 0 / 15894 0%
  --Register as FF 513 / 15894 4%
BSRAM 0 / 46 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 GW_OSC_CLK Base 10.000 100.0 0.000 5.000 GW_OSC_CLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 GW_OSC_CLK 100.000(MHz) 163.934(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.950
Data Arrival Time 3.599
Data Required Time 5.549
From inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0
To inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1
Launch Clk GW_OSC_CLK[F]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
0.450 0.450 tNET RR 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0/CLK
0.740 0.290 tC2Q RF 2 inst_GW_UART/inst_ctrl/inst_spi_cmd/spi_tx_start_reg_s0/Q
1.332 0.593 tNET FF 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n264_s2/I0
1.979 0.646 tINS FF 2 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/n264_s2/F
2.571 0.593 tNET FF 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s3/I2
3.149 0.577 tINS FR 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s3/F
3.599 0.450 tNET RR 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 GW_OSC_CLK
5.000 0.000 tCL FF 1 GW_OSC_CLK_ibuf/I
5.000 0.000 tINS FF 514 GW_OSC_CLK_ibuf/O
5.593 0.593 tNET FF 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1/CLK
5.549 -0.044 tSu 1 inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/data_tx_done_reg_s1
Path Statistics:
Clock Skew: 0.143
Setup Relationship: 5.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 1.224, 38.865%; route: 1.635, 51.925%; tC2Q: 0.290, 9.210%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 2

Path Summary:
Slack 3.929
Data Arrival Time 6.477
Data Required Time 10.406
From inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
0.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
0.740 0.290 tC2Q RF 5 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.332 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.026 0.694 tINS FF 6 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
2.619 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.312 0.694 tINS FF 8 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
3.905 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/I1
4.599 0.694 tINS FF 3 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/F
5.191 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/I1
5.885 0.694 tINS FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n101_s2/F
6.478 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 GW_OSC_CLK
10.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
10.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
10.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0/CLK
10.406 -0.044 tSu 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 3

Path Summary:
Slack 3.929
Data Arrival Time 6.477
Data Required Time 10.406
From inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
0.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
0.740 0.290 tC2Q RF 5 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.332 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.026 0.694 tINS FF 6 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
2.619 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.312 0.694 tINS FF 8 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
3.905 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/I1
4.599 0.694 tINS FF 3 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s3/F
5.191 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s2/I1
5.885 0.694 tINS FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n102_s2/F
6.478 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 GW_OSC_CLK
10.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
10.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
10.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0/CLK
10.406 -0.044 tSu 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 4

Path Summary:
Slack 3.929
Data Arrival Time 6.477
Data Required Time 10.406
From inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
0.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
0.740 0.290 tC2Q RF 5 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.332 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.026 0.694 tINS FF 6 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
2.619 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.312 0.694 tINS FF 8 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
3.905 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/I1
4.599 0.694 tINS FF 2 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/F
5.191 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n106_s2/I1
5.885 0.694 tINS FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n106_s2/F
6.478 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 GW_OSC_CLK
10.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
10.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
10.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0/CLK
10.406 -0.044 tSu 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_17_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%

Path 5

Path Summary:
Slack 3.929
Data Arrival Time 6.477
Data Required Time 10.406
From inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0
To inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
0.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/CLK
0.740 0.290 tC2Q RF 5 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_1_s0/Q
1.332 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/I1
2.026 0.694 tINS FF 6 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n119_s3/F
2.619 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/I1
3.312 0.694 tINS FF 8 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n110_s3/F
3.905 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/I1
4.599 0.694 tINS FF 2 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s4/F
5.191 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s2/I1
5.885 0.694 tINS FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/n107_s2/F
6.478 0.593 tNET FF 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 GW_OSC_CLK
10.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
10.000 0.000 tINS RR 514 GW_OSC_CLK_ibuf/O
10.450 0.450 tNET RR 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0/CLK
10.406 -0.044 tSu 1 inst_GW_UART/uart_slave_inst/u_uart_slave_rx/div_cnt_16_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%
Arrival Data Path Delay: cell: 2.775, 46.039%; route: 2.963, 49.150%; tC2Q: 0.290, 4.811%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.450, 100.000%