Power Messages

Report Title Power Analysis Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2024\uart_spi\pro\12-11\ref_design\fpga_project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.11 (64-bit)
Part Number GW2A-LV18MG196C7/I6
Device GW2A-18
Created Time Tue Dec 17 17:27:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 111.716
Quiescent Power (mW) 107.150
Dynamic Power (mW) 4.567

Thermal Information:

Junction Temperature 28.875
Theta JA 34.690
Max Allowed Ambient Temperature 81.125

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 3.189 55.991 59.180
VCCX 3.300 0.289 15.000 50.453
VCCIO12 1.200 0.158 0.083 0.289
VCCIO18 1.800 0.131 0.866 1.794

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 0.278 NA 3.125
IO 5.125 3.458 6.771
PLL 2.615 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 2.893 2.893(2.873)
top/inst_uart/ 0.258 0.258(0.258)
top/inst_uart/inst_GW_UART/ 0.258 0.258(0.242)
top/inst_uart/inst_GW_UART/inst_ctrl/ 0.129 0.129(0.078)
top/inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/ 0.078 0.078(0.015)
top/inst_uart/inst_GW_UART/inst_ctrl/inst_spi_cmd/inst_spi_master/ 0.015 0.015(0.000)
top/inst_uart/inst_GW_UART/inst_ms/ 0.010 0.010(0.000)
top/inst_uart/inst_GW_UART/inst_uart_spi/ 0.053 0.053(0.000)
top/inst_uart/inst_GW_UART/uart_slave_inst/ 0.051 0.051(0.051)
top/inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_rx/ 0.025 0.025(0.000)
top/inst_uart/inst_GW_UART/uart_slave_inst/u_uart_slave_tx/ 0.026 0.026(0.000)
top/pll_25M/ 2.615 2.615(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
pll_25M/rpll_inst/CLKOUT.default_gen_clk 25.000 0.285
clk_in 50.000 2.615