Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_interface.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_rdfifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_wrfifo.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Sun Aug 20 15:09:46 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module RiscV_AE350_SOC_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 3s, Peak memory usage = 80.520MB
Running netlist conversion:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 80.520MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.438s, Peak memory usage = 80.520MB
    Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 80.520MB
    Optimizing Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.422s, Peak memory usage = 80.520MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.182s, Peak memory usage = 80.520MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 80.520MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 80.520MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 80.520MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.491s, Peak memory usage = 80.520MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.249s, Peak memory usage = 80.520MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 80.520MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 80.520MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 80.520MB
Generate output files:
    CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 1s, Peak memory usage = 85.938MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 9s, Peak memory usage = 85.938MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 212
I/O Buf 209
    IBUF 71
    OBUF 111
    TBUF 2
    IOBUF 22
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 3422
    DFFSE 1
    DFFRE 678
    DFFPE 82
    DFFCE 2660
    DLCE 1
LUT 2877
    LUT2 711
    LUT3 1236
    LUT4 930
ALU 254
    ALU 254
SSRAM 64
    RAM16SDP4 64
INV 100
    INV 100
IOLOGIC 75
    IDES8_MEM 16
    OSER8 23
    OSER8_MEM 20
    IODELAY 16
BSRAM 22
    SDPB 14
    SDPX9B 8
CLOCK 4
    CLKDIV 1
    DQS 2
    DDRDLL 1
AE350_SOC 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3615(2977 LUT, 254 ALU, 64 RAM16) / 138240 3%
Register 3422 / 139140 3%
  --Register as Latch 1 / 139140 <1%
  --Register as FF 3421 / 139140 3%
BSRAM 22 / 340 7%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
DDR3_CLK_IN Base 10.000 100.0 0.000 5.000 DDR3_CLK_IN_ibuf/I
DDR3_MEMORY_CLK Base 10.000 100.0 0.000 5.000 DDR3_MEMORY_CLK_ibuf/I
DDR_CLK Base 10.000 100.0 0.000 5.000 DDR_CLK_ibuf/I
AHB_CLK Base 10.000 100.0 0.000 5.000 AHB_CLK_ibuf/I
FLASH_SPI_CLK_iobuf/I Base 10.000 100.0 0.000 5.000 FLASH_SPI_CLK_iobuf/I
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_s2/O
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_9 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_s6/O
FLASH_SPI_CLK_in Base 10.000 100.0 0.000 5.000 FLASH_SPI_CLK_iobuf/O
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 DDR3_MEMORY_CLK_ibuf/I DDR3_MEMORY_CLK u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 DDR3_CLK_IN 100.0(MHz) 265.1(MHz) 6 TOP
2 DDR3_MEMORY_CLK 100.0(MHz) 1506.0(MHz) 1 TOP
3 DDR_CLK 100.0(MHz) 235.8(MHz) 7 TOP
4 AHB_CLK 100.0(MHz) 122.5(MHz) 13 TOP
5 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 100.0(MHz) 1643.7(MHz) 1 TOP
6 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 100.0(MHz) 1643.7(MHz) 1 TOP
7 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 100.0(MHz) 1643.7(MHz) 1 TOP
8 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 100.0(MHz) 1643.7(MHz) 1 TOP
9 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 100.0(MHz) 1643.7(MHz) 1 TOP
10 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 100.0(MHz) 1643.7(MHz) 1 TOP
11 u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk 25.0(MHz) 148.5(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.834
Data Arrival Time 8.967
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK
1.230 0.367 tC2Q RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/I0
1.915 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/I0
2.600 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I1
3.951 0.496 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F
4.131 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1
4.627 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F
4.807 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1
5.303 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F
5.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/I2
5.925 0.443 tINS RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/F
6.105 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1
6.645 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
6.645 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
6.693 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
6.693 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
6.741 0.048 tINS RR 17 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
6.921 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s3/I1
7.417 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s3/F
7.597 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s1/I0
8.102 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s1/F
8.282 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s0/I0
8.787 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s0/F
8.967 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.578, 68.818%; route: 2.160, 26.651%; tC2Q: 0.367, 4.531%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 2.357
Data Arrival Time 8.444
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/CLK
1.230 0.367 tC2Q RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s12/I0
1.915 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s12/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/period_cnt_r_7_s4/I0
2.600 0.505 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/period_cnt_r_7_s4/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_3_s8/I0
3.285 0.505 tINS RR 6 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_3_s8/F
3.465 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s8/I1
3.961 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s4/I0
4.646 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s4/F
4.826 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s3/I0
5.331 0.505 tINS RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s3/F
5.511 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/I2
5.954 0.443 tINS RR 7 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s3/F
6.134 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_0_s3/I0
6.639 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_0_s3/F
6.819 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s0/I0
7.353 0.534 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s0/COUT
7.353 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/CIN
7.401 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/COUT
7.401 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/CIN
7.449 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/COUT
7.449 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_3_s0/CIN
7.497 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_3_s0/COUT
7.497 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_4_s0/CIN
7.545 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_4_s0/COUT
7.545 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_5_s0/CIN
7.593 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_5_s0/COUT
7.593 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/CIN
7.641 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/COUT
7.821 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/I2
8.264 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/F
8.444 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.234, 69.041%; route: 1.980, 26.116%; tC2Q: 0.367, 4.843%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 2.397
Data Arrival Time 8.167
Data Required Time 10.564
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK
1.230 0.367 tC2Q RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/I0
1.915 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/I0
2.600 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I1
3.951 0.496 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F
4.131 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1
4.627 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F
4.807 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1
5.303 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F
5.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/I2
5.925 0.443 tINS RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/F
6.105 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1
6.645 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
6.645 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
6.693 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
6.693 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
6.741 0.048 tINS RR 17 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
6.921 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s4/I2
7.364 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s4/F
7.544 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s3/I2
7.987 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s3/F
8.167 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK
10.564 -0.299 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 4.957, 67.866%; route: 1.980, 27.107%; tC2Q: 0.367, 5.027%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 2.582
Data Arrival Time 8.220
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK
1.230 0.367 tC2Q RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/I0
1.915 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/I0
2.600 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I1
3.951 0.496 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F
4.131 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1
4.627 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F
4.807 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1
5.303 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F
5.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/I2
5.925 0.443 tINS RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/F
6.105 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1
6.645 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
6.645 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
6.693 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
6.693 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
6.741 0.048 tINS RR 17 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
6.921 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I1
7.417 0.496 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
7.597 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/I2
8.040 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/F
8.220 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.010, 68.097%; route: 1.980, 26.912%; tC2Q: 0.367, 4.991%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 2.582
Data Arrival Time 8.220
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK
1.230 0.367 tC2Q RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/I0
1.915 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/I0
2.600 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s8/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I1
3.951 0.496 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F
4.131 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1
4.627 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F
4.807 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1
5.303 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F
5.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/I2
5.925 0.443 tINS RR 5 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s23/F
6.105 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1
6.645 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
6.645 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
6.693 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
6.693 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
6.741 0.048 tINS RR 17 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
6.921 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I1
7.417 0.496 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
7.597 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n501_s2/I2
8.040 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n501_s2/F
8.220 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.010, 68.097%; route: 1.980, 26.912%; tC2Q: 0.367, 4.991%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%