Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_interface.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_rdfifo.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_wrfifo.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Fri Aug 18 15:48:30 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RiscV_AE350_SOC_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 80.727MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 80.727MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.283s, Peak memory usage = 80.727MB Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 80.727MB Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.314s, Peak memory usage = 80.727MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.11s, Peak memory usage = 80.727MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 80.727MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 80.727MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 80.727MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 80.727MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.218s, Peak memory usage = 80.727MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.094s, Peak memory usage = 80.727MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 80.844MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.31s, Peak memory usage = 80.844MB Generate output files: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.467s, Peak memory usage = 86.328MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 7s, Peak memory usage = 86.328MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 112 |
| I/O Buf | 109 |
| IBUF | 18 |
| OBUF | 32 |
| TBUF | 2 |
| IOBUF | 54 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 3422 |
| DFFSE | 1 |
| DFFRE | 678 |
| DFFPE | 82 |
| DFFCE | 2660 |
| DLCE | 1 |
| LUT | 2901 |
| LUT2 | 704 |
| LUT3 | 1241 |
| LUT4 | 956 |
| ALU | 254 |
| ALU | 254 |
| SSRAM | 64 |
| RAM16SDP4 | 64 |
| INV | 164 |
| INV | 164 |
| IOLOGIC | 75 |
| IDES8_MEM | 16 |
| OSER8 | 23 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| BSRAM | 22 |
| SDPB | 14 |
| SDPX9B | 8 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DDRDLL | 1 |
| AE350_SOC | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3703(3065 LUT, 254 ALU, 64 RAM16) / 138240 | 3% |
| Register | 3422 / 139140 | 3% |
| --Register as Latch | 1 / 139140 | <1% |
| --Register as FF | 3421 / 139140 | 3% |
| BSRAM | 22 / 340 | 7% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| DDR3_CLK_IN | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
| DDR3_MEMORY_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
| DDR_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
| AHB_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
| FLASH_SPI_CLK_iobuf/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/I | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_s2/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_9 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_s6/O | ||
| FLASH_SPI_CLK_in | Base | 10.000 | 100.0 | 0.000 | 5.000 | FLASH_SPI_CLK_iobuf/O | ||
| u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | DDR3_CLK_IN | 100.0(MHz) | 265.1(MHz) | 6 | TOP |
| 2 | DDR3_MEMORY_CLK | 100.0(MHz) | 1506.0(MHz) | 1 | TOP |
| 3 | DDR_CLK | 100.0(MHz) | 235.8(MHz) | 7 | TOP |
| 4 | AHB_CLK | 100.0(MHz) | 122.3(MHz) | 13 | TOP |
| 5 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 7 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 8 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 9 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 10 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
| 11 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 148.5(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.824 |
| Data Arrival Time | 8.977 |
| Data Required Time | 10.801 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q |
| 1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/I0 |
| 1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/F |
| 2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/I0 |
| 2.600 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/F |
| 2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1 |
| 3.276 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F |
| 3.456 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
| 3.961 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
| 4.141 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1 |
| 4.637 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F |
| 4.817 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1 |
| 5.312 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F |
| 5.492 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/I2 |
| 5.935 | 0.443 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/F |
| 6.115 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1 |
| 6.655 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 6.655 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 6.703 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 6.703 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 6.751 | 0.048 | tINS | RR | 14 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 6.931 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s3/I1 |
| 7.426 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s3/F |
| 7.606 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s1/I0 |
| 8.112 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s1/F |
| 8.292 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s0/I0 |
| 8.797 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n678_s0/F |
| 8.977 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1/CLK |
| 10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.587, 68.856%; route: 2.160, 26.619%; tC2Q: 0.367, 4.525% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 2.387 |
| Data Arrival Time | 8.176 |
| Data Required Time | 10.564 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q |
| 1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/I0 |
| 1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/F |
| 2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/I0 |
| 2.600 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/F |
| 2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1 |
| 3.276 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F |
| 3.456 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
| 3.961 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
| 4.141 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1 |
| 4.637 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F |
| 4.817 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1 |
| 5.312 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F |
| 5.492 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/I2 |
| 5.935 | 0.443 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/F |
| 6.115 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1 |
| 6.655 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 6.655 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 6.703 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 6.703 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 6.751 | 0.048 | tINS | RR | 14 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 6.931 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s4/I2 |
| 7.374 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s4/F |
| 7.554 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s3/I2 |
| 7.996 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s3/F |
| 8.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1/CLK |
| 10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_req_invalid_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 4.967, 67.908%; route: 1.980, 27.071%; tC2Q: 0.367, 5.021% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 2.409 |
| Data Arrival Time | 8.392 |
| Data Required Time | 10.801 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_0_s1/Q |
| 1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s12/I0 |
| 1.915 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_1_s12/F |
| 2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/period_cnt_r_7_s5/I0 |
| 2.600 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/period_cnt_r_7_s5/F |
| 2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_3_s8/I0 |
| 3.285 | 0.505 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/clock_cnt_r_3_s8/F |
| 3.465 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s10/I1 |
| 3.961 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s10/F |
| 4.141 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s5/I0 |
| 4.646 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s5/F |
| 4.826 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s4/I2 |
| 5.269 | 0.443 | tINS | RR | 6 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s4/F |
| 5.449 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s3/I0 |
| 5.954 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s3/F |
| 6.134 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_2_s3/I1 |
| 6.630 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_bin_rd_ptr_2_s3/F |
| 6.810 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/I1 |
| 7.350 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_1_s0/COUT |
| 7.350 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/CIN |
| 7.398 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/COUT |
| 7.398 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_3_s0/CIN |
| 7.446 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_3_s0/COUT |
| 7.446 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_4_s0/CIN |
| 7.494 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_4_s0/COUT |
| 7.494 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_5_s0/CIN |
| 7.542 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_5_s0/COUT |
| 7.542 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/CIN |
| 7.590 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_6_s0/COUT |
| 7.770 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/I2 |
| 8.212 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n465_s1/F |
| 8.392 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/CLK |
| 10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.183, 68.829%; route: 1.980, 26.295%; tC2Q: 0.367, 4.876% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 2.572 |
| Data Arrival Time | 8.229 |
| Data Required Time | 10.801 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q |
| 1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/I0 |
| 1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/F |
| 2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/I0 |
| 2.600 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/F |
| 2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1 |
| 3.276 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F |
| 3.456 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
| 3.961 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
| 4.141 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1 |
| 4.637 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F |
| 4.817 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1 |
| 5.312 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F |
| 5.492 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/I2 |
| 5.935 | 0.443 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/F |
| 6.115 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1 |
| 6.655 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 6.655 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 6.703 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 6.703 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 6.751 | 0.048 | tINS | RR | 14 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 6.931 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I1 |
| 7.426 | 0.496 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 7.606 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/I2 |
| 8.049 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/F |
| 8.229 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK |
| 10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.020, 68.138%; route: 1.980, 26.877%; tC2Q: 0.367, 4.985% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 2.572 |
| Data Arrival Time | 8.229 |
| Data Required Time | 10.801 |
| From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1 |
| To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Launch Clk | AHB_CLK[R] |
| Latch Clk | AHB_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/CLK |
| 1.230 | 0.367 | tC2Q | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_bit_cnt_r_4_s1/Q |
| 1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/I0 |
| 1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s15/F |
| 2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/I0 |
| 2.600 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/tx_ready_s10/F |
| 2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/I1 |
| 3.276 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s6/F |
| 3.456 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/I0 |
| 3.961 | 0.505 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_3_s3/F |
| 4.141 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/I1 |
| 4.637 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s8/F |
| 4.817 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/I1 |
| 5.312 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s4/F |
| 5.492 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/I2 |
| 5.935 | 0.443 | tINS | RR | 5 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_1_s24/F |
| 6.115 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/I1 |
| 6.655 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
| 6.655 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
| 6.703 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
| 6.703 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
| 6.751 | 0.048 | tINS | RR | 14 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
| 6.931 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I1 |
| 7.426 | 0.496 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F |
| 7.606 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n501_s2/I2 |
| 8.049 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n501_s2/F |
| 8.229 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 290 | AHB_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK |
| 10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.020, 68.138%; route: 1.980, 26.877%; tC2Q: 0.367, 4.985% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |