Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_interface.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_rdfifo.v
D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_wrfifo.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-3
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Sun Aug 20 15:48:14 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module RiscV_AE350_SOC_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.975s, Peak memory usage = 58.043MB
Running netlist conversion:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 58.043MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 58.043MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 58.043MB
    Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 58.043MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 58.043MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 58.043MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 58.043MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 58.043MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 58.043MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 58.043MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 58.043MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 62.762MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 62.762MB
Generate output files:
    CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 62.762MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 62.762MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 237
I/O Buf 237
    IBUF 81
    OBUF 118
    IOBUF 38
Register 226
    DFFRE 1
    DFFPE 5
    DFFCE 219
    DLCE 1
LUT 691
    LUT2 182
    LUT3 277
    LUT4 232
ALU 61
    ALU 61
SSRAM 64
    RAM16SDP4 64
INV 96
    INV 96
AE350_SOC 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1232(787 LUT, 61 ALU, 64 RAM16) / 138240 <1%
Register 226 / 139140 <1%
  --Register as Latch 1 / 139140 <1%
  --Register as FF 225 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
AHB_CLK Base 10.000 100.0 0.000 5.000 AHB_CLK_ibuf/I
FLASH_SPI_CLK_iobuf/I Base 10.000 100.0 0.000 5.000 FLASH_SPI_CLK_iobuf/I
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_9 Base 10.000 100.0 0.000 5.000 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_clock_inv_s6/O
FLASH_SPI_CLK_in Base 10.000 100.0 0.000 5.000 FLASH_SPI_CLK_iobuf/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 AHB_CLK 100.0(MHz) 118.0(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.526
Data Arrival Time 9.276
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK
1.230 0.367 tC2Q RR 25 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/I0
1.915 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/I0
2.600 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I0
3.961 0.505 tINS RR 13 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I1
4.637 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F
4.817 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I0
5.322 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F
5.502 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/I0
6.007 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/F
6.187 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I3
6.439 0.252 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F
6.619 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1
7.159 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT
7.159 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN
7.207 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
7.207 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
7.255 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
7.255 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
7.303 0.048 tINS RR 14 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
7.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I0
7.988 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
8.168 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/I3
8.420 0.252 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/F
8.600 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/I1
9.096 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/F
9.276 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.706, 67.822%; route: 2.340, 27.813%; tC2Q: 0.367, 4.365%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 1.578
Data Arrival Time 9.223
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK
1.230 0.367 tC2Q RR 25 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/I0
1.915 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/I0
2.600 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I0
3.961 0.505 tINS RR 13 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I1
4.637 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F
4.817 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I0
5.322 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F
5.502 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/I0
6.007 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/F
6.187 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I3
6.439 0.252 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F
6.619 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1
7.159 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT
7.159 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN
7.207 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
7.207 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
7.255 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
7.255 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
7.303 0.048 tINS RR 14 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
7.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I0
7.988 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
8.168 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/I3
8.420 0.252 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/F
8.600 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/I2
9.043 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n502_s2/F
9.223 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.653, 67.619%; route: 2.340, 27.989%; tC2Q: 0.367, 4.392%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 1.578
Data Arrival Time 9.223
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK
1.230 0.367 tC2Q RR 25 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/I0
1.915 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/I0
2.600 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I0
3.961 0.505 tINS RR 13 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I1
4.637 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F
4.817 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I0
5.322 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F
5.502 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/I0
6.007 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/F
6.187 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I3
6.439 0.252 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F
6.619 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1
7.159 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT
7.159 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN
7.207 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
7.207 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
7.255 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
7.255 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
7.303 0.048 tINS RR 14 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
7.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I0
7.988 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
8.168 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/I3
8.420 0.252 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/F
8.600 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n499_s2/I2
9.043 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n499_s2/F
9.223 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.653, 67.619%; route: 2.340, 27.989%; tC2Q: 0.367, 4.392%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 1.578
Data Arrival Time 9.223
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK
1.230 0.367 tC2Q RR 25 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/I0
1.915 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/I0
2.600 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I0
3.961 0.505 tINS RR 13 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I1
4.637 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F
4.817 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I0
5.322 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F
5.502 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/I0
6.007 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/F
6.187 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I3
6.439 0.252 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F
6.619 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1
7.159 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT
7.159 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN
7.207 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
7.207 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
7.255 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
7.255 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
7.303 0.048 tINS RR 14 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
7.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I0
7.988 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
8.168 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/I3
8.420 0.252 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/F
8.600 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n497_s2/I2
9.043 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n497_s2/F
9.223 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.653, 67.619%; route: 2.340, 27.989%; tC2Q: 0.367, 4.392%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 1.578
Data Arrival Time 9.223
Data Required Time 10.801
From u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0
To u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1
Launch Clk AHB_CLK[R]
Latch Clk AHB_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 AHB_CLK
0.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
0.683 0.683 tINS RR 290 AHB_CLK_ibuf/O
0.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/CLK
1.230 0.367 tC2Q RR 25 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_cs_r_0_s0/Q
1.410 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/I0
1.915 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s16/F
2.095 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/I0
2.600 0.505 tINS RR 4 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s18/F
2.780 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/I1
3.276 0.496 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s9/F
3.456 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/I0
3.961 0.505 tINS RR 13 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_ns_2_s8/F
4.141 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I1
4.637 0.496 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F
4.817 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/I0
5.322 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s4/F
5.502 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/I0
6.007 0.505 tINS RR 2 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s12/F
6.187 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/I3
6.439 0.252 tINS RR 3 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s15/F
6.619 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1
7.159 0.540 tINS RF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT
7.159 0.000 tNET FF 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN
7.207 0.048 tINS FR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT
7.207 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN
7.255 0.048 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT
7.255 0.000 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN
7.303 0.048 tINS RR 14 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT
7.483 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/I0
7.988 0.505 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s5/F
8.168 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/I3
8.420 0.252 tINS RR 9 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s11/F
8.600 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n496_s2/I2
9.043 0.443 tINS RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n496_s2/F
9.223 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 AHB_CLK
10.000 0.000 tCL RR 1 AHB_CLK_ibuf/I
10.682 0.683 tINS RR 290 AHB_CLK_ibuf/O
10.863 0.180 tNET RR 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1/CLK
10.801 -0.061 tSu 1 u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 5.653, 67.619%; route: 2.340, 27.989%; tC2Q: 0.367, 4.392%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%