Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_soc.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_ddr3.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\riscv_ae350_flash.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_interface.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_rdfifo.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RiscV_AE350_SOC\data\ddr3_memory_wrfifo.v |
GowinSynthesis Constraints File | --- |
Version | V1.9.9 Beta-3 |
Part Number | GW5AST-LV138FPG676AES |
Device | GW5AST-138 |
Device Version | B |
Created Time | Fri Aug 18 18:15:23 2023 |
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | RiscV_AE350_SOC_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 80.945MB Running netlist conversion: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 80.945MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.283s, Peak memory usage = 80.945MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 80.945MB Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 80.945MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 80.945MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 80.945MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 80.945MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 80.945MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.404s, Peak memory usage = 80.945MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.127s, Peak memory usage = 80.945MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 80.945MB Tech-Mapping Phase 3: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 83.320MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.43s, Peak memory usage = 83.320MB Generate output files: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.612s, Peak memory usage = 95.820MB |
Total Time and Memory Usage | CPU time = 0h 0m 12s, Elapsed time = 0h 0m 13s, Peak memory usage = 95.820MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 292 |
I/O Buf | 262 |
    IBUF | 94 |
    OBUF | 141 |
    TBUF | 2 |
    IOBUF | 22 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 3806 |
    DFFSE | 1 |
    DFFRE | 681 |
    DFFPE | 112 |
    DFFCE | 3010 |
    DLCE | 2 |
LUT | 3962 |
    LUT2 | 804 |
    LUT3 | 1630 |
    LUT4 | 1528 |
ALU | 343 |
    ALU | 343 |
SSRAM | 128 |
    RAM16SDP4 | 128 |
INV | 44 |
    INV | 44 |
IOLOGIC | 75 |
    IDES8_MEM | 16 |
    OSER8 | 23 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 22 |
    SDPB | 14 |
    SDPX9B | 8 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DDRDLL | 1 |
AE350_SOC | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 5117(4006 LUT, 343 ALU, 128 RAM16) / 138240 | 4% |
Register | 3806 / 139140 | 3% |
  --Register as Latch | 2 / 139140 | <1% |
  --Register as FF | 3804 / 139140 | 3% |
BSRAM | 22 / 340 | 7% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
DDR3_CLK_IN | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_CLK_IN_ibuf/I | ||
DDR3_MEMORY_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_MEMORY_CLK_ibuf/I | ||
DDR_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR_CLK_ibuf/I | ||
AHB_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AHB_CLK_ibuf/I | ||
FR_PCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | FR_PCLK_ibuf/I | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/u_ddr_init/n1782_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_gclk_0/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/master_gclk_0/n4_s2/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_w_clk_slv_20 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_w_clk_slv_s9/F | ||
u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_w_clk_slv_21 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_spiif/spi_w_clk_slv_s10/O | ||
u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DDR3_MEMORY_CLK_ibuf/I | DDR3_MEMORY_CLK | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | DDR3_CLK_IN | 100.0(MHz) | 265.1(MHz) | 6 | TOP |
2 | DDR3_MEMORY_CLK | 100.0(MHz) | 1506.0(MHz) | 1 | TOP |
3 | DDR_CLK | 100.0(MHz) | 235.8(MHz) | 7 | TOP |
4 | AHB_CLK | 100.0(MHz) | 79.3(MHz) | 21 | TOP |
5 | FR_PCLK | 100.0(MHz) | 152.4(MHz) | 10 | TOP |
6 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
7 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_hwrite_buf/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
8 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
9 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_wr/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
10 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
11 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3_ahb_top/u_fifo_rd/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP |
12 | u_RiscV_AE350_SOC/u_riscv_ae350_ddr3_top/u_ddr3_memory_ahb_top/u_ddr3/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.0(MHz) | 148.5(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -2.618 |
Data Arrival Time | 13.419 |
Data Required Time | 10.801 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/I0 |
2.600 | 0.505 | tINS | RR | 15 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/F |
2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.223 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/I1 |
3.943 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/COUT |
3.943 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/CIN |
3.991 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/COUT |
3.991 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/CIN |
4.039 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/COUT |
4.039 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/CIN |
4.087 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/COUT |
4.087 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/CIN |
4.135 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/COUT |
4.135 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/CIN |
4.183 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/COUT |
4.183 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/CIN |
4.231 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/COUT |
4.231 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/CIN |
4.279 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/COUT |
4.279 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/CIN |
4.327 | 0.048 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/COUT |
4.507 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/I0 |
5.012 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/F |
5.192 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/I2 |
5.635 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/F |
5.815 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/I1 |
6.310 | 0.496 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/F |
6.490 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/I0 |
6.996 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/F |
7.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/I0 |
7.681 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/F |
7.861 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I2 |
8.304 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F |
8.484 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
8.989 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
9.169 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
9.674 | 0.505 | tINS | RR | 13 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
9.854 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/I0 |
10.359 | 0.505 | tINS | RR | 40 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_0_s2/F |
10.539 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s4/I1 |
11.035 | 0.496 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s4/F |
11.215 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/I1 |
11.711 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/next_gray_rd_ptr_2_s0/F |
11.891 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n459_s0/I0 |
12.425 | 0.534 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n459_s0/COUT |
12.425 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n460_s0/CIN |
12.473 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n460_s0/COUT |
12.473 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n461_s0/CIN |
12.521 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n461_s0/COUT |
12.521 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n462_s0/CIN |
12.569 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n462_s0/COUT |
12.569 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n463_s0/CIN |
12.617 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n463_s0/COUT |
12.797 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n466_s2/I2 |
13.239 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/n466_s2/F |
13.419 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0/CLK |
10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_fifo/u_spi_txfifo/empty_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 21 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.950, 71.273%; route: 3.240, 25.803%; tC2Q: 0.367, 2.924% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:Slack | -2.132 |
Data Arrival Time | 12.933 |
Data Required Time | 10.801 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/I0 |
2.600 | 0.505 | tINS | RR | 15 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/F |
2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.223 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/I1 |
3.943 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/COUT |
3.943 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/CIN |
3.991 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/COUT |
3.991 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/CIN |
4.039 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/COUT |
4.039 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/CIN |
4.087 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/COUT |
4.087 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/CIN |
4.135 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/COUT |
4.135 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/CIN |
4.183 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/COUT |
4.183 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/CIN |
4.231 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/COUT |
4.231 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/CIN |
4.279 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/COUT |
4.279 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/CIN |
4.327 | 0.048 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/COUT |
4.507 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/I0 |
5.012 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/F |
5.192 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/I2 |
5.635 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/F |
5.815 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/I1 |
6.310 | 0.496 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/F |
6.490 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/I0 |
6.996 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/F |
7.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/I0 |
7.681 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/F |
7.861 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I2 |
8.304 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F |
8.484 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
8.989 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
9.169 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
9.674 | 0.505 | tINS | RR | 13 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
9.854 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
10.394 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
10.394 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
10.442 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
10.442 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
10.490 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
10.490 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
10.538 | 0.048 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
10.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/I1 |
11.214 | 0.496 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/F |
11.394 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/I3 |
11.646 | 0.252 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/F |
11.826 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/I3 |
12.078 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/F |
12.258 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/I1 |
12.753 | 0.496 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n503_s2/F |
12.933 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.801 | -0.061 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 21 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.464, 70.116%; route: 3.240, 26.842%; tC2Q: 0.367, 3.042% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:Slack | -2.126 |
Data Arrival Time | 12.690 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/I0 |
2.600 | 0.505 | tINS | RR | 15 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/F |
2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.223 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/I1 |
3.943 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/COUT |
3.943 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/CIN |
3.991 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/COUT |
3.991 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/CIN |
4.039 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/COUT |
4.039 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/CIN |
4.087 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/COUT |
4.087 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/CIN |
4.135 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/COUT |
4.135 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/CIN |
4.183 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/COUT |
4.183 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/CIN |
4.231 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/COUT |
4.231 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/CIN |
4.279 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/COUT |
4.279 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/CIN |
4.327 | 0.048 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/COUT |
4.507 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/I0 |
5.012 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/F |
5.192 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/I2 |
5.635 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/F |
5.815 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/I1 |
6.310 | 0.496 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/F |
6.490 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/I0 |
6.996 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/F |
7.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/I0 |
7.681 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/F |
7.861 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I2 |
8.304 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F |
8.484 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
8.989 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
9.169 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
9.674 | 0.505 | tINS | RR | 13 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
9.854 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
10.394 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
10.394 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
10.442 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
10.442 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
10.490 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
10.490 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
10.538 | 0.048 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
10.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/I1 |
11.214 | 0.496 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/F |
11.394 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/I3 |
11.646 | 0.252 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/F |
11.826 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/I3 |
12.078 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/F |
12.258 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
12.510 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
12.690 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_0_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 21 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.220, 69.501%; route: 3.240, 27.394%; tC2Q: 0.367, 3.105% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:Slack | -2.126 |
Data Arrival Time | 12.690 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/I0 |
2.600 | 0.505 | tINS | RR | 15 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/F |
2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.223 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/I1 |
3.943 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/COUT |
3.943 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/CIN |
3.991 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/COUT |
3.991 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/CIN |
4.039 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/COUT |
4.039 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/CIN |
4.087 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/COUT |
4.087 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/CIN |
4.135 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/COUT |
4.135 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/CIN |
4.183 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/COUT |
4.183 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/CIN |
4.231 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/COUT |
4.231 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/CIN |
4.279 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/COUT |
4.279 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/CIN |
4.327 | 0.048 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/COUT |
4.507 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/I0 |
5.012 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/F |
5.192 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/I2 |
5.635 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/F |
5.815 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/I1 |
6.310 | 0.496 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/F |
6.490 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/I0 |
6.996 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/F |
7.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/I0 |
7.681 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/F |
7.861 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I2 |
8.304 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F |
8.484 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
8.989 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
9.169 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
9.674 | 0.505 | tINS | RR | 13 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
9.854 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
10.394 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
10.394 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
10.442 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
10.442 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
10.490 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
10.490 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
10.538 | 0.048 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
10.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/I1 |
11.214 | 0.496 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/F |
11.394 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/I3 |
11.646 | 0.252 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/F |
11.826 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/I3 |
12.078 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/F |
12.258 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
12.510 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
12.690 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 21 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.220, 69.501%; route: 3.240, 27.394%; tC2Q: 0.367, 3.105% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:Slack | -2.126 |
Data Arrival Time | 12.690 |
Data Required Time | 10.564 |
From | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1 |
To | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
Launch Clk | AHB_CLK[R] |
Latch Clk | AHB_CLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | AHB_CLK | |||
0.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
0.683 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
0.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/CLK |
1.230 | 0.367 | tC2Q | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/slave_cmd_2_s1/Q |
1.410 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/I0 |
1.915 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s3/F |
2.095 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/I0 |
2.600 | 0.505 | tINS | RR | 15 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s6/F |
2.780 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/I2 |
3.223 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/arb_wr_num_0_s1/F |
3.403 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/I1 |
3.943 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n394_s0/COUT |
3.943 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/CIN |
3.991 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n395_s0/COUT |
3.991 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/CIN |
4.039 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n396_s0/COUT |
4.039 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/CIN |
4.087 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n397_s0/COUT |
4.087 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/CIN |
4.135 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n398_s0/COUT |
4.135 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/CIN |
4.183 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n399_s0/COUT |
4.183 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/CIN |
4.231 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n400_s0/COUT |
4.231 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/CIN |
4.279 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n401_s0/COUT |
4.279 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/CIN |
4.327 | 0.048 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n402_s0/COUT |
4.507 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/I0 |
5.012 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s10/F |
5.192 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/I2 |
5.635 | 0.443 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s8/F |
5.815 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/I1 |
6.310 | 0.496 | tINS | RR | 8 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n609_s6/F |
6.490 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/I0 |
6.996 | 0.505 | tINS | RR | 3 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_2_s12/F |
7.176 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/I0 |
7.681 | 0.505 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s42/F |
7.861 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/I2 |
8.304 | 0.443 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s7/F |
8.484 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/I0 |
8.989 | 0.505 | tINS | RR | 2 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s3/F |
9.169 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/I0 |
9.674 | 0.505 | tINS | RR | 13 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/ctrl_ns_0_s2/F |
9.854 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/I1 |
10.394 | 0.540 | tINS | RF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n9_s0/COUT |
10.394 | 0.000 | tNET | FF | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/CIN |
10.442 | 0.048 | tINS | FR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n10_s0/COUT |
10.442 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/CIN |
10.490 | 0.048 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n11_s0/COUT |
10.490 | 0.000 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/CIN |
10.538 | 0.048 | tINS | RR | 7 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/n12_s0/COUT |
10.718 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/I1 |
11.214 | 0.496 | tINS | RR | 4 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/rx_mask_cnt_r_1_s5/F |
11.394 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/I3 |
11.646 | 0.252 | tINS | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s8/F |
11.826 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/I3 |
12.078 | 0.252 | tINS | RR | 10 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s13/F |
12.258 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/I3 |
12.510 | 0.252 | tINS | RR | 9 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_8_s3/F |
12.690 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CE |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | AHB_CLK | |||
10.000 | 0.000 | tCL | RR | 1 | AHB_CLK_ibuf/I |
10.682 | 0.683 | tINS | RR | 475 | AHB_CLK_ibuf/O |
10.863 | 0.180 | tNET | RR | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1/CLK |
10.564 | -0.299 | tSu | 1 | u_RiscV_AE350_SOC/u_riscv_ae350_flash_top/u_gwspiflash/u_spi_ctrl/data_cnt_r_2_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 21 |
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Arrival Data Path Delay: | cell: 8.220, 69.501%; route: 3.240, 27.394%; tC2Q: 0.367, 3.105% |
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |