Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.11.01 (64-bit) |
Part Number | GW5AST-LV138FPG676AC1/I0 |
Device | GW5AST-138 |
Device Version | B |
Created Time | Thu Feb 27 16:36:55 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | DDR3_Memory_Interface_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 156.828MB Running netlist conversion: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 156.828MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.343s, Peak memory usage = 156.828MB Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.419s, Peak memory usage = 156.828MB Optimizing Phase 2: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.567s, Peak memory usage = 156.828MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.309s, Peak memory usage = 156.828MB Inferring Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.128s, Peak memory usage = 156.828MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 156.828MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 156.828MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.401s, Peak memory usage = 156.828MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 156.828MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 156.828MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 171.488MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.577s, Peak memory usage = 171.488MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 2s, Peak memory usage = 172.316MB |
Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 13s, Peak memory usage = 172.316MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 371 |
I/O Buf | 365 |
    IBUF | 182 |
    OBUF | 162 |
    TBUF | 2 |
    IOBUF | 16 |
    ELVDS_OBUF | 1 |
    ELVDS_IOBUF | 2 |
Register | 3411 |
    DFFSE | 1 |
    DFFRE | 249 |
    DFFPE | 66 |
    DFFCE | 3095 |
LUT | 2113 |
    LUT2 | 304 |
    LUT3 | 963 |
    LUT4 | 846 |
ALU | 125 |
    ALU | 125 |
INV | 21 |
    INV | 21 |
IOLOGIC | 76 |
    IDES8_MEM | 16 |
    OSER8 | 24 |
    OSER8_MEM | 20 |
    IODELAY | 16 |
BSRAM | 8 |
    SDPB | 4 |
    SDPX9B | 4 |
CLOCK | 4 |
    CLKDIV | 1 |
    DQS | 2 |
    DDRDLL | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 2259(2134 LUT, 125 ALU) / 138240 | 2% |
Register | 3411 / 139140 | 3% |
  --Register as Latch | 0 / 139140 | 0% |
  --Register as FF | 3411 / 139140 | 3% |
BSRAM | 8 / 340 | 3% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | memory_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
2 | clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | ||
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | memory_clk_ibuf/I | memory_clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | memory_clk | 100.000(MHz) | 1115.449(MHz) | 1 | TOP |
2 | clk | 100.000(MHz) | 148.148(MHz) | 7 | TOP |
3 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 25.000(MHz) | 161.225(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 2.287 |
Data Arrival Time | 2.579 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.381 | 0.381 | tCL | RR | 3450 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK |
1.176 | 0.382 | tC2Q | RR | 12 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q |
1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0 |
2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F |
2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 64 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.408 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:Slack | 2.287 |
Data Arrival Time | 2.579 |
Data Required Time | 4.866 |
From | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0 |
To | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Launch Clk | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
Latch Clk | memory_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
0.381 | 0.381 | tCL | RR | 3450 | gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
0.793 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK |
1.176 | 0.382 | tC2Q | RR | 11 | gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q |
1.588 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0 |
2.167 | 0.579 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F |
2.579 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
5.000 | 0.000 | memory_clk | |||
5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
5.000 | 0.000 | tINS | FF | 64 | memory_clk_ibuf/O |
5.385 | 0.385 | tNET | FF | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
5.350 | -0.035 | tUnc | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
4.866 | -0.484 | tSu | 1 | gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
Clock Skew: | -0.408 |
Setup Relationship: | 5.000 |
Logic Level: | 2 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 0.579, 32.400%; route: 0.825, 46.186%; tC2Q: 0.382, 21.414% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:Slack | 3.250 |
Data Arrival Time | 7.099 |
Data Required Time | 10.349 |
From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.786 | 0.579 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.199 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/I1 |
2.766 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/F |
3.179 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/I1 |
3.746 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/F |
4.159 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/I1 |
4.726 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/F |
5.139 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
5.706 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/F |
6.119 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s4/I1 |
6.686 | 0.567 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s4/F |
7.099 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1/CLK |
10.349 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_12_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.416, 51.093%; route: 2.887, 43.186%; tC2Q: 0.382, 5.721% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:Slack | 3.250 |
Data Arrival Time | 7.099 |
Data Required Time | 10.349 |
From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.786 | 0.579 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.199 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/I1 |
2.766 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/F |
3.179 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/I1 |
3.746 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/F |
4.159 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/I1 |
4.726 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/F |
5.139 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
5.706 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/F |
6.119 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/I1 |
6.686 | 0.567 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n44_s1/F |
7.099 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1/CLK |
10.349 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_13_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.416, 51.093%; route: 2.887, 43.186%; tC2Q: 0.382, 5.721% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:Slack | 3.529 |
Data Arrival Time | 6.820 |
Data Required Time | 10.349 |
From | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3 |
To | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
0.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/CLK |
0.795 | 0.382 | tC2Q | RR | 6 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_0_s3/Q |
1.207 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/I0 |
1.786 | 0.579 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n53_s2/F |
2.199 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/I1 |
2.766 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n52_s2/F |
3.179 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/I1 |
3.746 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n49_s3/F |
4.159 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/I1 |
4.726 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n48_s2/F |
5.139 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/I1 |
5.706 | 0.567 | tINS | RR | 3 | gw3_top/u_ddr_phy_top/ddr_sync/n45_s3/F |
6.119 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n43_s1/I3 |
6.408 | 0.289 | tINS | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/n43_s1/F |
6.820 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
10.000 | 0.000 | clk | |||
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
10.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
10.413 | 0.413 | tNET | RR | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1/CLK |
10.349 | -0.064 | tSu | 1 | gw3_top/u_ddr_phy_top/ddr_sync/lock_cnt_14_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 10.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Arrival Data Path Delay: | cell: 3.138, 48.966%; route: 2.887, 45.064%; tC2Q: 0.382, 5.970% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |