Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\CAN\data\can.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\CAN\data\can_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Wed Feb 26 16:30:07 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module CAN_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.765s, Peak memory usage = 142.699MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 142.699MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.703s, Peak memory usage = 142.699MB
    Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.186s, Peak memory usage = 142.699MB
    Optimizing Phase 2: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.457s, Peak memory usage = 142.699MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 142.699MB
    Inferring Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.294s, Peak memory usage = 142.699MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 142.699MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 142.699MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.8s, Peak memory usage = 142.699MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 142.699MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.259s, Peak memory usage = 142.699MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 24s, Elapsed time = 0h 0m 24s, Peak memory usage = 173.098MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.533s, Peak memory usage = 173.098MB
Generate output files:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.5s, Peak memory usage = 173.098MB
Total Time and Memory Usage CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 173.098MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 121
I/O Buf 94
    IBUF 57
    OBUF 37
Register 2179
    DFFSE 6
    DFFRE 9
    DFFPE 10
    DFFCE 2154
LUT 4316
    LUT2 289
    LUT3 1030
    LUT4 2997
ALU 357
    ALU 357
INV 19
    INV 19
BSRAM 1
    SP 1

Resource Utilization Summary

Resource Usage Utilization
Logic 4692(4335 LUT, 357 ALU) / 138240 4%
Register 2179 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 2179 / 139140 2%
BSRAM 1 / 340 <1%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 canclk Base 10.000 100.000 0.000 5.000 canclk_ibuf/I
2 sysclk Base 10.000 100.000 0.000 5.000 sysclk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 canclk 100.000(MHz) 72.536(MHz) 16 TOP
2 sysclk 100.000(MHz) 121.029(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -3.816
Data Arrival Time 14.130
Data Required Time 10.314
From u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0
To u_canc_top/u_canc_0/u_cbsp_0/cbsp_txd_s0
Launch Clk sysclk[R]
Latch Clk canclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sysclk
0.000 0.000 tCL RR 1 sysclk_ibuf/I
0.000 0.000 tINS RR 1740 sysclk_ibuf/O
0.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/Q
1.207 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/I0
1.803 0.595 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/COUT
1.803 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/CIN
2.046 0.244 tINS FR 5 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/SUM
2.459 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/I1
3.026 0.567 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/F
3.439 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/I0
4.018 0.579 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/F
4.430 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/I1
5.030 0.600 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/COUT
5.030 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/CIN
5.274 0.244 tINS FR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/SUM
5.686 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/I1
6.254 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/F
6.666 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/I3
6.955 0.289 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/F
7.368 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/I2
7.875 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/F
8.288 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/I2
8.795 0.507 tINS RR 2 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/F
9.208 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/I1
9.775 0.567 tINS RR 5 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/F
10.188 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/I1
10.755 0.567 tINS RR 12 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/F
11.168 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s8/I0
11.746 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s8/F
12.159 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s3/I0
12.738 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s3/F
13.150 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s1/I1
13.718 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8944_s1/F
14.130 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/cbsp_txd_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 canclk
10.000 0.000 tCL RR 1 canclk_ibuf/I
10.000 0.000 tINS RR 440 canclk_ibuf/O
10.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/cbsp_txd_s0/CLK
10.378 -0.035 tUnc u_canc_top/u_canc_0/u_cbsp_0/cbsp_txd_s0
10.314 -0.064 tSu 1 u_canc_top/u_canc_0/u_cbsp_0/cbsp_txd_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.560, 55.112%; route: 5.775, 42.100%; tC2Q: 0.382, 2.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -3.816
Data Arrival Time 14.130
Data Required Time 10.314
From u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0
To u_canc_top/u_canc_0/u_cbsp_0/c_state_3_s0
Launch Clk sysclk[R]
Latch Clk canclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sysclk
0.000 0.000 tCL RR 1 sysclk_ibuf/I
0.000 0.000 tINS RR 1740 sysclk_ibuf/O
0.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/Q
1.207 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/I0
1.803 0.595 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/COUT
1.803 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/CIN
2.046 0.244 tINS FR 5 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/SUM
2.459 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/I1
3.026 0.567 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/F
3.439 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/I0
4.018 0.579 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/F
4.430 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/I1
5.030 0.600 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/COUT
5.030 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/CIN
5.274 0.244 tINS FR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/SUM
5.686 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/I1
6.254 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/F
6.666 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/I3
6.955 0.289 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/F
7.368 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/I2
7.875 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/F
8.288 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/I2
8.795 0.507 tINS RR 2 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/F
9.208 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/I1
9.775 0.567 tINS RR 5 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/F
10.188 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/I1
10.755 0.567 tINS RR 12 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/F
11.168 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s5/I1
11.735 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s5/F
12.148 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s2/I0
12.726 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s2/F
13.139 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s1/I0
13.718 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8940_s1/F
14.130 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 canclk
10.000 0.000 tCL RR 1 canclk_ibuf/I
10.000 0.000 tINS RR 440 canclk_ibuf/O
10.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_3_s0/CLK
10.378 -0.035 tUnc u_canc_top/u_canc_0/u_cbsp_0/c_state_3_s0
10.314 -0.064 tSu 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.560, 55.112%; route: 5.775, 42.100%; tC2Q: 0.382, 2.788%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -3.756
Data Arrival Time 14.070
Data Required Time 10.314
From u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0
To u_canc_top/u_canc_0/u_cbsp_0/c_state_2_s0
Launch Clk sysclk[R]
Latch Clk canclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sysclk
0.000 0.000 tCL RR 1 sysclk_ibuf/I
0.000 0.000 tINS RR 1740 sysclk_ibuf/O
0.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/Q
1.207 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/I0
1.803 0.595 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/COUT
1.803 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/CIN
2.046 0.244 tINS FR 5 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/SUM
2.459 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/I1
3.026 0.567 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/F
3.439 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/I0
4.018 0.579 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/F
4.430 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/I1
5.030 0.600 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/COUT
5.030 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/CIN
5.274 0.244 tINS FR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/SUM
5.686 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/I1
6.254 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/F
6.666 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/I3
6.955 0.289 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/F
7.368 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/I2
7.875 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/F
8.288 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/I2
8.795 0.507 tINS RR 2 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/F
9.208 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/I1
9.775 0.567 tINS RR 5 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/F
10.188 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/I1
10.755 0.567 tINS RR 12 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/F
11.168 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s80/I2
11.675 0.507 tINS RR 4 u_canc_top/u_canc_0/u_cbsp_0/n8631_s80/F
12.088 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8941_s2/I0
12.666 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8941_s2/F
13.079 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8941_s1/I0
13.658 0.579 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8941_s1/F
14.070 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 canclk
10.000 0.000 tCL RR 1 canclk_ibuf/I
10.000 0.000 tINS RR 440 canclk_ibuf/O
10.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_2_s0/CLK
10.378 -0.035 tUnc u_canc_top/u_canc_0/u_cbsp_0/c_state_2_s0
10.314 -0.064 tSu 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.500, 54.915%; route: 5.775, 42.284%; tC2Q: 0.382, 2.801%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -3.734
Data Arrival Time 14.048
Data Required Time 10.314
From u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0
To u_canc_top/u_canc_0/u_cbsp_0/c_state_1_s0
Launch Clk sysclk[R]
Latch Clk canclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sysclk
0.000 0.000 tCL RR 1 sysclk_ibuf/I
0.000 0.000 tINS RR 1740 sysclk_ibuf/O
0.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/Q
1.207 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/I0
1.803 0.595 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/COUT
1.803 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/CIN
2.046 0.244 tINS FR 5 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/SUM
2.459 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/I1
3.026 0.567 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/F
3.439 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/I0
4.018 0.579 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/F
4.430 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/I1
5.030 0.600 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/COUT
5.030 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/CIN
5.274 0.244 tINS FR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/SUM
5.686 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/I1
6.254 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/F
6.666 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/I3
6.955 0.289 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/F
7.368 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/I2
7.875 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/F
8.288 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/I2
8.795 0.507 tINS RR 2 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/F
9.208 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/I1
9.775 0.567 tINS RR 5 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/F
10.188 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/I1
10.755 0.567 tINS RR 12 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/F
11.168 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s80/I2
11.675 0.507 tINS RR 4 u_canc_top/u_canc_0/u_cbsp_0/n8631_s80/F
12.088 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8942_s3/I1
12.655 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8942_s3/F
13.068 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8942_s1/I1
13.635 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8942_s1/F
14.048 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 canclk
10.000 0.000 tCL RR 1 canclk_ibuf/I
10.000 0.000 tINS RR 440 canclk_ibuf/O
10.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_1_s0/CLK
10.378 -0.035 tUnc u_canc_top/u_canc_0/u_cbsp_0/c_state_1_s0
10.314 -0.064 tSu 1 u_canc_top/u_canc_0/u_cbsp_0/c_state_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.478, 54.841%; route: 5.775, 42.354%; tC2Q: 0.382, 2.805%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -3.674
Data Arrival Time 13.988
Data Required Time 10.314
From u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0
To u_canc_top/u_canc_0/u_cbsp_0/txstuffcntr_tot_2_s0
Launch Clk sysclk[R]
Latch Clk canclk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sysclk
0.000 0.000 tCL RR 1 sysclk_ibuf/I
0.000 0.000 tINS RR 1740 sysclk_ibuf/O
0.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/CLK
0.795 0.382 tC2Q RR 5 u_canc_top/u_canc_0/u_cregs_0/phseg2_nom_0_s0/Q
1.207 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/I0
1.803 0.595 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_0_s/COUT
1.803 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/CIN
2.046 0.244 tINS FR 5 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_pre_nom_1_s/SUM
2.459 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/I1
3.026 0.567 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s1/F
3.439 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/I0
4.018 0.579 tINS RR 2 u_canc_top/u_canc_0/u_cbtl_0/pherrcnt_neg_post_nom_2_s0/F
4.430 0.413 tNET RR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/I1
5.030 0.600 tINS RF 1 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_2_s/COUT
5.030 0.000 tNET FF 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/CIN
5.274 0.244 tINS FR 2 u_canc_top/u_canc_0/u_cbtl_0/phseg2_adj_nom_3_s/SUM
5.686 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/I1
6.254 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s100/F
6.666 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/I3
6.955 0.289 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s97/F
7.368 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/I2
7.875 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s92/F
8.288 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/I2
8.795 0.507 tINS RR 2 u_canc_top/u_canc_0/u_cbsp_0/n8631_s87/F
9.208 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/I1
9.775 0.567 tINS RR 5 u_canc_top/u_canc_0/u_cbsp_0/n8631_s85/F
10.188 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/I1
10.755 0.567 tINS RR 12 u_canc_top/u_canc_0/u_cbsp_0/n8631_s82/F
11.168 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s99/I2
11.675 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s99/F
12.088 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s96/I1
12.655 0.567 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s96/F
13.068 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s94/I2
13.575 0.507 tINS RR 1 u_canc_top/u_canc_0/u_cbsp_0/n8580_s94/F
13.988 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/txstuffcntr_tot_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 canclk
10.000 0.000 tCL RR 1 canclk_ibuf/I
10.000 0.000 tINS RR 440 canclk_ibuf/O
10.413 0.413 tNET RR 1 u_canc_top/u_canc_0/u_cbsp_0/txstuffcntr_tot_2_s0/CLK
10.378 -0.035 tUnc u_canc_top/u_canc_0/u_cbsp_0/txstuffcntr_tot_2_s0
10.314 -0.064 tSu 1 u_canc_top/u_canc_0/u_cbsp_0/txstuffcntr_tot_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.418, 54.641%; route: 5.775, 42.541%; tC2Q: 0.382, 2.818%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%