Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code_hs.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm_5a.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\eth_mac.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\eth_mac_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm_5a.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\PSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\parameter.vh
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v
F:\EMB_pub\embedded\risc_v\ae350_soc\example\1.3\AHB_Master\ref_design\FPGA_RefDesign\DK_START_GW5AST138_V1.1\ae350_ahb_master\src\gowin_empu_m1\temp\gw_empu_m1\DDR3_define.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Wed Feb 26 15:02:01 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_EMPU_M1_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 4s, Elapsed time = 0h 0m 6s, Peak memory usage = 177.832MB
Running netlist conversion:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 177.832MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.573s, Peak memory usage = 177.832MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 177.832MB
    Optimizing Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.416s, Peak memory usage = 177.832MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.347s, Peak memory usage = 177.832MB
    Inferring Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 177.832MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 177.832MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 177.832MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.542s, Peak memory usage = 177.832MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 177.832MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.201s, Peak memory usage = 177.832MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 16s, Elapsed time = 0h 0m 16s, Peak memory usage = 179.074MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.479s, Peak memory usage = 179.074MB
Generate output files:
    CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.935s, Peak memory usage = 180.418MB
Total Time and Memory Usage CPU time = 0h 0m 23s, Elapsed time = 0h 0m 26s, Peak memory usage = 180.418MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 126
I/O Buf 125
    IBUF 37
    OBUF 88
Register 1816
    DFFSE 1
    DFFRE 516
    DFFPE 92
    DFFCE 1207
LUT 3797
    LUT2 268
    LUT3 1486
    LUT4 2043
ALU 49
    ALU 49
INV 2
    INV 2
DSP
    MULT27X36 2
BSRAM 32
    SP 32

Resource Utilization Summary

Resource Usage Utilization
Logic 3848(3799 LUT, 49 ALU) / 138240 3%
Register 1816 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1816 / 139140 2%
BSRAM 32 / 340 10%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 HCLK Base 10.000 100.000 0.000 5.000 HCLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 HCLK 100.000(MHz) 67.877(MHz) 17 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -4.733
Data Arrival Time 15.081
Data Required Time 10.349
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 1851 HCLK_ibuf/O
0.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/CLK
0.795 0.382 tC2Q RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/Q
1.207 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/I0
1.786 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/F
2.199 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/I1
2.349 0.150 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/O
2.761 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/I1
2.848 0.086 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/O
3.260 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/I1
3.346 0.086 tINS RR 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/O
3.759 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
4.338 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
4.750 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
5.318 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
5.730 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
6.298 0.567 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
6.710 0.413 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
7.310 0.600 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
7.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
7.360 0.050 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
7.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
7.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
7.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
7.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
7.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
7.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
7.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
7.560 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
7.560 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
7.610 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
7.610 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
7.660 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
7.660 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
7.710 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
7.710 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
7.760 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
7.760 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
7.810 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
7.810 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
7.860 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
7.860 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
7.910 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
7.910 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
7.960 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
7.960 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
8.010 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
8.010 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
8.060 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
8.060 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
8.110 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
8.110 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
8.160 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
8.160 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
8.210 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
8.210 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
8.260 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
8.260 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
8.310 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
8.310 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
8.360 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
8.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
8.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
8.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
8.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
8.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
8.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT
8.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN
8.754 0.244 tINS RR 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/SUM
9.166 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I0
9.745 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
10.158 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/I3
10.446 0.289 tINS RR 3 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/F
10.859 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s5/I2
11.366 0.507 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s5/F
11.779 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s11/I3
12.068 0.289 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s11/F
12.480 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s9/I2
12.988 0.507 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s9/F
13.400 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1
13.968 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F
14.380 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3
14.669 0.289 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F
15.081 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 1851 HCLK_ibuf/O
10.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK
10.349 -0.064 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 7.686, 52.398%; route: 6.600, 44.994%; tC2Q: 0.382, 2.608%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack -2.740
Data Arrival Time 13.089
Data Required Time 10.349
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 1851 HCLK_ibuf/O
0.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/CLK
0.795 0.382 tC2Q RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/Q
1.207 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/I0
1.786 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/F
2.199 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/I1
2.349 0.150 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/O
2.761 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/I1
2.848 0.086 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/O
3.260 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/I1
3.346 0.086 tINS RR 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/O
3.759 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
4.338 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
4.750 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
5.318 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
5.730 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
6.298 0.567 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
6.710 0.413 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
7.310 0.600 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
7.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
7.360 0.050 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
7.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
7.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
7.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
7.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
7.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
7.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
7.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
7.560 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
7.560 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
7.610 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
7.610 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
7.660 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
7.660 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
7.710 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
7.710 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
7.760 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
7.760 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
7.810 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
7.810 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
7.860 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
7.860 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
7.910 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
7.910 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
7.960 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
7.960 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
8.010 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
8.010 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
8.060 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
8.060 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
8.110 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
8.110 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
8.160 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
8.160 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
8.210 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
8.210 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
8.260 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
8.260 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
8.310 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
8.310 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
8.360 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
8.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
8.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
8.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
8.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
8.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
8.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT
8.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN
8.560 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT
8.560 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN
8.610 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT
8.610 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN
8.660 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT
8.660 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN
8.710 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT
8.710 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN
8.954 0.244 tINS RR 8 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM
9.366 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/I1
9.934 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s3/F
10.346 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I3
10.635 0.289 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
11.048 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I1
11.615 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F
12.028 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0
12.178 0.150 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O
12.590 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0
12.676 0.086 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O
13.089 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 1851 HCLK_ibuf/O
10.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK
10.349 -0.064 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 6.519, 51.425%; route: 5.775, 45.558%; tC2Q: 0.382, 3.017%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack -2.191
Data Arrival Time 12.540
Data Required Time 10.349
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 1851 HCLK_ibuf/O
0.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/CLK
0.795 0.382 tC2Q RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/Q
1.207 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/I0
1.786 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/F
2.199 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/I1
2.349 0.150 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/O
2.761 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/I1
2.848 0.086 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/O
3.260 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/I1
3.346 0.086 tINS RR 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/O
3.759 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
4.338 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
4.750 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
5.318 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
5.730 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
6.298 0.567 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
6.710 0.413 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
7.310 0.600 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
7.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
7.360 0.050 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
7.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
7.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
7.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
7.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
7.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
7.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
7.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
7.560 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
7.560 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
7.610 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
7.610 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
7.660 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
7.660 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
7.710 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
7.710 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
7.760 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
7.760 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
7.810 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
7.810 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
7.860 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
7.860 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
7.910 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
7.910 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
7.960 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
7.960 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
8.010 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
8.010 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
8.060 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
8.060 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
8.110 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
8.110 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
8.160 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
8.160 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
8.210 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
8.210 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
8.260 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
8.260 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
8.310 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
8.310 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
8.360 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
8.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
8.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
8.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
8.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
8.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
8.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT
8.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN
8.754 0.244 tINS RR 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/SUM
9.166 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I0
9.745 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
10.158 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/I3
10.446 0.289 tINS RR 3 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/F
10.859 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s6/I3
11.148 0.289 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s6/F
11.560 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I1
12.128 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F
12.540 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 1851 HCLK_ibuf/O
10.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK
10.349 -0.064 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 6.383, 52.628%; route: 5.362, 44.218%; tC2Q: 0.382, 3.154%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack -2.131
Data Arrival Time 12.480
Data Required Time 10.349
From M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1
To M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 1851 HCLK_ibuf/O
0.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/CLK
0.795 0.382 tC2Q RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_RAMREG_7_G[2]_s1/Q
1.207 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/I0
1.786 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s15/F
2.199 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/I1
2.349 0.150 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s7/O
2.761 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/I1
2.848 0.086 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s3/O
3.260 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/I1
3.346 0.086 tINS RR 7 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_RAMOUT_30_G[0]_s1/O
3.759 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
4.338 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
4.750 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
5.318 0.567 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
5.730 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
6.298 0.567 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
6.710 0.413 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
7.310 0.600 tINS RF 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
7.310 0.000 tNET FF 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
7.360 0.050 tINS FR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
7.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
7.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
7.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
7.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT
7.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN
7.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT
7.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN
7.560 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT
7.560 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN
7.610 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT
7.610 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN
7.660 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT
7.660 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN
7.710 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT
7.710 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN
7.760 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT
7.760 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN
7.810 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
7.810 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
7.860 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
7.860 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
7.910 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
7.910 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
7.960 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
7.960 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
8.010 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
8.010 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
8.060 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
8.060 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
8.110 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
8.110 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
8.160 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
8.160 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
8.210 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
8.210 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
8.260 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
8.260 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
8.310 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
8.310 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
8.360 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT
8.360 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN
8.410 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT
8.410 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN
8.460 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT
8.460 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN
8.510 0.050 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT
8.510 0.000 tNET RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN
8.754 0.244 tINS RR 4 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/SUM
9.166 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/I0
9.745 0.579 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s9/F
10.158 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/I3
10.446 0.289 tINS RR 3 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s2/F
10.859 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s6/I3
11.148 0.289 tINS RR 2 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s6/F
11.560 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I2
12.068 0.507 tINS RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F
12.480 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 1851 HCLK_ibuf/O
10.413 0.413 tNET RR 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK
10.349 -0.064 tSu 1 M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 6.323, 52.392%; route: 5.362, 44.438%; tC2Q: 0.382, 3.170%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack -1.132
Data Arrival Time 11.234
Data Required Time 10.101
From u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/RegAddr_29_s0
To u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1
Launch Clk HCLK[R]
Latch Clk HCLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 HCLK
0.000 0.000 tCL RR 1 HCLK_ibuf/I
0.000 0.000 tINS RR 1851 HCLK_ibuf/O
0.413 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/RegAddr_29_s0/CLK
0.795 0.382 tC2Q RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/RegAddr_29_s0/Q
1.207 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HADDR_d_29_s0/I0
1.786 0.579 tINS RR 7 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HADDR_d_29_s0/F
2.199 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/I0
2.778 0.579 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s3/F
3.190 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s2/I1
3.758 0.567 tINS RR 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage6/uOutputArb/NoPortNext_s2/F
4.170 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s5/I0
4.749 0.579 tINS RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s5/F
5.161 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s1/I1
5.729 0.567 tINS RR 11 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uMatrixDecodeS0/AddrOutPort_0_s1/F
6.141 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s13/I2
6.649 0.507 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s13/F
7.061 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s5/I1
7.211 0.150 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s5/O
7.624 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s1/I1
7.710 0.086 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s1/O
8.123 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/I1
8.209 0.086 tINS RR 3 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage8/Active0to8_s/O
8.621 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s7/I0
9.200 0.579 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s7/F
9.613 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s2/I2
10.120 0.507 tINS RR 2 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/n115_s2/F
10.533 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/I3
10.821 0.289 tINS RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s3/F
11.234 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 HCLK
10.000 0.000 tCL RR 1 HCLK_ibuf/I
10.000 0.000 tINS RR 1851 HCLK_ibuf/O
10.413 0.413 tNET RR 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CLK
10.101 -0.311 tSu 1 u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 5.076, 46.910%; route: 5.362, 49.555%; tC2Q: 0.382, 3.535%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%