Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\TSE_MAC\data\eth_mac_top.v
D:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\TSE_MAC\data\eth_mac.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Thu Feb 27 14:50:20 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Triple_Speed_Ethernet_MAC_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.422s, Peak memory usage = 113.637MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 113.637MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 113.637MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 113.637MB
    Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.137s, Peak memory usage = 113.637MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 113.637MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 113.637MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 113.637MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 113.637MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 113.637MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 113.637MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 113.637MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 140.277MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.281s, Peak memory usage = 140.289MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 140.289MB
Total Time and Memory Usage CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 140.289MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 247
I/O Buf 247
    IBUF 129
    OBUF 118
Register 1214
    DFFPE 79
    DFFCE 1135
LUT 1225
    LUT2 231
    LUT3 265
    LUT4 729
ALU 6
    ALU 6
INV 8
    INV 8
IOLOGIC 16
    IDDR 5
    ODDR 6
    IODELAY 5

Resource Utilization Summary

Resource Usage Utilization
Logic 1239(1233 LUT, 6 ALU) / 138240 <1%
Register 1214 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 1214 / 139140 <1%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 rgmii_rxc Base 10.000 100.000 0.000 5.000 rgmii_rxc_ibuf/I
2 gtx_clk Base 10.000 100.000 0.000 5.000 gtx_clk_ibuf/I
3 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 rgmii_rxc 100.000(MHz) 172.973(MHz) 6 TOP
2 gtx_clk 100.000(MHz) 169.241(MHz) 6 TOP
3 clk 100.000(MHz) 193.658(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.091
Data Arrival Time 6.010
Data Required Time 10.101
From u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0
To u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s1
Launch Clk gtx_clk[R]
Latch Clk gtx_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gtx_clk
0.000 0.000 tCL RR 1 gtx_clk_ibuf/I
0.000 0.000 tINS RR 578 gtx_clk_ibuf/O
0.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0/CLK
0.795 0.382 tC2Q RR 3 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0/Q
1.207 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s5/I0
1.786 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s5/F
2.199 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s3/I0
2.778 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s3/F
3.190 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s1/I2
3.697 0.507 tINS RR 2 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s1/F
4.110 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s0/I2
4.618 0.507 tINS RR 5 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s0/F
5.030 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s4/I1
5.598 0.567 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s4/F
6.010 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 gtx_clk
10.000 0.000 tCL RR 1 gtx_clk_ibuf/I
10.000 0.000 tINS RR 578 gtx_clk_ibuf/O
10.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s1/CLK
10.101 -0.311 tSu 1 u_triple_speed_mac/u_mac_tx_ctrl/type_ptr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.740, 48.951%; route: 2.475, 44.216%; tC2Q: 0.382, 6.833%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 4.151
Data Arrival Time 5.950
Data Required Time 10.101
From u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0
To u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s1
Launch Clk gtx_clk[R]
Latch Clk gtx_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gtx_clk
0.000 0.000 tCL RR 1 gtx_clk_ibuf/I
0.000 0.000 tINS RR 578 gtx_clk_ibuf/O
0.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0/CLK
0.795 0.382 tC2Q RR 3 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_4_s0/Q
1.207 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s5/I0
1.786 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s5/F
2.199 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s3/I0
2.778 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s3/F
3.190 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s1/I2
3.697 0.507 tINS RR 2 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s1/F
4.110 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s0/I2
4.618 0.507 tINS RR 5 u_triple_speed_mac/u_mac_tx_ctrl/n1906_s0/F
5.030 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s4/I2
5.538 0.507 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s4/F
5.950 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 gtx_clk
10.000 0.000 tCL RR 1 gtx_clk_ibuf/I
10.000 0.000 tINS RR 578 gtx_clk_ibuf/O
10.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s1/CLK
10.101 -0.311 tSu 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_vlan_frame_latch_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.680, 48.398%; route: 2.475, 44.695%; tC2Q: 0.382, 6.907%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 4.163
Data Arrival Time 5.939
Data Required Time 10.101
From u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_9_s0
To u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s1
Launch Clk gtx_clk[R]
Latch Clk gtx_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gtx_clk
0.000 0.000 tCL RR 1 gtx_clk_ibuf/I
0.000 0.000 tINS RR 578 gtx_clk_ibuf/O
0.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_9_s0/CLK
0.795 0.382 tC2Q RR 4 u_triple_speed_mac/u_mac_tx_ctrl/statistics_data_reg_9_s0/Q
1.207 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s3/I0
1.786 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s3/F
2.199 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s2/I1
2.766 0.567 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s2/F
3.179 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s1/I2
3.686 0.507 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s1/F
4.099 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s0/I2
4.606 0.507 tINS RR 2 u_triple_speed_mac/u_mac_tx_ctrl/n1938_s0/F
5.019 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s4/I2
5.526 0.507 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s4/F
5.939 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 gtx_clk
10.000 0.000 tCL RR 1 gtx_clk_ibuf/I
10.000 0.000 tINS RR 578 gtx_clk_ibuf/O
10.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s1/CLK
10.101 -0.311 tSu 1 u_triple_speed_mac/u_mac_tx_ctrl/tx_mac_ctrl_frm_latch_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.669, 48.292%; route: 2.475, 44.786%; tC2Q: 0.382, 6.922%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 4.207
Data Arrival Time 6.141
Data Required Time 10.349
From u_triple_speed_mac/u_mac_tx_ctrl/c_state_0_s0
To u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_16_s1
Launch Clk gtx_clk[R]
Latch Clk gtx_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gtx_clk
0.000 0.000 tCL RR 1 gtx_clk_ibuf/I
0.000 0.000 tINS RR 578 gtx_clk_ibuf/O
0.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/c_state_0_s0/CLK
0.795 0.382 tC2Q RR 24 u_triple_speed_mac/u_mac_tx_ctrl/c_state_0_s0/Q
1.207 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n828_s1/I0
1.786 0.579 tINS RR 30 u_triple_speed_mac/u_mac_tx_ctrl/n828_s1/F
2.199 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n259_s4/I1
2.766 0.567 tINS RR 4 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n259_s4/F
3.179 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n285_s5/I0
3.758 0.579 tINS RR 5 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n285_s5/F
4.170 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n274_s4/I0
4.749 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n274_s4/F
5.161 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n274_s2/I1
5.729 0.567 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/n274_s2/F
6.141 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_16_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 gtx_clk
10.000 0.000 tCL RR 1 gtx_clk_ibuf/I
10.000 0.000 tINS RR 578 gtx_clk_ibuf/O
10.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_16_s1/CLK
10.349 -0.064 tSu 1 u_triple_speed_mac/u_mac_tx_ctrl/u_crc_gen/crc_reg_16_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 4.207
Data Arrival Time 6.141
Data Required Time 10.349
From u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_0_s3
To u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0
Launch Clk gtx_clk[R]
Latch Clk gtx_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 gtx_clk
0.000 0.000 tCL RR 1 gtx_clk_ibuf/I
0.000 0.000 tINS RR 578 gtx_clk_ibuf/O
0.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_0_s3/CLK
0.795 0.382 tC2Q RR 40 u_triple_speed_mac/u_mac_tx_ctrl/frm_byte_cnt_0_s3/Q
1.207 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1820_s2/I0
1.786 0.579 tINS RR 4 u_triple_speed_mac/u_mac_tx_ctrl/n1820_s2/F
2.199 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s10/I1
2.766 0.567 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s10/F
3.179 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s5/I1
3.746 0.567 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s5/F
4.159 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s2/I0
4.738 0.579 tINS RR 2 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s2/F
5.150 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s1/I0
5.729 0.579 tINS RR 1 u_triple_speed_mac/u_mac_tx_ctrl/n1307_s1/F
6.141 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 gtx_clk
10.000 0.000 tCL RR 1 gtx_clk_ibuf/I
10.000 0.000 tINS RR 578 gtx_clk_ibuf/O
10.413 0.413 tNET RR 1 u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0/CLK
10.349 -0.064 tSu 1 u_triple_speed_mac/u_mac_tx_ctrl/clr_retrans_cnt_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.871, 50.120%; route: 2.475, 43.203%; tC2Q: 0.382, 6.677%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%