Timing Messages

Report Title Timing Analysis Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\SPI_JTAG\ref_ip\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2024\SPI_JTAG\ref_ip\fpga_project\src\fpga_project.cst
Timing Constraint File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Mon May 6 14:01:11 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C7/I6
Hold Delay Model Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed 1145
Numbers of Endpoints Analyzed 574
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
u_OSC/osc_inst/OSCOUT.default_clk Base 40.000 25.000 0.000 20.000 u_OSC/osc_inst/OSCOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_OSC/osc_inst/OSCOUT.default_clk 25.000(MHz) 105.094(MHz) 9 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
u_OSC/osc_inst/OSCOUT.default_clk Setup 0.000 0
u_OSC/osc_inst/OSCOUT.default_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 30.485 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 9.377
2 30.906 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 8.798
3 32.271 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.697
4 32.271 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.697
5 32.271 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_9_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.697
6 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
7 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_1_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
8 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
9 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
10 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
11 32.547 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_10_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.421
12 32.819 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_8_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.149
13 32.819 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_12_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.149
14 32.823 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.145
15 32.823 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_11_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 7.145
16 33.080 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.623
17 33.098 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_14_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.869
18 33.123 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.581
19 33.124 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_15_s1/CE u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.844
20 33.165 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.539
21 33.175 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[10] u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.793
22 33.207 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.496
23 33.216 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[12] u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.752
24 33.217 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[9] u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.751
25 33.249 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 6.454

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
2 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
3 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
4 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
5 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
6 0.524 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
7 0.524 led_s2/Q led_s2/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.524
8 0.525 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
9 0.525 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
10 0.525 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
11 0.525 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
12 0.525 inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/Q inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.525
13 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
14 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
15 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
16 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
17 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
18 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
19 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
20 0.526 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.526
21 0.528 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.528
22 0.531 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.531
23 0.541 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.541
24 0.542 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.542
25 0.542 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/D u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 0.542

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 38.166 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
2 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
3 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
4 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
5 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
6 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
7 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
8 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
9 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
10 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
11 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
12 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
13 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
14 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
15 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
16 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
17 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
18 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
19 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
20 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
21 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
22 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
23 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
24 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682
25 38.286 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 40.000 0.000 1.682

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
2 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
3 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
4 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
5 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
6 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
7 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
8 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
9 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
10 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
11 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
12 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
13 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
14 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
15 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
16 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
17 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
18 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
19 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
20 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
21 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
22 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
23 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
24 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196
25 1.187 inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR u_OSC/osc_inst/OSCOUT.default_clk:[R] u_OSC/osc_inst/OSCOUT.default_clk:[R] 0.000 0.000 1.196

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk led_cnt_30_s0
2 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk led_cnt_28_s0
3 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk led_cnt_24_s0
4 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk led_cnt_16_s0
5 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk led_cnt_0_s0
6 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_3_s1
7 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_6_s0
8 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_7_s0
9 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1
10 19.017 19.943 0.926 Low Pulse Width u_OSC/osc_inst/OSCOUT.default_clk inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 30.485
Data Arrival Time 9.557
Data Required Time 40.042
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.520 0.340 tC2Q RF 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.596 1.076 tNET FF 1 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.205 0.609 tINS FF 6 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.421 1.215 tNET FF 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.015 0.594 tINS FR 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.325 0.310 tNET RR 2 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
4.733 0.408 tINS RR 1 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.733 0.000 tNET RR 2 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.775 0.042 tINS RF 1 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.775 0.000 tNET FF 2 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.817 0.042 tINS FF 1 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.817 0.000 tNET FF 2 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.859 0.042 tINS FF 1 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.859 0.000 tNET FF 2 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.902 0.042 tINS FF 1 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.902 0.000 tNET FF 2 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.944 0.042 tINS FF 1 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.944 0.000 tNET FF 2 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.986 0.042 tINS FF 1 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.986 0.000 tNET FF 2 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.403 0.417 tINS FF 3 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/SUM
6.020 0.616 tNET FF 2 R12C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/I0
6.730 0.710 tINS FF 1 R12C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
6.730 0.000 tNET FF 2 R12C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
6.772 0.042 tINS FF 1 R12C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
6.772 0.000 tNET FF 2 R12C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
6.814 0.042 tINS FF 1 R12C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
6.814 0.000 tNET FF 2 R12C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
6.856 0.042 tINS FF 1 R12C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
6.856 0.000 tNET FF 2 R12C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
6.899 0.042 tINS FF 2 R12C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
7.916 1.017 tNET FF 1 R12C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/I2
8.702 0.786 tINS FR 1 R12C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/F
9.557 0.855 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.042 -0.139 tSu 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.947, 42.089%; route: 5.091, 54.289%; tC2Q: 0.340, 3.622%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path2

Path Summary:

Slack 30.906
Data Arrival Time 8.978
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.520 0.340 tC2Q RF 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.596 1.076 tNET FF 1 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.205 0.609 tINS FF 6 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.421 1.215 tNET FF 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.015 0.594 tINS FR 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.325 0.310 tNET RR 2 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
4.733 0.408 tINS RR 1 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.733 0.000 tNET RR 2 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.775 0.042 tINS RF 1 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.775 0.000 tNET FF 2 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.817 0.042 tINS FF 1 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.817 0.000 tNET FF 2 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.859 0.042 tINS FF 1 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.859 0.000 tNET FF 2 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.902 0.042 tINS FF 1 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.902 0.000 tNET FF 2 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.944 0.042 tINS FF 1 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.944 0.000 tNET FF 2 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.986 0.042 tINS FF 1 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.986 0.000 tNET FF 2 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.403 0.417 tINS FF 3 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/SUM
6.020 0.616 tNET FF 2 R12C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/I0
6.730 0.710 tINS FF 1 R12C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
6.730 0.000 tNET FF 2 R12C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
6.772 0.042 tINS FF 1 R12C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
6.772 0.000 tNET FF 2 R12C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
6.814 0.042 tINS FF 1 R12C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
6.814 0.000 tNET FF 2 R12C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
6.856 0.042 tINS FF 1 R12C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
6.856 0.000 tNET FF 2 R12C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
6.899 0.042 tINS FF 2 R12C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.164 1.265 tNET FF 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/I0
8.978 0.814 tINS FF 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/F
8.978 0.000 tNET FF 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
39.884 -0.296 tSu 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 9
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.975, 45.178%; route: 4.483, 50.961%; tC2Q: 0.340, 3.860%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path3

Path Summary:

Slack 32.271
Data Arrival Time 7.877
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_2_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.877 1.689 tNET RR 1 R16C14[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C14[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CLK
40.148 -0.032 tSu 1 R16C14[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 32.560%; route: 4.851, 63.028%; tC2Q: 0.340, 4.413%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path4

Path Summary:

Slack 32.271
Data Arrival Time 7.877
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_3_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.877 1.689 tNET RR 1 R16C14[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C14[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CLK
40.148 -0.032 tSu 1 R16C14[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 32.560%; route: 4.851, 63.028%; tC2Q: 0.340, 4.413%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path5

Path Summary:

Slack 32.271
Data Arrival Time 7.877
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_9_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.877 1.689 tNET RR 1 R16C14[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C14[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_9_s1/CLK
40.148 -0.032 tSu 1 R16C14[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 32.560%; route: 4.851, 63.028%; tC2Q: 0.340, 4.413%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path6

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
40.148 -0.032 tSu 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path7

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R16C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_1_s1/CLK
40.148 -0.032 tSu 1 R16C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path8

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_5_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R16C12[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C12[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CLK
40.148 -0.032 tSu 1 R16C12[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path9

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_6_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R16C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CLK
40.148 -0.032 tSu 1 R16C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path10

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_7_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R15C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R15C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CLK
40.148 -0.032 tSu 1 R15C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path11

Path Summary:

Slack 32.547
Data Arrival Time 7.602
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_10_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.602 1.413 tNET RR 1 R16C12[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_10_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C12[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_10_s1/CLK
40.148 -0.032 tSu 1 R16C12[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 33.770%; route: 4.575, 61.654%; tC2Q: 0.340, 4.577%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path12

Path Summary:

Slack 32.819
Data Arrival Time 7.329
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_8_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.329 1.141 tNET RR 1 R17C13[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_8_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R17C13[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_8_s1/CLK
40.148 -0.032 tSu 1 R17C13[3][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 35.056%; route: 4.303, 60.193%; tC2Q: 0.340, 4.751%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path13

Path Summary:

Slack 32.819
Data Arrival Time 7.329
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_12_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.329 1.141 tNET RR 1 R17C13[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_12_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R17C13[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_12_s1/CLK
40.148 -0.032 tSu 1 R17C13[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_12_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 35.056%; route: 4.303, 60.193%; tC2Q: 0.340, 4.751%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path14

Path Summary:

Slack 32.823
Data Arrival Time 7.326
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_4_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.326 1.137 tNET RR 1 R17C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R17C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CLK
40.148 -0.032 tSu 1 R17C12[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 35.073%; route: 4.300, 60.174%; tC2Q: 0.340, 4.753%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path15

Path Summary:

Slack 32.823
Data Arrival Time 7.326
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_11_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.326 1.137 tNET RR 1 R17C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_11_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R17C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_11_s1/CLK
40.148 -0.032 tSu 1 R17C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 35.073%; route: 4.300, 60.174%; tC2Q: 0.340, 4.753%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path16

Path Summary:

Slack 33.080
Data Arrival Time 6.804
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.520 0.340 tC2Q RF 9 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
1.121 0.601 tNET FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/I0
1.936 0.814 tINS FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/F
3.013 1.077 tNET FF 1 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
3.777 0.765 tINS FF 5 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
3.798 0.020 tNET FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
4.612 0.814 tINS FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
5.922 1.310 tNET FF 2 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
5.964 0.042 tINS FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
5.964 0.000 tNET FF 2 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.006 0.042 tINS FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.006 0.000 tNET FF 2 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.049 0.042 tINS FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.049 0.000 tNET FF 2 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.091 0.042 tINS FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.091 0.000 tNET FF 2 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.133 0.042 tINS FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.133 0.000 tNET FF 2 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.175 0.042 tINS FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.175 0.000 tNET FF 2 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.218 0.042 tINS FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.218 0.000 tNET FF 2 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.260 0.042 tINS FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.260 0.000 tNET FF 2 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.302 0.042 tINS FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.302 0.000 tNET FF 2 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
6.344 0.042 tINS FF 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
6.344 0.000 tNET FF 2 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
6.387 0.042 tINS FF 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/COUT
6.387 0.000 tNET FF 2 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/CIN
6.804 0.417 tINS FF 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/SUM
6.804 0.000 tNET FF 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
39.884 -0.296 tSu 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.275, 49.451%; route: 3.008, 45.422%; tC2Q: 0.340, 5.128%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path17

Path Summary:

Slack 33.098
Data Arrival Time 7.050
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_14_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.050 0.861 tNET RR 1 R14C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_14_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R14C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_14_s1/CLK
40.148 -0.032 tSu 1 R14C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_14_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 36.481%; route: 4.024, 58.575%; tC2Q: 0.340, 4.944%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path18

Path Summary:

Slack 33.123
Data Arrival Time 6.761
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.520 0.340 tC2Q RF 9 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
1.121 0.601 tNET FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/I0
1.936 0.814 tINS FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/F
3.013 1.077 tNET FF 1 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
3.777 0.765 tINS FF 5 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
3.798 0.020 tNET FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
4.612 0.814 tINS FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
5.922 1.310 tNET FF 2 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
5.964 0.042 tINS FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
5.964 0.000 tNET FF 2 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.006 0.042 tINS FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.006 0.000 tNET FF 2 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.049 0.042 tINS FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.049 0.000 tNET FF 2 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.091 0.042 tINS FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.091 0.000 tNET FF 2 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.133 0.042 tINS FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.133 0.000 tNET FF 2 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.175 0.042 tINS FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.175 0.000 tNET FF 2 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.218 0.042 tINS FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.218 0.000 tNET FF 2 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.260 0.042 tINS FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.260 0.000 tNET FF 2 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.302 0.042 tINS FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.302 0.000 tNET FF 2 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
6.344 0.042 tINS FF 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
6.344 0.000 tNET FF 2 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
6.761 0.417 tINS FF 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/SUM
6.761 0.000 tNET FF 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
39.884 -0.296 tSu 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.233, 49.126%; route: 3.008, 45.713%; tC2Q: 0.340, 5.161%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path19

Path Summary:

Slack 33.124
Data Arrival Time 7.025
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_15_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.520 0.340 tC2Q RF 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
1.125 0.605 tNET FF 1 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/I0
1.890 0.765 tINS FF 8 R16C14[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n996_s7/F
2.505 0.615 tNET FF 1 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/I0
3.319 0.814 tINS FF 9 R17C12[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s4/F
3.931 0.612 tNET FF 1 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/I0
4.395 0.464 tINS FF 3 R16C11[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s1/F
5.725 1.330 tNET FF 1 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/I0
6.188 0.463 tINS FR 16 R15C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n834_s0/F
7.025 0.836 tNET RR 1 R16C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_15_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_15_s1/CLK
40.148 -0.032 tSu 1 R16C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.506, 36.615%; route: 3.999, 58.423%; tC2Q: 0.340, 4.962%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path20

Path Summary:

Slack 33.165
Data Arrival Time 6.719
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.520 0.340 tC2Q RF 9 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
1.121 0.601 tNET FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/I0
1.936 0.814 tINS FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/F
3.013 1.077 tNET FF 1 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
3.777 0.765 tINS FF 5 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
3.798 0.020 tNET FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
4.612 0.814 tINS FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
5.922 1.310 tNET FF 2 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
5.964 0.042 tINS FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
5.964 0.000 tNET FF 2 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.006 0.042 tINS FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.006 0.000 tNET FF 2 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.049 0.042 tINS FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.049 0.000 tNET FF 2 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.091 0.042 tINS FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.091 0.000 tNET FF 2 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.133 0.042 tINS FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.133 0.000 tNET FF 2 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.175 0.042 tINS FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.175 0.000 tNET FF 2 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.218 0.042 tINS FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.218 0.000 tNET FF 2 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.260 0.042 tINS FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.260 0.000 tNET FF 2 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.302 0.042 tINS FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.302 0.000 tNET FF 2 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
6.719 0.417 tINS FF 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/SUM
6.719 0.000 tNET FF 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
39.884 -0.296 tSu 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.191, 48.798%; route: 3.008, 46.008%; tC2Q: 0.340, 5.194%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path21

Path Summary:

Slack 33.175
Data Arrival Time 6.974
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.520 0.340 tC2Q RF 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.596 1.076 tNET FF 1 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.205 0.609 tINS FF 6 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.421 1.215 tNET FF 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.015 0.594 tINS FR 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.325 0.310 tNET RR 2 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
4.733 0.408 tINS RR 1 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.733 0.000 tNET RR 2 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.775 0.042 tINS RF 1 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.775 0.000 tNET FF 2 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.817 0.042 tINS FF 1 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.817 0.000 tNET FF 2 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.859 0.042 tINS FF 1 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.859 0.000 tNET FF 2 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.902 0.042 tINS FF 1 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.902 0.000 tNET FF 2 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.944 0.042 tINS FF 1 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.944 0.000 tNET FF 2 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.986 0.042 tINS FF 1 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.986 0.000 tNET FF 2 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.403 0.417 tINS FF 3 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/SUM
6.974 1.570 tNET FF 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.148 -0.032 tSu 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.282, 33.585%; route: 4.172, 61.415%; tC2Q: 0.340, 4.999%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path22

Path Summary:

Slack 33.207
Data Arrival Time 6.677
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.520 0.340 tC2Q RF 9 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
1.121 0.601 tNET FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/I0
1.936 0.814 tINS FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/F
3.013 1.077 tNET FF 1 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
3.777 0.765 tINS FF 5 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
3.798 0.020 tNET FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
4.612 0.814 tINS FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
5.922 1.310 tNET FF 2 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
5.964 0.042 tINS FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
5.964 0.000 tNET FF 2 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.006 0.042 tINS FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.006 0.000 tNET FF 2 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.049 0.042 tINS FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.049 0.000 tNET FF 2 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.091 0.042 tINS FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.091 0.000 tNET FF 2 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.133 0.042 tINS FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.133 0.000 tNET FF 2 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.175 0.042 tINS FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.175 0.000 tNET FF 2 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.218 0.042 tINS FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.218 0.000 tNET FF 2 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.260 0.042 tINS FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.260 0.000 tNET FF 2 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.677 0.417 tINS FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/SUM
6.677 0.000 tNET FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
39.884 -0.296 tSu 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.149, 48.465%; route: 3.008, 46.307%; tC2Q: 0.340, 5.228%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path23

Path Summary:

Slack 33.216
Data Arrival Time 6.932
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.520 0.340 tC2Q RF 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.596 1.076 tNET FF 1 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.205 0.609 tINS FF 6 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.421 1.215 tNET FF 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.015 0.594 tINS FR 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.325 0.310 tNET RR 2 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
4.733 0.408 tINS RR 1 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.733 0.000 tNET RR 2 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.775 0.042 tINS RF 1 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.775 0.000 tNET FF 2 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.817 0.042 tINS FF 1 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.817 0.000 tNET FF 2 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.859 0.042 tINS FF 1 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.859 0.000 tNET FF 2 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.902 0.042 tINS FF 1 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.902 0.000 tNET FF 2 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.944 0.042 tINS FF 1 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.944 0.000 tNET FF 2 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.986 0.042 tINS FF 1 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.986 0.000 tNET FF 2 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.028 0.042 tINS FF 1 R13C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/COUT
5.028 0.000 tNET FF 2 R13C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/CIN
5.071 0.042 tINS FF 1 R13C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/COUT
5.071 0.000 tNET FF 2 R13C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/CIN
5.488 0.417 tINS FF 3 R13C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/SUM
6.932 1.444 tNET FF 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[12]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.148 -0.032 tSu 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.366, 35.044%; route: 4.046, 59.926%; tC2Q: 0.340, 5.030%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path24

Path Summary:

Slack 33.217
Data Arrival Time 6.932
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.520 0.340 tC2Q RF 1 R16C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.596 1.076 tNET FF 1 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.205 0.609 tINS FF 6 R16C11[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.421 1.215 tNET FF 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.015 0.594 tINS FR 1 R13C7[3][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.325 0.310 tNET RR 2 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
4.733 0.408 tINS RR 1 R13C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
4.733 0.000 tNET RR 2 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
4.775 0.042 tINS RF 1 R13C7[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
4.775 0.000 tNET FF 2 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
4.817 0.042 tINS FF 1 R13C7[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
4.817 0.000 tNET FF 2 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
4.859 0.042 tINS FF 1 R13C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
4.859 0.000 tNET FF 2 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.902 0.042 tINS FF 1 R13C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.902 0.000 tNET FF 2 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.944 0.042 tINS FF 1 R13C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.944 0.000 tNET FF 2 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
5.361 0.417 tINS FF 3 R13C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/SUM
6.932 1.570 tNET FF 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/ADB[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.148 -0.032 tSu 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 2.239, 33.169%; route: 4.172, 61.800%; tC2Q: 0.340, 5.031%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path25

Path Summary:

Slack 33.249
Data Arrival Time 6.635
Data Required Time 39.884
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.520 0.340 tC2Q RF 9 R12C9[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
1.121 0.601 tNET FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/I0
1.936 0.814 tINS FF 1 R13C11[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_wren_s1/F
3.013 1.077 tNET FF 1 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
3.777 0.765 tINS FF 5 R16C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
3.798 0.020 tNET FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
4.612 0.814 tINS FF 1 R16C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
5.922 1.310 tNET FF 2 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
5.964 0.042 tINS FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
5.964 0.000 tNET FF 2 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.006 0.042 tINS FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.006 0.000 tNET FF 2 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.049 0.042 tINS FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.049 0.000 tNET FF 2 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.091 0.042 tINS FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.091 0.000 tNET FF 2 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.133 0.042 tINS FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.133 0.000 tNET FF 2 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.175 0.042 tINS FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.175 0.000 tNET FF 2 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.218 0.042 tINS FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.218 0.000 tNET FF 2 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.635 0.417 tINS FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/SUM
6.635 0.000 tNET FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
39.884 -0.296 tSu 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 7
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 3.106, 48.127%; route: 3.008, 46.611%; tC2Q: 0.340, 5.262%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.383 0.247 tC2Q RR 5 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/Q
0.385 0.002 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1005_s4/I0
0.661 0.276 tINS RF 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1005_s4/F
0.661 0.000 tNET FF 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1/CLK
0.136 0.000 tHld 1 R15C12[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/send_counter_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/CLK
0.383 0.247 tC2Q RR 5 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/Q
0.385 0.002 tNET RR 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n364_s11/I1
0.661 0.276 tINS RF 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n364_s11/F
0.661 0.000 tNET FF 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0/CLK
0.136 0.000 tHld 1 R14C15[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/CLK
0.383 0.247 tC2Q RR 4 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/Q
0.385 0.002 tNET RR 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n346_s11/I1
0.661 0.276 tINS RF 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n346_s11/F
0.661 0.000 tNET FF 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0/CLK
0.136 0.000 tHld 1 R14C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/CLK
0.383 0.247 tC2Q RR 3 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/Q
0.385 0.002 tNET RR 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n22_s4/I0
0.661 0.276 tINS RF 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n22_s4/F
0.661 0.000 tNET FF 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6/CLK
0.136 0.000 tHld 1 R16C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/frist_reg_s6

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/CLK
0.383 0.247 tC2Q RR 4 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/Q
0.385 0.002 tNET RR 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n222_s2/I3
0.661 0.276 tINS RF 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n222_s2/F
0.661 0.000 tNET FF 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1/CLK
0.136 0.000 tHld 1 R14C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/CLK
0.383 0.247 tC2Q RR 3 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/Q
0.385 0.002 tNET RR 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n183_s2/I2
0.661 0.276 tINS RF 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n183_s2/F
0.661 0.000 tNET FF 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/CLK
0.136 0.000 tHld 1 R15C18[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.136
From led_s2
To led_s2
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C4[0][A] led_s2/CLK
0.383 0.247 tC2Q RR 2 R15C4[0][A] led_s2/Q
0.385 0.002 tNET RR 1 R15C4[0][A] n135_s3/I0
0.661 0.276 tINS RF 1 R15C4[0][A] n135_s3/F
0.661 0.000 tNET FF 1 R15C4[0][A] led_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C4[0][A] led_s2/CLK
0.136 0.000 tHld 1 R15C4[0][A] led_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/CLK
0.383 0.247 tC2Q RR 4 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/Q
0.386 0.003 tNET RR 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1061_s4/I1
0.662 0.276 tINS RF 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1061_s4/F
0.662 0.000 tNET FF 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0/CLK
0.136 0.000 tHld 1 R17C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/CLK
0.383 0.247 tC2Q RR 3 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/Q
0.386 0.003 tNET RR 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n319_s13/I2
0.662 0.276 tINS RF 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n319_s13/F
0.662 0.000 tNET FF 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0/CLK
0.136 0.000 tHld 1 R12C13[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/CLK_RXRDY_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/CLK
0.383 0.247 tC2Q RR 4 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/Q
0.386 0.003 tNET RR 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n352_s11/I1
0.662 0.276 tINS RF 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n352_s11/F
0.662 0.000 tNET FF 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0/CLK
0.136 0.000 tHld 1 R12C14[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/CLK
0.383 0.247 tC2Q RR 8 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/Q
0.386 0.003 tNET RR 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n90_s4/I2
0.662 0.276 tINS RF 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n90_s4/F
0.662 0.000 tNET FF 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3/CLK
0.136 0.000 tHld 1 R17C17[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack 0.525
Data Arrival Time 0.662
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/counter_3_s1
To inst_SPI_JTAG/inst_GW_SPI/counter_3_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/CLK
0.383 0.247 tC2Q RR 4 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/Q
0.386 0.003 tNET RR 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/n26_s1/I3
0.662 0.276 tINS RF 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/n26_s1/F
0.662 0.000 tNET FF 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/counter_3_s1/CLK
0.136 0.000 tHld 1 R11C12[1][A] inst_SPI_JTAG/inst_GW_SPI/counter_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/CLK
0.383 0.247 tC2Q RR 12 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/Q
0.387 0.003 tNET RR 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1113_s5/I0
0.663 0.276 tINS RF 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1113_s5/F
0.663 0.000 tNET FF 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3/CLK
0.136 0.000 tHld 1 R12C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/CLK
0.383 0.247 tC2Q RR 6 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/Q
0.387 0.003 tNET RR 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1111_s3/I0
0.663 0.276 tINS RF 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1111_s3/F
0.663 0.000 tNET FF 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1/CLK
0.136 0.000 tHld 1 R12C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/t_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/CLK
0.383 0.247 tC2Q RR 12 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/Q
0.387 0.003 tNET RR 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n829_s4/I0
0.663 0.276 tINS RF 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n829_s4/F
0.663 0.000 tNET FF 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1/CLK
0.136 0.000 tHld 1 R15C10[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/length_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/CLK
0.383 0.247 tC2Q RR 4 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/Q
0.387 0.003 tNET RR 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1059_s2/I2
0.663 0.276 tINS RF 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1059_s2/F
0.663 0.000 tNET FF 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0/CLK
0.136 0.000 tHld 1 R17C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/clk_i_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/CLK
0.383 0.247 tC2Q RR 5 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/Q
0.387 0.003 tNET RR 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n372_s11/I0
0.663 0.276 tINS RF 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n372_s11/F
0.663 0.000 tNET FF 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0/CLK
0.136 0.000 tHld 1 R13C15[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/CLK
0.383 0.247 tC2Q RR 4 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/Q
0.387 0.003 tNET RR 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n184_s5/I1
0.663 0.276 tINS RF 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n184_s5/F
0.663 0.000 tNET FF 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3/CLK
0.136 0.000 tHld 1 R15C18[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/CLK
0.383 0.247 tC2Q RR 8 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/Q
0.387 0.003 tNET RR 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n88_s4/I2
0.663 0.276 tINS RF 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n88_s4/F
0.663 0.000 tNET FF 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3/CLK
0.136 0.000 tHld 1 R16C17[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/spi_data_2_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack 0.526
Data Arrival Time 0.663
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/CLK
0.383 0.247 tC2Q RR 6 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/Q
0.387 0.003 tNET RR 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n223_s2/I2
0.663 0.276 tINS RF 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/n223_s2/F
0.663 0.000 tNET FF 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1/CLK
0.136 0.000 tHld 1 R11C16[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack 0.528
Data Arrival Time 0.664
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/CLK
0.383 0.247 tC2Q RR 8 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/Q
0.389 0.005 tNET RR 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1052_s4/I0
0.664 0.276 tINS RF 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n1052_s4/F
0.664 0.000 tNET FF 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5/CLK
0.136 0.000 tHld 1 R16C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/TCK_s5

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack 0.531
Data Arrival Time 0.667
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/CLK
0.383 0.247 tC2Q RR 35 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/Q
0.391 0.008 tNET RR 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n850_s0/I2
0.667 0.276 tINS RF 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/n850_s0/F
0.667 0.000 tNET FF 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1/CLK
0.136 0.000 tHld 1 R16C11[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/User_model_state_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.276, 51.958%; route: 0.008, 1.484%; tC2Q: 0.247, 46.558%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack 0.541
Data Arrival Time 0.677
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/CLK
0.383 0.247 tC2Q RR 2 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/Q
0.385 0.002 tNET RR 2 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_11_s/I1
0.677 0.292 tINS RF 1 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_11_s/SUM
0.677 0.000 tNET FF 1 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0/CLK
0.136 0.000 tHld 1 R11C9[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.292, 53.995%; route: 0.002, 0.324%; tC2Q: 0.247, 45.681%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack 0.542
Data Arrival Time 0.678
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
0.383 0.247 tC2Q RR 3 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/Q
0.386 0.003 tNET RR 2 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_3_s/I1
0.678 0.292 tINS RF 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_3_s/SUM
0.678 0.000 tNET FF 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
0.136 0.000 tHld 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack 0.542
Data Arrival Time 0.678
Data Required Time 0.136
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
0.383 0.247 tC2Q RR 3 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/Q
0.386 0.003 tNET RR 2 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_5_s/I1
0.678 0.292 tINS RF 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_next_5_s/SUM
0.678 0.000 tNET FF 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
0.136 0.000 tHld 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 38.166
Data Arrival Time 1.863
Data Required Time 40.029
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 8 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.029 -0.152 tSu 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path2

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLK
40.148 -0.032 tSu 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path3

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
40.148 -0.032 tSu 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path4

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLK
40.148 -0.032 tSu 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path5

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLK
40.148 -0.032 tSu 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path6

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLK
40.148 -0.032 tSu 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path7

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
40.148 -0.032 tSu 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path8

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLK
40.148 -0.032 tSu 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path9

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
40.148 -0.032 tSu 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path10

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
40.148 -0.032 tSu 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path11

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
40.148 -0.032 tSu 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path12

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
40.148 -0.032 tSu 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path13

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
40.148 -0.032 tSu 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path14

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
40.148 -0.032 tSu 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path15

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLK
40.148 -0.032 tSu 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path16

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLK
40.148 -0.032 tSu 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path17

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLK
40.148 -0.032 tSu 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path18

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
40.148 -0.032 tSu 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path19

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLK
40.148 -0.032 tSu 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path20

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
40.148 -0.032 tSu 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path21

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLK
40.148 -0.032 tSu 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path22

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLK
40.148 -0.032 tSu 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path23

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLK
40.148 -0.032 tSu 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path24

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLK
40.148 -0.032 tSu 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Path25

Path Summary:

Slack 38.286
Data Arrival Time 1.863
Data Required Time 40.148
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.180 0.180 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.520 0.340 tC2Q RF 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.863 1.343 tNET FF 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.000 40.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
40.180 0.180 tNET RR 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLK
40.148 -0.032 tSu 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 40.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.343, 79.812%; tC2Q: 0.340, 20.188%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.180, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 8 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
0.146 0.009 tHld 1 BSRAM_R10[2] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLK
0.146 0.009 tHld 1 R16C5[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.146 0.009 tHld 1 R16C5[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.146 0.009 tHld 1 R16C5[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLK
0.146 0.009 tHld 1 R16C5[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLK
0.146 0.009 tHld 1 R16C5[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.146 0.009 tHld 1 R16C5[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLK
0.146 0.009 tHld 1 R16C6[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
0.146 0.009 tHld 1 R16C6[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
0.146 0.009 tHld 1 R16C6[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
0.146 0.009 tHld 1 R16C6[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
0.146 0.009 tHld 1 R16C6[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
0.146 0.009 tHld 1 R16C6[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
0.146 0.009 tHld 1 R16C7[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLK
0.146 0.009 tHld 1 R11C7[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLK
0.146 0.009 tHld 1 R11C7[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLK
0.146 0.009 tHld 1 R11C7[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
0.146 0.009 tHld 1 R11C8[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLK
0.146 0.009 tHld 1 R11C8[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
0.146 0.009 tHld 1 R11C8[1][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLK
0.146 0.009 tHld 1 R11C8[1][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLK
0.146 0.009 tHld 1 R11C8[2][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLK
0.146 0.009 tHld 1 R11C8[2][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLK
0.146 0.009 tHld 1 R11C9[0][A] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack 1.187
Data Arrival Time 1.332
Data Required Time 0.146
From inst_SPI_JTAG/inst_GW_SPI/RST_N_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/CLK
0.383 0.247 tC2Q RR 183 R11C11[0][A] inst_SPI_JTAG/inst_GW_SPI/RST_N_s0/Q
1.332 0.949 tNET RR 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 R20C0 u_OSC/osc_inst/OSCOUT
0.136 0.136 tNET RR 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLK
0.146 0.009 tHld 1 R11C9[0][B] inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.949, 79.344%; tC2Q: 0.247, 20.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.136, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: led_cnt_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_30_s0/CLK

MPW2

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: led_cnt_28_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_28_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_28_s0/CLK

MPW3

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: led_cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_24_s0/CLK

MPW4

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: led_cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: led_cnt_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF led_cnt_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR led_cnt_0_s0/CLK

MPW6

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_3_s1

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_3_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/tx_cnt_3_s1/CLK

MPW7

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_6_s0/CLK

MPW8

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_7_s0/CLK

MPW9

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rx_cnt_1_s1/CLK

MPW10

MPW Summary:

Slack: 19.017
Actual Width: 19.943
Required Width: 0.926
Type: Low Pulse Width
Clock: u_OSC/osc_inst/OSCOUT.default_clk
Objects: inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
20.000 0.000 tCL FF u_OSC/osc_inst/OSCOUT
20.193 0.193 tNET FF inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
40.000 0.000 active clock edge time
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR u_OSC/osc_inst/OSCOUT
40.136 0.136 tNET RR inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/counter_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
225 GW_OSC_CLK_d 30.485 0.489
183 RST_N 36.891 1.702
43 CS_reg 35.212 2.045
35 User_model_state[1] 34.350 1.015
32 n20_16 33.678 1.033
16 n342_21 33.491 1.249
16 n834_3 32.271 2.054
16 User_model_state[0] 34.004 1.000
13 FIFO_model_state[0] 35.791 0.658
13 FIFO_model_state[1] 35.465 0.622

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R16C17 88.89%
R14C3 86.11%
R11C8 81.94%
R13C17 79.17%
R15C13 77.78%
R16C6 77.78%
R16C5 75.00%
R15C18 73.61%
R12C3 70.83%
R14C4 70.83%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command