Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\SPI_JTAG\ref_ip\fpga_project\src\goconfig_spi\goconfig_spi.v
E:\work_files\IP_A_new\GoConfig\00_2024\SPI_JTAG\ref_ip\fpga_project\src\gowin_osc\gowin_osc.v
E:\work_files\IP_A_new\GoConfig\00_2024\SPI_JTAG\ref_ip\fpga_project\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Mon May 6 14:01:09 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 294.484MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 294.484MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 294.484MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 294.484MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 294.484MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 294.484MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 294.484MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 294.484MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 294.484MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 294.484MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 294.484MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 294.484MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 294.484MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 294.484MB
Total Time and Memory Usage CPU time = 0h 0m 0.325s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 294.484MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 12
I/O Buf 12
    IBUF 4
    OBUF 8
Register 222
    DFF 5
    DFFE 4
    DFFR 32
    DFFP 2
    DFFPE 9
    DFFC 61
    DFFCE 109
LUT 335
    LUT2 58
    LUT3 87
    LUT4 190
ALU 79
    ALU 79
INV 5
    INV 5
BSRAM 1
    SDPB 1
CLOCK 1
    OSCO 1

Resource Utilization Summary

Resource Usage Utilization
Logic 419(340 LUT, 79 ALU) / 2304 19%
Register 222 / 2643 9%
  --Register as Latch 0 / 2643 0%
  --Register as FF 222 / 2355 10%
BSRAM 1 / 4 25%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
u_OSC/osc_inst/OSCOUT.default_clk Base 40.000 25.0 0.000 20.000 u_OSC/osc_inst/OSCOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_OSC/osc_inst/OSCOUT.default_clk 25.000(MHz) 103.935(MHz) 8 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 30.379
Data Arrival Time 9.863
Data Required Time 40.242
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.878 0.340 tC2Q RF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.589 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.403 0.814 tINS FF 6 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.115 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
3.929 0.814 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.640 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.415 0.774 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.415 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.457 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.457 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
5.499 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
5.499 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
5.541 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
5.541 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
5.584 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
5.584 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
5.626 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
5.626 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
5.668 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
5.668 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.710 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/COUT
5.710 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/CIN
5.753 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/COUT
5.753 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/CIN
5.795 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/COUT
5.795 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/CIN
5.837 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/COUT
5.837 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/CIN
6.254 0.417 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/SUM
6.966 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/I0
7.676 0.710 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.387 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/I0
9.152 0.765 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/F
9.863 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
40.242 -0.296 tSu 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.717, 50.587%; route: 4.268, 45.771%; tC2Q: 0.340, 3.642%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 30.880
Data Arrival Time 9.519
Data Required Time 40.399
From inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.878 0.340 tC2Q RF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.589 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.403 0.814 tINS FF 6 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.115 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
3.929 0.814 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.640 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.415 0.774 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.415 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.457 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.457 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
5.499 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
5.499 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
5.541 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
5.541 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
5.584 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
5.584 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
5.626 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
5.626 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
5.668 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
5.668 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
5.710 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/COUT
5.710 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/CIN
5.753 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/COUT
5.753 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/CIN
5.795 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/COUT
5.795 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/CIN
5.837 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/COUT
5.837 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/CIN
6.254 0.417 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/SUM
6.966 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/I0
7.676 0.710 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.387 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/I2
8.981 0.594 tINS FR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/F
9.519 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.399 -0.139 tSu 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.547, 50.625%; route: 4.095, 45.593%; tC2Q: 0.340, 3.782%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 32.322
Data Arrival Time 7.919
Data Required Time 40.242
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.878 0.340 tC2Q RF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/Q
1.589 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/I1
2.403 0.814 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/F
3.115 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I1
3.929 0.814 tINS FF 5 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
4.640 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/I2
5.249 0.609 tINS FF 12 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/F
5.961 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/I3
6.368 0.408 tINS FR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
6.368 0.000 tNET RR 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.411 0.042 tINS RF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.411 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.453 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.453 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.495 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.495 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.537 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.537 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.580 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.580 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.622 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.622 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.664 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.664 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.706 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.706 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
6.749 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
6.749 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
6.791 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/COUT
6.791 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/CIN
7.208 0.417 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/SUM
7.919 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
40.242 -0.296 tSu 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.485, 47.213%; route: 3.557, 48.186%; tC2Q: 0.340, 4.601%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 32.364
Data Arrival Time 7.877
Data Required Time 40.242
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.878 0.340 tC2Q RF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/Q
1.589 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/I1
2.403 0.814 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/F
3.115 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I1
3.929 0.814 tINS FF 5 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
4.640 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/I2
5.249 0.609 tINS FF 12 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/F
5.961 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/I3
6.368 0.408 tINS FR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
6.368 0.000 tNET RR 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.411 0.042 tINS RF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.411 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.453 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.453 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.495 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.495 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.537 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.537 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.580 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.580 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.622 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.622 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.664 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.664 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.706 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.706 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
6.749 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
6.749 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
7.166 0.417 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/SUM
7.877 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
40.242 -0.296 tSu 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.443, 46.909%; route: 3.557, 48.463%; tC2Q: 0.340, 4.628%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 32.407
Data Arrival Time 7.835
Data Required Time 40.242
From inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
To inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Latch Clk u_OSC/osc_inst/OSCOUT.default_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
0.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
0.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.878 0.340 tC2Q RF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/Q
1.589 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/I1
2.403 0.814 tINS FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s3/F
3.115 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I1
3.929 0.814 tINS FF 5 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
4.640 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/I2
5.249 0.609 tINS FF 12 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_s1/F
5.961 0.711 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/I3
6.368 0.408 tINS FR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
6.368 0.000 tNET RR 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
6.411 0.042 tINS RF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
6.411 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
6.453 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
6.453 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
6.495 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
6.495 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
6.537 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
6.537 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
6.580 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
6.580 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
6.622 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
6.622 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
6.664 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
6.664 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
6.706 0.042 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
6.706 0.000 tNET FF 2 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
7.123 0.417 tINS FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/SUM
7.835 0.711 tNET FF 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
40.000 0.000 u_OSC/osc_inst/OSCOUT.default_clk
40.000 0.000 tCL RR 225 u_OSC/osc_inst/OSCOUT
40.538 0.538 tNET RR 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
40.242 -0.296 tSu 1 inst_SPI_JTAG/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 40.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.400, 46.601%; route: 3.557, 48.745%; tC2Q: 0.340, 4.654%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%